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#pragma once
#define REG_ADD_OFF_STM32 (0x0000)
#define REG_ADD_OFF_STM32_CONFIG_START_ADD (0x0010)
#define REGADDOFF__FPGA_INFO (0x0020)
#define REGADDOFF__TTLIN (0x0100)
#define REGADDOFF__EXTERNAL_TIMECODE (0x0120)
#define REGADDOFF__EXTERNAL_GENLOCK (0x0130)
#define REGADDOFF__INTERNAL_TIMECODE (0x0300)
#define REGADDOFF__INTERNAL_GENLOCK (0x0310)
#define REGADDOFF__INTERNAL_CLOCK (0x0320)
#define REGADDOFF__TTLOUT1 (0x0200)
#define REGADDOFF__TTLOUT2 (0x0210)
#define REGADDOFF__TTLOUT3 (0x0220)
#define REGADDOFF__TTLOUT4 (0x0230)
#define REGADDOFF__TIMECODE_OUT (0x0240)
#define REGADDOFF__GENLOCK_OUT (0x0250)
#define REGADDOFF__CAMERA_SYNC_OUT (0x0260)
#define REGADDOFF__SYS_TIMECODE (0x0400)
#define REGADDOFF__SYS_GENLOCK (0x0410)
#define REGADDOFF__SYS_CLOCK (0x0420)
#define REGADDOFF__RECORD_SIG_GENERATOR (0x0500)
typedef enum { /**
* @brief * REG 0(16) �豸��Ϣ�����Ĵ��� */ ksoftware_version = 0, kmanufacturer0 = 1, kmanufacturer1 = 2, kproduct_type_id = 3, ksn_id0 = 4, ksn_id1 = 5, ksn_id2 = 6, kmac0 = 7, kmac1 = 8,
/**
* @brief * REG 16(32) STM32���üĴ���0 */ kstm32_obtaining_ip_mode = REG_ADD_OFF_STM32_CONFIG_START_ADD + 0, kstm32_ip = REG_ADD_OFF_STM32_CONFIG_START_ADD + 1, kstm32_gw = REG_ADD_OFF_STM32_CONFIG_START_ADD + 2, kstm32_netmask = REG_ADD_OFF_STM32_CONFIG_START_ADD + 3, kstm32_config0 = REG_ADD_OFF_STM32_CONFIG_START_ADD + 4, // bit0: timecode report enable, bit1: camera sync report enable
kstm32_camera_sync_signal_count = REG_ADD_OFF_STM32_CONFIG_START_ADD + 5, // д������ֵ֮������
kstm32_camera_sync_signal_count_report_period = REG_ADD_OFF_STM32_CONFIG_START_ADD + 6, // �ϱ����ڣ���λΪ֡��
kstm32_action0 = REG_ADD_OFF_STM32_CONFIG_START_ADD + 14, // action reg
kstm32_action_val0 = REG_ADD_OFF_STM32_CONFIG_START_ADD + 15, // action val reg
/**
* @brief * REG 48(32) FPGA���üĴ���0 */ kfpga_info_reg0 = REGADDOFF__FPGA_INFO + 0, kfpga_info_reg1 = REGADDOFF__FPGA_INFO + 1, kfpga_info_reg2 = REGADDOFF__FPGA_INFO + 2, kfpga_info_reg3 = REGADDOFF__FPGA_INFO + 3, kfpga_info_reg4 = REGADDOFF__FPGA_INFO + 4, kfpga_info_reg5 = REGADDOFF__FPGA_INFO + 5, kfpga_info_reg6 = REGADDOFF__FPGA_INFO + 6, kfpga_info_reg7 = REGADDOFF__FPGA_INFO + 7, kfpga_info_reg8 = REGADDOFF__FPGA_INFO + 8, kfpga_info_reg9 = REGADDOFF__FPGA_INFO + 9, kfpga_info_rega = REGADDOFF__FPGA_INFO + 10, kfpga_info_regb = REGADDOFF__FPGA_INFO + 11, kfpga_info_regc = REGADDOFF__FPGA_INFO + 12, kfpga_info_regd = REGADDOFF__FPGA_INFO + 13, kfpga_info_rege = REGADDOFF__FPGA_INFO + 14, kfpga_info_regf = REGADDOFF__FPGA_INFO + 15,
/*******************************************************************************
* TTL����ģ�� * *******************************************************************************/
k_ttlin_module = REGADDOFF__TTLIN + 0, k_ttlin_en_reg = REGADDOFF__TTLIN + 1, k_ttlin1_freq_detector_reg = REGADDOFF__TTLIN + 2, k_ttlin2_freq_detector_reg = REGADDOFF__TTLIN + 3, k_ttlin3_freq_detector_reg = REGADDOFF__TTLIN + 4, k_ttlin4_freq_detector_reg = REGADDOFF__TTLIN + 5, k_ttlin1_filter_factor_reg = REGADDOFF__TTLIN + 6, k_ttlin2_filter_factor_reg = REGADDOFF__TTLIN + 7, k_ttlin3_filter_factor_reg = REGADDOFF__TTLIN + 8, k_ttlin4_filter_factor_reg = REGADDOFF__TTLIN + 9,
/*******************************************************************************
* TTL����ģ�� * *******************************************************************************/
kreg_ttlout1_module = REGADDOFF__TTLOUT1 + 0, kreg_ttlout1_signal_process_mode = REGADDOFF__TTLOUT1 + 1, kreg_ttlout1_input_signal_select = REGADDOFF__TTLOUT1 + 2, kreg_ttlout1_pllout_freq_division_ctrl = REGADDOFF__TTLOUT1 + 3, kreg_ttlout1_pllout_freq_multiplication_ctrl = REGADDOFF__TTLOUT1 + 4, kreg_ttlout1_pllout_polarity_ctrl = REGADDOFF__TTLOUT1 + 5, kreg_ttlout1_pllout_trigger_edge_select = REGADDOFF__TTLOUT1 + 6, kreg_ttlout1_forward_mode_polarity_ctrl = REGADDOFF__TTLOUT1 + 7, kreg_ttlout1_placeholder0 = REGADDOFF__TTLOUT1 + 8, kreg_ttlout1_freq_detect_bias = REGADDOFF__TTLOUT1 + 9, kreg_ttlout1_sig_in_freq_detect = REGADDOFF__TTLOUT1 + 0xE, kreg_ttlout1_sig_out_freq_detect = REGADDOFF__TTLOUT1 + 0xF,
kreg_ttlout2_module = REGADDOFF__TTLOUT2 + 0, kreg_ttlout2_signal_process_mode = REGADDOFF__TTLOUT2 + 1, kreg_ttlout2_input_signal_select = REGADDOFF__TTLOUT2 + 2, kreg_ttlout2_pllout_freq_division_ctrl = REGADDOFF__TTLOUT2 + 3, kreg_ttlout2_pllout_freq_multiplication_ctrl = REGADDOFF__TTLOUT2 + 4, kreg_ttlout2_pllout_polarity_ctrl = REGADDOFF__TTLOUT2 + 5, kreg_ttlout2_pllout_trigger_edge_select = REGADDOFF__TTLOUT2 + 6, kreg_ttlout2_forward_mode_polarity_ctrl = REGADDOFF__TTLOUT2 + 7, kreg_ttlout2_placeholder0 = REGADDOFF__TTLOUT2 + 8, kreg_ttlout2_freq_detect_bias = REGADDOFF__TTLOUT2 + 9, kreg_ttlout2_sig_in_freq_detect = REGADDOFF__TTLOUT2 + 0xE, kreg_ttlout2_sig_out_freq_detect = REGADDOFF__TTLOUT2 + 0xF,
kreg_ttlout3_module = REGADDOFF__TTLOUT3 + 0, kreg_ttlout3_signal_process_mode = REGADDOFF__TTLOUT3 + 1, kreg_ttlout3_input_signal_select = REGADDOFF__TTLOUT3 + 2, kreg_ttlout3_pllout_freq_division_ctrl = REGADDOFF__TTLOUT3 + 3, kreg_ttlout3_pllout_freq_multiplication_ctrl = REGADDOFF__TTLOUT3 + 4, kreg_ttlout3_pllout_polarity_ctrl = REGADDOFF__TTLOUT3 + 5, kreg_ttlout3_pllout_trigger_edge_select = REGADDOFF__TTLOUT3 + 6, kreg_ttlout3_forward_mode_polarity_ctrl = REGADDOFF__TTLOUT3 + 7, kreg_ttlout3_placeholder0 = REGADDOFF__TTLOUT3 + 8, kreg_ttlout3_freq_detect_bias = REGADDOFF__TTLOUT3 + 9, kreg_ttlout3_sig_in_freq_detect = REGADDOFF__TTLOUT3 + 0xE, kreg_ttlout3_sig_out_freq_detect = REGADDOFF__TTLOUT3 + 0xF,
kreg_ttlout4_module = REGADDOFF__TTLOUT4 + 0, kreg_ttlout4_signal_process_mode = REGADDOFF__TTLOUT4 + 1, kreg_ttlout4_input_signal_select = REGADDOFF__TTLOUT4 + 2, kreg_ttlout4_pllout_freq_division_ctrl = REGADDOFF__TTLOUT4 + 3, kreg_ttlout4_pllout_freq_multiplication_ctrl = REGADDOFF__TTLOUT4 + 4, kreg_ttlout4_pllout_polarity_ctrl = REGADDOFF__TTLOUT4 + 5, kreg_ttlout4_pllout_trigger_edge_select = REGADDOFF__TTLOUT4 + 6, kreg_ttlout4_forward_mode_polarity_ctrl = REGADDOFF__TTLOUT4 + 7, kreg_ttlout4_placeholder0 = REGADDOFF__TTLOUT4 + 8, kreg_ttlout4_freq_detect_bias = REGADDOFF__TTLOUT4 + 9, kreg_ttlout4_sig_in_freq_detect = REGADDOFF__TTLOUT4 + 0xE, kreg_ttlout4_sig_out_freq_detect = REGADDOFF__TTLOUT4 + 0xF,
/*******************************************************************************
* TIMECODE����ģ�� * *******************************************************************************/
external_timecode_module = REGADDOFF__EXTERNAL_TIMECODE + 0, external_timecode_sig_selt = REGADDOFF__EXTERNAL_TIMECODE + 1, external_timecode_format = REGADDOFF__EXTERNAL_TIMECODE + 2, external_timecode_code0 = REGADDOFF__EXTERNAL_TIMECODE + 3, external_timecode_code1 = REGADDOFF__EXTERNAL_TIMECODE + 4,
/*******************************************************************************
* �ڲ�TIMECODEģ�� * *******************************************************************************/
internal_timecode_module = REGADDOFF__INTERNAL_TIMECODE + 0, internal_timecode_en = REGADDOFF__INTERNAL_TIMECODE + 1, internal_timecode_format = REGADDOFF__INTERNAL_TIMECODE + 2, internal_timecode_data0 = REGADDOFF__INTERNAL_TIMECODE + 3, internal_timecode_data1 = REGADDOFF__INTERNAL_TIMECODE + 4,
/*******************************************************************************
* SYS_TIMECODE * *******************************************************************************/
sys_timecode_module = REGADDOFF__SYS_TIMECODE, sys_timecode_select = REGADDOFF__SYS_TIMECODE + 1, sys_timecode_format = REGADDOFF__SYS_TIMECODE + 2, sys_timecode_data0 = REGADDOFF__SYS_TIMECODE + 3, sys_timecode_data1 = REGADDOFF__SYS_TIMECODE + 4,
/*******************************************************************************
* TIMECODE����ģ�� * *******************************************************************************/
timecode_output_module = REGADDOFF__TIMECODE_OUT + 0, timecode_output_timecode0 = REGADDOFF__TIMECODE_OUT + 1, timecode_output_timecode1 = REGADDOFF__TIMECODE_OUT + 2, timecode_output_timecode_format = REGADDOFF__TIMECODE_OUT + 3, timecode_output_bnc_outut_level_select = REGADDOFF__TIMECODE_OUT + 4, timecode_output_headphone_outut_level_select = REGADDOFF__TIMECODE_OUT + 5,
/*******************************************************************************
* �ⲿGENLOCK * *******************************************************************************/
external_genlock_module = REGADDOFF__EXTERNAL_GENLOCK + 0, external_genlock_freq_detect_bias = REGADDOFF__EXTERNAL_GENLOCK + 1, external_genlock_freq = REGADDOFF__EXTERNAL_GENLOCK + 2,
/*******************************************************************************
* �ڲ�GENLOCK * *******************************************************************************/ internal_genlock_module = REGADDOFF__INTERNAL_GENLOCK + 0, internal_genlock_ctrl_mode = REGADDOFF__INTERNAL_GENLOCK + 1, internal_genlock_en = REGADDOFF__INTERNAL_GENLOCK + 2, internal_genlock_format = REGADDOFF__INTERNAL_GENLOCK + 3, internal_genlock_freq = REGADDOFF__INTERNAL_GENLOCK + 4,
/*******************************************************************************
* SYSGENLOCK * *******************************************************************************/ sys_genlock_module = REGADDOFF__SYS_GENLOCK, sys_genlock_source = REGADDOFF__SYS_GENLOCK + 1, sys_genlock_freq_detect_bias = REGADDOFF__SYS_GENLOCK + 2, sys_genlock_freq = REGADDOFF__SYS_GENLOCK + 3,
/*******************************************************************************
* �ڲ�CLOCK * *******************************************************************************/
internal_clock_module = REGADDOFF__INTERNAL_CLOCK + 0, internal_clock_ctrl_mode = REGADDOFF__INTERNAL_CLOCK + 1, internal_clock_en = REGADDOFF__INTERNAL_CLOCK + 2, internal_clock_freq = REGADDOFF__INTERNAL_CLOCK + 3,
/*******************************************************************************
* SYSCLOCK * *******************************************************************************/ sys_clock_module = REGADDOFF__SYS_CLOCK, sys_clock_source = REGADDOFF__SYS_CLOCK + 1, sys_clock_freq_division_ctrl = REGADDOFF__SYS_CLOCK + 2, sys_clock_freq_multiplication_ctrl = REGADDOFF__SYS_CLOCK + 3, sys_clock_freq_detect_bias = REGADDOFF__SYS_CLOCK + 4, sys_clock_trigger_edge_select = REGADDOFF__SYS_CLOCK + 5, sys_clock_infreq_detect = REGADDOFF__SYS_CLOCK + 0xE, sys_clock_outfreq_detect = REGADDOFF__SYS_CLOCK + 0xF,
/*******************************************************************************
* record_sig_gen * *******************************************************************************/ record_sig_gen_module = REGADDOFF__RECORD_SIG_GENERATOR + 0, record_sig_gen_ctrl_control_mode = REGADDOFF__RECORD_SIG_GENERATOR + 1, record_sig_gen_timecode_start0 = REGADDOFF__RECORD_SIG_GENERATOR + 2, record_sig_gen_timecode_start1 = REGADDOFF__RECORD_SIG_GENERATOR + 3, record_sig_gen_timecode_stop0 = REGADDOFF__RECORD_SIG_GENERATOR + 4, record_sig_gen_timecode_stop1 = REGADDOFF__RECORD_SIG_GENERATOR + 5, record_sig_gen_timecode_control_flag = REGADDOFF__RECORD_SIG_GENERATOR + 6,
record_sig_gen_ttlin_trigger_sig_source = REGADDOFF__RECORD_SIG_GENERATOR + 7, record_sig_gen_ttlin_trigger_level = REGADDOFF__RECORD_SIG_GENERATOR + 8, record_sig_gen_exposure_time = REGADDOFF__RECORD_SIG_GENERATOR + 9, record_sig_gen_exposure_offset_time = REGADDOFF__RECORD_SIG_GENERATOR + 10, record_sig_gen_manual_ctrl = REGADDOFF__RECORD_SIG_GENERATOR + 11,
record_sig_gen_timecode_snapshot0 = REGADDOFF__RECORD_SIG_GENERATOR + 13, record_sig_gen_timecode_snapshot1 = REGADDOFF__RECORD_SIG_GENERATOR + 14, record_sig_gen_record_state = REGADDOFF__RECORD_SIG_GENERATOR + 15,
/*******************************************************************************
* camera_sync_module * *******************************************************************************/ camera_sync_module = REGADDOFF__CAMERA_SYNC_OUT + 0, camera_sync_pulse_mode_valid_len = REGADDOFF__CAMERA_SYNC_OUT + 1,
} RegAdd_t;
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