xsync_stm32/usrc/base_service/fpga_if.c

#include "fpga_if.h"

#include "xsync_regs.hpp"
/**
 * @brief fpga_if��ʼ��
 */
#define TAG "fpga_if"
static fpga_if_t  fpga_if;
xs_gpio_t         spi2_cs;
SemaphoreHandle_t m_spilock;

void fpga_if_init() {  //
                       // fpga_if.spi1 = &hspi1;
                       // fpga_if.spi2 = &hspi2;
  uint8_t rxbuf[1];
  m_spilock = xSemaphoreCreateRecursiveMutex();
  /**
   * @brief ����SPI��δ������һ֡����֮ǰ��ʱ�����ǵ͵�ƽ(������Ӧ��Ϊ��)������
   * �ٴ���һ֡���ݣ�ʹʱ���߱�Ϊ�ߵ�ƽ��
   */

  /**
   * @brief
   *
   * CPOL:1
   * CPHA:1
   * LSB-FIRST
   */
  fpga_if.spi2 = &hspi1;
  xs_gpio_init_as_output(&spi2_cs, PA4, kxs_gpio_pullup, false, true);
  HAL_SPI_Receive(fpga_if.spi2, rxbuf, 1, 1000);

  // fpga_if.spi2 = &hspi1;
  // HAL_SPI_Receive(fpga_if.spi2, rxbuf, 1, 1000);

  fpga_if.timecode_irq_pin                     = PD6;
  fpga_if.camera_sync_code_irq_pin             = PD4;
  fpga_if.xsync_workstate_start_sig_irq_io_pin = PD5;
  fpga_if.reset_pin                            = PD7;

#if 1
  xs_gpio_init_as_input(&fpga_if.camera_sync_code_irq_io, fpga_if.camera_sync_code_irq_pin, kxs_gpio_pulldown, kxs_gpio_rising_irq, false);
  xs_gpio_init_as_input(&fpga_if.timecode_irq_io, fpga_if.timecode_irq_pin, kxs_gpio_pulldown, kxs_gpio_rising_irq, false);
  xs_gpio_init_as_input(&fpga_if.xsync_workstate_start_sig_irq_io, fpga_if.xsync_workstate_start_sig_irq_io_pin, kxs_gpio_pulldown, kxs_gpio_rising_and_falling_irq, false);
  xs_gpio_init_as_output(&fpga_if.reset_pin_io, fpga_if.reset_pin, kxs_gpio_pullup, false, false);

  xs_gpio_write(&fpga_if.reset_pin_io, false);
  xs_delay_ms(10);
  xs_gpio_write(&fpga_if.reset_pin_io, true);
#endif

  while (true) {
    uint32_t rxdata = 0;
    /**
     * @brief 
     * 0x100�� FPGA�� TTLIN ģ���ĵ�ַ���õ�ַ����ֵ������ַ��һ������ֵ
     */
    fpga_if_spi_read_data_02(0x0100, &rxdata);
    if (rxdata == 0x0100) {
      break;
    }
    ZLOGI(TAG, "waiting for fpga init..... %x, %x", 0x0100, rxdata);
    osDelay(50);
  }
}
void fpga_if_get_timecode(uint32_t *timecode0, uint32_t *timecode1) {
  fpga_if_spi_read_data_02(sys_timecode_data0, timecode0);
  fpga_if_spi_read_data_02(sys_timecode_data1, timecode1);
  return;
}
void fpga_if_get_record_state(uint32_t *recordstate) {
  fpga_if_spi_read_data_02(record_sig_gen_record_state, recordstate);
  return;
}
/**
 * @brief SPI�Ĵ���дָ��
 *
 * @param add
 * @param txdata
 * @param rxdata
 */
static void _fpga_if_spi_write_data(SPI_HandleTypeDef *hspi, uint32_t add, uint32_t txdata, uint32_t *rxdata) {
  uint8_t txbuf[2 + 5] = {0};
  uint8_t rxbuf[2 + 5] = {0};
  txbuf[0]             = add & 0xFF;
  txbuf[1]             = (add >> 8) & 0xFF;
  txbuf[1] |= 0x80;  // write flag
  txbuf[2] = txdata & 0xFF;
  txbuf[3] = (txdata >> 8) & 0xFF;
  txbuf[4] = (txdata >> 16) & 0xFF;
  txbuf[5] = (txdata >> 24) & 0xFF;

  HAL_SPI_TransmitReceive_DMA(hspi, txbuf, rxbuf, 2 + 5);
  while (HAL_SPI_GetState(hspi) != HAL_SPI_STATE_READY) {
  }

  // HAL_SPI_Transmit(hspi, txbuf, 2 + 4, 1000);
  *rxdata = rxbuf[2] | (rxbuf[3] << 8) | (rxbuf[4] << 16) | (rxbuf[5] << 24);
}
/**
 * @brief SPI�Ĵ�����ָ��
 *
 * @param add
 * @param rxdata
 */
static void _fpga_if_spi_read_data(SPI_HandleTypeDef *hspi, uint32_t add, uint32_t *rxdata) {
  uint8_t txbuf[2 + 5] = {0};
  uint8_t rxbuf[2 + 5] = {0};

  txbuf[0] = add & 0xFF;
  txbuf[1] = (add >> 8) & 0xFF;
  txbuf[2] = 0;
  txbuf[3] = 0;
  txbuf[4] = 0;
  txbuf[5] = 0;
  HAL_SPI_TransmitReceive_DMA(hspi, txbuf, rxbuf, 2 + 5);
  while (HAL_SPI_GetState(hspi) != HAL_SPI_STATE_READY) {
  }
  *rxdata = rxbuf[2] | (rxbuf[3] << 8) | (rxbuf[4] << 16) | (rxbuf[5] << 24);
}

void fpga_if_spi_write_data_02(uint32_t add, uint32_t txdata, uint32_t *rxdata) {
  xSemaphoreTakeRecursive(m_spilock, portMAX_DELAY);
  xs_gpio_write(&spi2_cs, false);
  _fpga_if_spi_write_data(fpga_if.spi2, add, txdata, rxdata);
  xs_gpio_write(&spi2_cs, true);
  xs_delay_us(1);
  xs_gpio_write(&spi2_cs, false);
  _fpga_if_spi_read_data(fpga_if.spi2, add, rxdata);
  xs_gpio_write(&spi2_cs, true);
  xSemaphoreGiveRecursive(m_spilock);
}
void fpga_if_spi_read_data_02(uint32_t add, uint32_t *rxdata) {
  xSemaphoreTakeRecursive(m_spilock, portMAX_DELAY);
  xs_gpio_write(&spi2_cs, false);
  _fpga_if_spi_read_data(fpga_if.spi2, add, rxdata);
  xs_gpio_write(&spi2_cs, true);
  xSemaphoreGiveRecursive(m_spilock);
}

fpga_if_t *fpga_if_get_instance() { return &fpga_if; }