xsync_stm32/iflytop_xsync_protocol/iflytop_xsync_protocol.h

#pragma once
#include <stdint.h>

/**
 * @brief XSYNCЭ���˿�
 */
#define IFLYTOP_XSYNC_SERVICE_PORT 19901

#define IFLYTOP_XSYNC_TIMECODE_REPORT_FROM_PORT 19902
#define IFLYTOP_XSYNC_TIMECODE_REPORT_TO_PORT   19903

#define IFLYTOP_XSYNC_CAMERA_SYNC_PACKET_FROM_PORT 13013
#define IFLYTOP_XSYNC_CAMERA_SYNC_PACKET_TO_PORT   13014

/**
 * @brief
 *      Э��˵��
 *
 * kxsync_packet_type_reg_read:
 *  tx: regadd
 *  rx: ecode,regdata
 *
 * kxsync_packet_type_reg_write
 *  tx: regadd,regdata
 *  rx: ecode,regdata
 *
 * kxsync_packet_type_reg_read_regs
 *  tx: regstartadd,nreg
 *  rx: ecode,regdatas
 *
 */
typedef enum {
  kxsync_packet_type_none            = 0,
  kxsync_packet_type_reg_read        = 1,
  kxsync_packet_type_reg_write       = 2,
  kxsync_packet_type_reg_read_regs   = 3,
  kxsync_packet_type_timecode_report = 4,
} xsync_protocol_cmd_t;

typedef enum {
  kxsync_packet_type_cmd     = 0,
  kxsync_packet_type_receipt = 1,
  kxsync_packet_type_report  = 2,
} xsync_protocol_packet_type_t;

#pragma pack(1)

typedef struct {
  uint16_t type;
  uint16_t index;
  uint16_t cmd;
  uint16_t ndata;
  uint32_t data[];  // first is always checksum
} iflytop_xsync_packet_header_t;

typedef struct {
  uint32_t timecode0;
  uint32_t timecode1;
} iflytop_timecode_report_packet_t;

#define XYSNC_REG_DEVICE_INFO_START_ADD  0
#define XYSNC_REG_STM32_CONFIG_START_ADD 16
#define XYSNC_REG_FPGA_REG_START         32

typedef enum {
  /**
   * @brief
   *  REG 0(16)  �豸��Ϣ�����Ĵ���
   */
  kxsync_reg_software_version = 0,
  kxsync_reg_manufacturer0    = 1,
  kxsync_reg_manufacturer1    = 2,
  kxsync_reg_product_type_id  = 3,
  kxsync_reg_sn_id0           = 4,
  kxsync_reg_sn_id1           = 5,
  kxsync_reg_sn_id2           = 6,
  kxsync_reg_mac0             = 7,
  kxsync_reg_mac1             = 8,

  /**
   * @brief
   *  REG 16(32)  STM32���üĴ���0
   */
  kxsync_reg_stm32_obtaining_ip_mode        = XYSNC_REG_STM32_CONFIG_START_ADD + 0,
  kxsync_reg_stm32_ip                       = XYSNC_REG_STM32_CONFIG_START_ADD + 1,
  kxsync_reg_stm32_gw                       = XYSNC_REG_STM32_CONFIG_START_ADD + 2,
  kxsync_reg_stm32_netmask                  = XYSNC_REG_STM32_CONFIG_START_ADD + 3,
  kxsync_reg_stm32_camera_sync_signal_count = XYSNC_REG_STM32_CONFIG_START_ADD + 4,  // д������ֵ֮������
  kxsync_reg_stm32_config0                  = XYSNC_REG_STM32_CONFIG_START_ADD + 5,  // bit0: timecode report enable, bit1: camera sync report enable

  kxsync_reg_stm32_action0     = XYSNC_REG_STM32_CONFIG_START_ADD + 14,  // action reg
  kxsync_reg_stm32_action_val0 = XYSNC_REG_STM32_CONFIG_START_ADD + 15,  // action val reg

  /**
   * @brief
   *  REG 48(32)  FPGA���üĴ���0
   */
  kxsync_fpga_reg_test_reg0 = XYSNC_REG_FPGA_REG_START + 16 * 0 + 0,
  kxsync_fpga_reg_test_reg1 = XYSNC_REG_FPGA_REG_START + 16 * 0 + 1,
  kxsync_fpga_reg_test_reg2 = XYSNC_REG_FPGA_REG_START + 16 * 0 + 2,
  kxsync_fpga_reg_test_reg3 = XYSNC_REG_FPGA_REG_START + 16 * 0 + 3,
  kxsync_fpga_reg_test_reg4 = XYSNC_REG_FPGA_REG_START + 16 * 0 + 4,
  kxsync_fpga_reg_test_reg5 = XYSNC_REG_FPGA_REG_START + 16 * 0 + 5,
  kxsync_fpga_reg_test_reg6 = XYSNC_REG_FPGA_REG_START + 16 * 0 + 6,
  kxsync_fpga_reg_test_reg7 = XYSNC_REG_FPGA_REG_START + 16 * 0 + 7,
  kxsync_fpga_reg_test_reg8 = XYSNC_REG_FPGA_REG_START + 16 * 0 + 8,
  kxsync_fpga_reg_test_reg9 = XYSNC_REG_FPGA_REG_START + 16 * 0 + 9,
  kxsync_fpga_reg_test_rega = XYSNC_REG_FPGA_REG_START + 16 * 0 + 10,
  kxsync_fpga_reg_test_regb = XYSNC_REG_FPGA_REG_START + 16 * 0 + 11,
  kxsync_fpga_reg_test_regc = XYSNC_REG_FPGA_REG_START + 16 * 0 + 12,
  kxsync_fpga_reg_test_regd = XYSNC_REG_FPGA_REG_START + 16 * 0 + 13,
  kxsync_fpga_reg_test_rege = XYSNC_REG_FPGA_REG_START + 16 * 0 + 14,
  kxsync_fpga_reg_test_regf = XYSNC_REG_FPGA_REG_START + 16 * 0 + 15,

} xsync_reg_add_t;

#define KXSYNC_REG_STM32_CONFIG0_MASK_TIMECODE_REPORT_ENABLE    0x01
#define KXSYNC_REG_STM32_CONFIG0_MASK_CAMERA_SYNC_REPORT_ENABLE 0x02

typedef enum {
  xsync_stm32_action_none,               //
  xsync_stm32_action_generator_new_mac,  //
  xsync_stm32_action_factory_reset,      //
  xsync_stm32_action_reboot,             //
  xsync_stm32_action_storage_cfg,        //
} xsync_stm32_action_t;

typedef enum {
  kxsync_device_type_none         = 0,
  kxsync_device_type_xsync        = 1,
  kxsync_device_type_puck_station = 2,
  kxsync_device_type_encoder      = 3,
} xsync_device_type_t;

typedef enum { obtaining_ip_mode_type_static = 0, obtaining_ip_mode_type_dhcp = 1 } obtaining_ip_mode_t;
static inline const char* obtaining_ip_mode_to_string(obtaining_ip_mode_t mode) {
  switch (mode) {
    case obtaining_ip_mode_type_static:
      return "static";
    case obtaining_ip_mode_type_dhcp:
      return "dhcp";
    default:
      return "unknown";
  }
}
#pragma pack()