Browse Source

add timecode report logic

v5
zhaohe 2 years ago
parent
commit
baa2e4a553
  1. 3
      .vscode/settings.json
  2. 4
      Core/Src/spi.c
  3. 17
      README.md
  4. 2
      iflytop_xsync
  5. 36
      usrc/base_service/fpga_if.c
  6. 6
      usrc/base_service/task_level_config.h
  7. 2
      usrc/main.cpp
  8. 3
      usrc/service/network_service.c
  9. 9
      usrc/service/report_generator_service.c
  10. 8
      xsync_stm32.ioc

3
.vscode/settings.json

@ -96,7 +96,8 @@
"reg_manager.h": "c",
"fpga_if.h": "c",
"rng.h": "c",
"report_generator_service.h": "c"
"report_generator_service.h": "c",
"task_level_config.h": "c"
},
"files.autoGuessEncoding": false,
"files.encoding": "gbk"

4
Core/Src/spi.c

@ -49,7 +49,7 @@ void MX_SPI1_Init(void)
hspi1.Init.CLKPolarity = SPI_POLARITY_HIGH;
hspi1.Init.CLKPhase = SPI_PHASE_2EDGE;
hspi1.Init.NSS = SPI_NSS_HARD_OUTPUT;
hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_64;
hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_128;
hspi1.Init.FirstBit = SPI_FIRSTBIT_LSB;
hspi1.Init.TIMode = SPI_TIMODE_DISABLE;
hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
@ -81,7 +81,7 @@ void MX_SPI2_Init(void)
hspi2.Init.CLKPolarity = SPI_POLARITY_HIGH;
hspi2.Init.CLKPhase = SPI_PHASE_2EDGE;
hspi2.Init.NSS = SPI_NSS_SOFT;
hspi2.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_32;
hspi2.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_64;
hspi2.Init.FirstBit = SPI_FIRSTBIT_LSB;
hspi2.Init.TIMode = SPI_TIMODE_DISABLE;
hspi2.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;

17
README.md

@ -1,3 +1,20 @@
```
ref:https://iflytop1.feishu.cn/docx/FPqjdaTtkoBeU9x4qbjcD6vxnUc
```
```
FPGA
1. 将XyncInternal内部信号导出到ttl输出模块(包括内部timecode信号,外部timecode信号)OK
2. 完成XyncInternalPC端上位机相关配置 OK
2. 创建Timecode输出模块,监听Timecode输出信号到debug接口,完成timecodePC端上位机相关配置(输出同时输出到STM32)
影响网口输出
影响TIMECODE物理接口输出
3. 创建Genlock输出模块,完成Genlock输出模块PC端上位机相关配置(输出同时输出到STM32),计数清空信号
影响网口输出
影响GENLOCK物理接口输出
5. 实现Timecode输入解析。测试Timecode
```

2
iflytop_xsync

@ -1 +1 @@
Subproject commit 562d66799c183ce0ad6f9f242b700c13b6de1b5f
Subproject commit 6434f422ec46fc02968f71ad0dec47de6c8f1827

36
usrc/base_service/fpga_if.c

@ -4,14 +4,15 @@
* @brief fpga_if初始化
*/
#define TAG "fpga_if"
static fpga_if_t fpga_if;
xs_gpio_t spi2_cs;
static fpga_if_t fpga_if;
xs_gpio_t spi2_cs;
SemaphoreHandle_t m_spilock;
void fpga_if_init() { //
// fpga_if.spi1 = &hspi1;
// fpga_if.spi2 = &hspi2;
uint8_t rxbuf[1];
m_spilock = xSemaphoreCreateRecursiveMutex();
/**
* @brief SPI在未传输第一帧数据之前线()
* 使线
@ -24,16 +25,18 @@ void fpga_if_init() { //
// fpga_if.spi2 = &hspi1;
// HAL_SPI_Receive(fpga_if.spi2, rxbuf, 1, 1000);
#if 0
fpga_if.timecode_irq_pin = PD6;
fpga_if.camera_sync_code_irq_pin = PD4;
#if 1
xs_gpio_init_as_input(&fpga_if.camera_sync_code_irq_io, fpga_if.camera_sync_code_irq_pin, kxs_gpio_pulldown, kxs_gpio_rising_irq, false);
xs_gpio_init_as_input(&fpga_if.timecode_irq_io, fpga_if.timecode_irq_pin, kxs_gpio_pulldown, kxs_gpio_rising_irq, false);
for (size_t i = 0; i < 4; i++) {
xs_gpio_init_as_output(&fpga_if.timecode_add[i], fpga_if.timecode_add_pin[i], kxs_gpio_nopull, false, false);
}
for (size_t i = 0; i < 8; i++) {
xs_gpio_init_as_input(&fpga_if.timecode_data[i], fpga_if.timecode_data_pin[i], kxs_gpio_nopull, kxs_gpio_no_irq, false);
}
// for (size_t i = 0; i < 4; i++) {
// xs_gpio_init_as_output(&fpga_if.timecode_add[i], fpga_if.timecode_add_pin[i], kxs_gpio_nopull, false, false);
// }
// for (size_t i = 0; i < 8; i++) {
// xs_gpio_init_as_input(&fpga_if.timecode_data[i], fpga_if.timecode_data_pin[i], kxs_gpio_nopull, kxs_gpio_no_irq, false);
// }
#endif
}
/**
@ -57,8 +60,8 @@ static uint8_t _fpga_if_get_timecode_u8(uint8_t add) {
return data;
}
void fpga_if_get_timecode(uint32_t *timecode0, uint32_t *timecode1) {
*timecode0 = 1;
*timecode1 = 2;
// *timecode0 = 1;
// *timecode1 = 2;
#if 0
*timecode0 = 0;
*timecode1 = 0;
@ -71,6 +74,9 @@ void fpga_if_get_timecode(uint32_t *timecode0, uint32_t *timecode1) {
*timecode1 |= fpga_if_get_timecode_u8(4) << 0;
*timecode1 |= fpga_if_get_timecode_u8(5) << 8;
#endif
fpga_if_spi_read_data_02(577, timecode0);
fpga_if_spi_read_data_02(578, timecode1);
return;
}
@ -127,6 +133,7 @@ void fpga_if_spi_write_data_01(uint32_t add, uint32_t txdata, uint32_t *rxdata)
}
void fpga_if_spi_read_data_01(uint32_t add, uint32_t *rxdata) { _fpga_if_spi_read_data(fpga_if.spi1, add, rxdata); }
void fpga_if_spi_write_data_02(uint32_t add, uint32_t txdata, uint32_t *rxdata) {
xSemaphoreTakeRecursive(m_spilock, portMAX_DELAY);
xs_gpio_write(&spi2_cs, false);
_fpga_if_spi_write_data(fpga_if.spi2, add, txdata, rxdata);
xs_gpio_write(&spi2_cs, true);
@ -134,11 +141,14 @@ void fpga_if_spi_write_data_02(uint32_t add, uint32_t txdata, uint32_t *rxdata)
xs_gpio_write(&spi2_cs, false);
_fpga_if_spi_read_data(fpga_if.spi2, add, rxdata);
xs_gpio_write(&spi2_cs, true);
xSemaphoreGiveRecursive(m_spilock);
}
void fpga_if_spi_read_data_02(uint32_t add, uint32_t *rxdata) {
xSemaphoreTakeRecursive(m_spilock, portMAX_DELAY);
xs_gpio_write(&spi2_cs, false);
_fpga_if_spi_read_data(fpga_if.spi2, add, rxdata);
xs_gpio_write(&spi2_cs, true);
xSemaphoreGiveRecursive(m_spilock);
}
fpga_if_t *fpga_if_get_instance() { return &fpga_if; }

6
usrc/base_service/task_level_config.h

@ -0,0 +1,6 @@
#pragma once
#define TIMECODE_REPORT_TASK_LEVEL osPriorityNormal
#define UDP_RECEIVEER osPriorityNormal
#define CAMERA_SYNC_SIG_REPORT_TASK_LEVEL osPriorityAboveNormal
#define NETWORK_REPORT_TASK_LEVEL osPriorityHigh

2
usrc/main.cpp

@ -142,7 +142,7 @@ void umain() {
// HAL_SPI_Transmit(&hspi2, (uint8_t*)"hello", 5, 1000);
osDelay(10);
debug_light_ctrl();
// factory_reset_key_detect();
factory_reset_key_detect();
// ZLOGI(TAG,"factory_reset_key_state %d",xs_gpio_read(&m_factory_reset_key));
// osDelay(10);

3
usrc/service/network_service.c

@ -28,6 +28,7 @@
#include "ethernetif.h"
//
#include "base_service/base_service.h"
#include "base_service/task_level_config.h"
#define TAG "network"
@ -95,6 +96,6 @@ void network_service_init() {
/* Set the link callback function, this function is called on change of link status*/
netif_set_link_callback(&gnetif, ethernet_link_status_updated);
osThreadDef(EthLink, ethernet_link_thread, osPriorityBelowNormal, 0, 512);
osThreadDef(EthLink, ethernet_link_thread, NETWORK_REPORT_TASK_LEVEL, 0, 512);
osThreadCreate(osThread(EthLink), &gnetif);
}

9
usrc/service/report_generator_service.c

@ -5,6 +5,7 @@
#include "base_service/fpga_if.h"
#include "iflytop_xsync\xs_udp.h"
#include "reg_manager.h"
#include "base_service/task_level_config.h"
static udp_broadcast_handler_t m_udp_camera_sync_sender; //
static udp_broadcast_handler_t m_udp_camera_timecode_sender; //
@ -16,7 +17,7 @@ static uint32_t m_sync_count = 0;
static uint32_t m_timecode_trigger_input_off;
static uint32_t m_xync_trigger_input_off;
#define TAG "timecode"
/**
* @brief
*
@ -71,9 +72,11 @@ static void xync_signal_report_thread(void const *argument) {
void report_generator_service_irq_trigger(uint16_t gpiopin) {
if (gpiopin == m_timecode_trigger_input_off) {
// printf("1trigger\n");
osSignalSet(timecode_report_thread_id, 0x01);
}
if (gpiopin == m_xync_trigger_input_off) {
// printf("2trigger\n");
osSignalSet(xync_signal_report_thread_id, 0x01);
}
}
@ -82,10 +85,10 @@ void report_generator_service_init() {
ZASSERT(xs_udp_broadcast_init(&m_udp_camera_sync_sender, IFLYTOP_XSYNC_CAMERA_SYNC_PACKET_XSYNC_PORT));
ZASSERT(xs_udp_broadcast_init(&m_udp_camera_timecode_sender, IFLYTOP_XSYNC_TIMECODE_REPORT_XSYNC_PORT));
osThreadDef(timecode_report_thread, timecode_report_thread, osPriorityNormal, 0, 512);
osThreadDef(timecode_report_thread, timecode_report_thread, TIMECODE_REPORT_TASK_LEVEL, 0, 512);
timecode_report_thread_id = osThreadCreate(osThread(timecode_report_thread), NULL);
osThreadDef(xync_signal_report_thread, xync_signal_report_thread, osPriorityRealtime, 0, 512);
osThreadDef(xync_signal_report_thread, xync_signal_report_thread, CAMERA_SYNC_SIG_REPORT_TASK_LEVEL, 0, 512);
xync_signal_report_thread_id = osThreadCreate(osThread(xync_signal_report_thread), NULL);
ZASSERT(timecode_report_thread_id != NULL);

8
xsync_stm32.ioc

@ -306,20 +306,20 @@ RCC.VCOI2SOutputFreq_Value=128000000
RCC.VCOInputFreq_Value=2000000
RCC.VCOOutputFreq_Value=288000000
RCC.VcooutputI2S=64000000
SPI1.BaudRatePrescaler=SPI_BAUDRATEPRESCALER_64
SPI1.BaudRatePrescaler=SPI_BAUDRATEPRESCALER_128
SPI1.CLKPhase=SPI_PHASE_2EDGE
SPI1.CLKPolarity=SPI_POLARITY_HIGH
SPI1.CalculateBaudRate=1.125 MBits/s
SPI1.CalculateBaudRate=562.5 KBits/s
SPI1.Direction=SPI_DIRECTION_2LINES
SPI1.FirstBit=SPI_FIRSTBIT_LSB
SPI1.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate,VirtualNSS,BaudRatePrescaler,FirstBit,CLKPolarity,CLKPhase
SPI1.Mode=SPI_MODE_MASTER
SPI1.VirtualNSS=VM_NSSHARD
SPI1.VirtualType=VM_MASTER
SPI2.BaudRatePrescaler=SPI_BAUDRATEPRESCALER_32
SPI2.BaudRatePrescaler=SPI_BAUDRATEPRESCALER_64
SPI2.CLKPhase=SPI_PHASE_2EDGE
SPI2.CLKPolarity=SPI_POLARITY_HIGH
SPI2.CalculateBaudRate=1.125 MBits/s
SPI2.CalculateBaudRate=562.5 KBits/s
SPI2.Direction=SPI_DIRECTION_2LINES
SPI2.FirstBit=SPI_FIRSTBIT_LSB
SPI2.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate,CLKPolarity,CLKPhase,FirstBit,BaudRatePrescaler

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