10 changed files with 64 additions and 26 deletions
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3.vscode/settings.json
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4Core/Src/spi.c
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17README.md
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2iflytop_xsync
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36usrc/base_service/fpga_if.c
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6usrc/base_service/task_level_config.h
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2usrc/main.cpp
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3usrc/service/network_service.c
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9usrc/service/report_generator_service.c
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8xsync_stm32.ioc
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``` |
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ref:https://iflytop1.feishu.cn/docx/FPqjdaTtkoBeU9x4qbjcD6vxnUc |
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``` |
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``` |
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FPGA |
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1. 将XyncInternal内部信号导出到ttl输出模块(包括内部timecode信号,外部timecode信号)OK |
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2. 完成XyncInternalPC端上位机相关配置 OK |
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2. 创建Timecode输出模块,监听Timecode输出信号到debug接口,完成timecodePC端上位机相关配置(输出同时输出到STM32) |
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影响网口输出 |
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影响TIMECODE物理接口输出 |
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3. 创建Genlock输出模块,完成Genlock输出模块PC端上位机相关配置(输出同时输出到STM32),计数清空信号 |
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影响网口输出 |
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影响GENLOCK物理接口输出 |
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5. 实现Timecode输入解析。测试Timecode |
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``` |
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Subproject commit 562d66799c183ce0ad6f9f242b700c13b6de1b5f |
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Subproject commit 6434f422ec46fc02968f71ad0dec47de6c8f1827 |
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#pragma once |
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#define TIMECODE_REPORT_TASK_LEVEL osPriorityNormal |
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#define UDP_RECEIVEER osPriorityNormal |
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#define CAMERA_SYNC_SIG_REPORT_TASK_LEVEL osPriorityAboveNormal |
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#define NETWORK_REPORT_TASK_LEVEL osPriorityHigh |
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