diff --git a/Core/Inc/stm32f4xx_it.h b/Core/Inc/stm32f4xx_it.h
index 4e289e6..9730164 100644
--- a/Core/Inc/stm32f4xx_it.h
+++ b/Core/Inc/stm32f4xx_it.h
@@ -52,10 +52,16 @@ void MemManage_Handler(void);
 void BusFault_Handler(void);
 void UsageFault_Handler(void);
 void DebugMon_Handler(void);
+void DMA1_Stream3_IRQHandler(void);
+void DMA1_Stream4_IRQHandler(void);
 void TIM1_TRG_COM_TIM11_IRQHandler(void);
+void SPI1_IRQHandler(void);
+void SPI2_IRQHandler(void);
 void TIM6_DAC_IRQHandler(void);
 void TIM7_IRQHandler(void);
+void DMA2_Stream0_IRQHandler(void);
 void DMA2_Stream2_IRQHandler(void);
+void DMA2_Stream3_IRQHandler(void);
 void ETH_IRQHandler(void);
 /* USER CODE BEGIN EFP */
 
diff --git a/Core/Src/dma.c b/Core/Src/dma.c
index 3ed0a94..f66ceff 100644
--- a/Core/Src/dma.c
+++ b/Core/Src/dma.c
@@ -41,11 +41,24 @@ void MX_DMA_Init(void)
 
   /* DMA controller clock enable */
   __HAL_RCC_DMA2_CLK_ENABLE();
+  __HAL_RCC_DMA1_CLK_ENABLE();
 
   /* DMA interrupt init */
+  /* DMA1_Stream3_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(DMA1_Stream3_IRQn, 5, 0);
+  HAL_NVIC_EnableIRQ(DMA1_Stream3_IRQn);
+  /* DMA1_Stream4_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(DMA1_Stream4_IRQn, 5, 0);
+  HAL_NVIC_EnableIRQ(DMA1_Stream4_IRQn);
+  /* DMA2_Stream0_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(DMA2_Stream0_IRQn, 5, 0);
+  HAL_NVIC_EnableIRQ(DMA2_Stream0_IRQn);
   /* DMA2_Stream2_IRQn interrupt configuration */
   HAL_NVIC_SetPriority(DMA2_Stream2_IRQn, 5, 0);
   HAL_NVIC_EnableIRQ(DMA2_Stream2_IRQn);
+  /* DMA2_Stream3_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(DMA2_Stream3_IRQn, 5, 0);
+  HAL_NVIC_EnableIRQ(DMA2_Stream3_IRQn);
 
 }
 
diff --git a/Core/Src/spi.c b/Core/Src/spi.c
index 5295e89..0973641 100644
--- a/Core/Src/spi.c
+++ b/Core/Src/spi.c
@@ -26,6 +26,10 @@
 
 SPI_HandleTypeDef hspi1;
 SPI_HandleTypeDef hspi2;
+DMA_HandleTypeDef hdma_spi1_rx;
+DMA_HandleTypeDef hdma_spi1_tx;
+DMA_HandleTypeDef hdma_spi2_tx;
+DMA_HandleTypeDef hdma_spi2_rx;
 
 /* SPI1 init function */
 void MX_SPI1_Init(void)
@@ -45,7 +49,7 @@ void MX_SPI1_Init(void)
   hspi1.Init.CLKPolarity = SPI_POLARITY_HIGH;
   hspi1.Init.CLKPhase = SPI_PHASE_2EDGE;
   hspi1.Init.NSS = SPI_NSS_HARD_OUTPUT;
-  hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_4;
+  hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_16;
   hspi1.Init.FirstBit = SPI_FIRSTBIT_LSB;
   hspi1.Init.TIMode = SPI_TIMODE_DISABLE;
   hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
@@ -77,7 +81,7 @@ void MX_SPI2_Init(void)
   hspi2.Init.CLKPolarity = SPI_POLARITY_HIGH;
   hspi2.Init.CLKPhase = SPI_PHASE_2EDGE;
   hspi2.Init.NSS = SPI_NSS_HARD_OUTPUT;
-  hspi2.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
+  hspi2.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_8;
   hspi2.Init.FirstBit = SPI_FIRSTBIT_LSB;
   hspi2.Init.TIMode = SPI_TIMODE_DISABLE;
   hspi2.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
@@ -126,6 +130,46 @@ void HAL_SPI_MspInit(SPI_HandleTypeDef* spiHandle)
     GPIO_InitStruct.Alternate = GPIO_AF5_SPI1;
     HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
 
+    /* SPI1 DMA Init */
+    /* SPI1_RX Init */
+    hdma_spi1_rx.Instance = DMA2_Stream0;
+    hdma_spi1_rx.Init.Channel = DMA_CHANNEL_3;
+    hdma_spi1_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;
+    hdma_spi1_rx.Init.PeriphInc = DMA_PINC_DISABLE;
+    hdma_spi1_rx.Init.MemInc = DMA_MINC_ENABLE;
+    hdma_spi1_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
+    hdma_spi1_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
+    hdma_spi1_rx.Init.Mode = DMA_NORMAL;
+    hdma_spi1_rx.Init.Priority = DMA_PRIORITY_LOW;
+    hdma_spi1_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
+    if (HAL_DMA_Init(&hdma_spi1_rx) != HAL_OK)
+    {
+      Error_Handler();
+    }
+
+    __HAL_LINKDMA(spiHandle,hdmarx,hdma_spi1_rx);
+
+    /* SPI1_TX Init */
+    hdma_spi1_tx.Instance = DMA2_Stream3;
+    hdma_spi1_tx.Init.Channel = DMA_CHANNEL_3;
+    hdma_spi1_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
+    hdma_spi1_tx.Init.PeriphInc = DMA_PINC_DISABLE;
+    hdma_spi1_tx.Init.MemInc = DMA_MINC_ENABLE;
+    hdma_spi1_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
+    hdma_spi1_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
+    hdma_spi1_tx.Init.Mode = DMA_NORMAL;
+    hdma_spi1_tx.Init.Priority = DMA_PRIORITY_LOW;
+    hdma_spi1_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
+    if (HAL_DMA_Init(&hdma_spi1_tx) != HAL_OK)
+    {
+      Error_Handler();
+    }
+
+    __HAL_LINKDMA(spiHandle,hdmatx,hdma_spi1_tx);
+
+    /* SPI1 interrupt Init */
+    HAL_NVIC_SetPriority(SPI1_IRQn, 5, 0);
+    HAL_NVIC_EnableIRQ(SPI1_IRQn);
   /* USER CODE BEGIN SPI1_MspInit 1 */
 
   /* USER CODE END SPI1_MspInit 1 */
@@ -160,6 +204,46 @@ void HAL_SPI_MspInit(SPI_HandleTypeDef* spiHandle)
     GPIO_InitStruct.Alternate = GPIO_AF5_SPI2;
     HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
 
+    /* SPI2 DMA Init */
+    /* SPI2_TX Init */
+    hdma_spi2_tx.Instance = DMA1_Stream4;
+    hdma_spi2_tx.Init.Channel = DMA_CHANNEL_0;
+    hdma_spi2_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
+    hdma_spi2_tx.Init.PeriphInc = DMA_PINC_DISABLE;
+    hdma_spi2_tx.Init.MemInc = DMA_MINC_ENABLE;
+    hdma_spi2_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
+    hdma_spi2_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
+    hdma_spi2_tx.Init.Mode = DMA_NORMAL;
+    hdma_spi2_tx.Init.Priority = DMA_PRIORITY_LOW;
+    hdma_spi2_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
+    if (HAL_DMA_Init(&hdma_spi2_tx) != HAL_OK)
+    {
+      Error_Handler();
+    }
+
+    __HAL_LINKDMA(spiHandle,hdmatx,hdma_spi2_tx);
+
+    /* SPI2_RX Init */
+    hdma_spi2_rx.Instance = DMA1_Stream3;
+    hdma_spi2_rx.Init.Channel = DMA_CHANNEL_0;
+    hdma_spi2_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;
+    hdma_spi2_rx.Init.PeriphInc = DMA_PINC_DISABLE;
+    hdma_spi2_rx.Init.MemInc = DMA_MINC_ENABLE;
+    hdma_spi2_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
+    hdma_spi2_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
+    hdma_spi2_rx.Init.Mode = DMA_NORMAL;
+    hdma_spi2_rx.Init.Priority = DMA_PRIORITY_LOW;
+    hdma_spi2_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
+    if (HAL_DMA_Init(&hdma_spi2_rx) != HAL_OK)
+    {
+      Error_Handler();
+    }
+
+    __HAL_LINKDMA(spiHandle,hdmarx,hdma_spi2_rx);
+
+    /* SPI2 interrupt Init */
+    HAL_NVIC_SetPriority(SPI2_IRQn, 5, 0);
+    HAL_NVIC_EnableIRQ(SPI2_IRQn);
   /* USER CODE BEGIN SPI2_MspInit 1 */
 
   /* USER CODE END SPI2_MspInit 1 */
@@ -187,6 +271,12 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef* spiHandle)
 
     HAL_GPIO_DeInit(GPIOB, GPIO_PIN_5);
 
+    /* SPI1 DMA DeInit */
+    HAL_DMA_DeInit(spiHandle->hdmarx);
+    HAL_DMA_DeInit(spiHandle->hdmatx);
+
+    /* SPI1 interrupt Deinit */
+    HAL_NVIC_DisableIRQ(SPI1_IRQn);
   /* USER CODE BEGIN SPI1_MspDeInit 1 */
 
   /* USER CODE END SPI1_MspDeInit 1 */
@@ -209,6 +299,12 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef* spiHandle)
 
     HAL_GPIO_DeInit(GPIOB, GPIO_PIN_10|GPIO_PIN_9);
 
+    /* SPI2 DMA DeInit */
+    HAL_DMA_DeInit(spiHandle->hdmatx);
+    HAL_DMA_DeInit(spiHandle->hdmarx);
+
+    /* SPI2 interrupt Deinit */
+    HAL_NVIC_DisableIRQ(SPI2_IRQn);
   /* USER CODE BEGIN SPI2_MspDeInit 1 */
 
   /* USER CODE END SPI2_MspDeInit 1 */
diff --git a/Core/Src/stm32f4xx_it.c b/Core/Src/stm32f4xx_it.c
index 9815314..08022fc 100644
--- a/Core/Src/stm32f4xx_it.c
+++ b/Core/Src/stm32f4xx_it.c
@@ -56,6 +56,12 @@
 
 /* External variables --------------------------------------------------------*/
 extern ETH_HandleTypeDef heth;
+extern DMA_HandleTypeDef hdma_spi1_rx;
+extern DMA_HandleTypeDef hdma_spi1_tx;
+extern DMA_HandleTypeDef hdma_spi2_tx;
+extern DMA_HandleTypeDef hdma_spi2_rx;
+extern SPI_HandleTypeDef hspi1;
+extern SPI_HandleTypeDef hspi2;
 extern TIM_HandleTypeDef htim1;
 extern TIM_HandleTypeDef htim6;
 extern TIM_HandleTypeDef htim7;
@@ -165,6 +171,34 @@ void DebugMon_Handler(void)
 /******************************************************************************/
 
 /**
+  * @brief This function handles DMA1 stream3 global interrupt.
+  */
+void DMA1_Stream3_IRQHandler(void)
+{
+  /* USER CODE BEGIN DMA1_Stream3_IRQn 0 */
+
+  /* USER CODE END DMA1_Stream3_IRQn 0 */
+  HAL_DMA_IRQHandler(&hdma_spi2_rx);
+  /* USER CODE BEGIN DMA1_Stream3_IRQn 1 */
+
+  /* USER CODE END DMA1_Stream3_IRQn 1 */
+}
+
+/**
+  * @brief This function handles DMA1 stream4 global interrupt.
+  */
+void DMA1_Stream4_IRQHandler(void)
+{
+  /* USER CODE BEGIN DMA1_Stream4_IRQn 0 */
+
+  /* USER CODE END DMA1_Stream4_IRQn 0 */
+  HAL_DMA_IRQHandler(&hdma_spi2_tx);
+  /* USER CODE BEGIN DMA1_Stream4_IRQn 1 */
+
+  /* USER CODE END DMA1_Stream4_IRQn 1 */
+}
+
+/**
   * @brief This function handles TIM1 trigger and commutation interrupts and TIM11 global interrupt.
   */
 void TIM1_TRG_COM_TIM11_IRQHandler(void)
@@ -180,6 +214,34 @@ void TIM1_TRG_COM_TIM11_IRQHandler(void)
 }
 
 /**
+  * @brief This function handles SPI1 global interrupt.
+  */
+void SPI1_IRQHandler(void)
+{
+  /* USER CODE BEGIN SPI1_IRQn 0 */
+
+  /* USER CODE END SPI1_IRQn 0 */
+  HAL_SPI_IRQHandler(&hspi1);
+  /* USER CODE BEGIN SPI1_IRQn 1 */
+
+  /* USER CODE END SPI1_IRQn 1 */
+}
+
+/**
+  * @brief This function handles SPI2 global interrupt.
+  */
+void SPI2_IRQHandler(void)
+{
+  /* USER CODE BEGIN SPI2_IRQn 0 */
+
+  /* USER CODE END SPI2_IRQn 0 */
+  HAL_SPI_IRQHandler(&hspi2);
+  /* USER CODE BEGIN SPI2_IRQn 1 */
+
+  /* USER CODE END SPI2_IRQn 1 */
+}
+
+/**
   * @brief This function handles TIM6 global interrupt, DAC1 and DAC2 underrun error interrupts.
   */
 void TIM6_DAC_IRQHandler(void)
@@ -208,6 +270,20 @@ void TIM7_IRQHandler(void)
 }
 
 /**
+  * @brief This function handles DMA2 stream0 global interrupt.
+  */
+void DMA2_Stream0_IRQHandler(void)
+{
+  /* USER CODE BEGIN DMA2_Stream0_IRQn 0 */
+
+  /* USER CODE END DMA2_Stream0_IRQn 0 */
+  HAL_DMA_IRQHandler(&hdma_spi1_rx);
+  /* USER CODE BEGIN DMA2_Stream0_IRQn 1 */
+
+  /* USER CODE END DMA2_Stream0_IRQn 1 */
+}
+
+/**
   * @brief This function handles DMA2 stream2 global interrupt.
   */
 void DMA2_Stream2_IRQHandler(void)
@@ -222,6 +298,20 @@ void DMA2_Stream2_IRQHandler(void)
 }
 
 /**
+  * @brief This function handles DMA2 stream3 global interrupt.
+  */
+void DMA2_Stream3_IRQHandler(void)
+{
+  /* USER CODE BEGIN DMA2_Stream3_IRQn 0 */
+
+  /* USER CODE END DMA2_Stream3_IRQn 0 */
+  HAL_DMA_IRQHandler(&hdma_spi1_tx);
+  /* USER CODE BEGIN DMA2_Stream3_IRQn 1 */
+
+  /* USER CODE END DMA2_Stream3_IRQn 1 */
+}
+
+/**
   * @brief This function handles Ethernet global interrupt.
   */
 void ETH_IRQHandler(void)
diff --git a/usrc/base_service/config_service.c b/usrc/base_service/config_service.c
index 17da2ef..be57c24 100644
--- a/usrc/base_service/config_service.c
+++ b/usrc/base_service/config_service.c
@@ -60,12 +60,13 @@ void config_init(void) {
   dump_config(&_config);
 }
 config_t *config_get(void) { return &_config; }
-void      config_flush(void) {  xs_flash_flush(); }
+void      config_flush(void) { xs_flash_flush(); }
 void      config_factory_reset(void) { xs_flash_factory_reset(); }
 
 void config_generate_random_mac(void) {
   static mac_t mac;
   xs_id_generate_random_mac(&mac);
+  ZLOGI(TAG, "gen random mac is %02x:%02x:%02x:%02x:%02x:%02x", mac.mac[0], mac.mac[1], mac.mac[2], mac.mac[3], mac.mac[4], mac.mac[5]);
   memset(&_config.mac[0], 0, sizeof(_config.mac));
   memcpy(&_config.mac[0], mac.mac, 6);
 }
diff --git a/usrc/base_service/fpga_if.c b/usrc/base_service/fpga_if.c
index fa5a0ac..d2fb918 100644
--- a/usrc/base_service/fpga_if.c
+++ b/usrc/base_service/fpga_if.c
@@ -3,11 +3,26 @@
 /**
  * @brief fpga_if初始化
  */
-
+#define TAG "fpga_if"
 static fpga_if_t fpga_if;
-void             fpga_if_init() {  //
-  fpga_if.spi1 = &hspi1;
-  fpga_if.spi2 = &hspi2;
+xs_gpio_t        spi1_cs;
+
+void fpga_if_init() {  //
+                       // fpga_if.spi1 = &hspi1;
+                       // fpga_if.spi2 = &hspi2;
+  fpga_if.spi1 = &hspi2;
+  fpga_if.spi2 = &hspi1;
+
+  xs_gpio_init_as_output(&spi1_cs, PC6, kxs_gpio_nopull, false, true);
+
+  /**
+   * @brief 由于SPI在未传输第一帧数据之前，时钟线是低电平(理论上应该为高)，这里
+   * 假传输一帧数据，使时钟线变为高电平。
+   */
+  uint8_t rxbuf[1];
+  HAL_SPI_Receive(fpga_if.spi1, rxbuf, 1, 1000);
+  HAL_SPI_Receive(fpga_if.spi2, rxbuf, 1, 1000);
+
   // xs_gpio_init_as_output(PA)
 #if 0
   xs_gpio_init_as_input(&fpga_if.camera_sync_code_irq_io, fpga_if.camera_sync_code_irq_pin, kxs_gpio_pulldown, kxs_gpio_rising_irq, false);
@@ -68,6 +83,7 @@ void fpga_if_get_timecode(uint32_t *timecode0, uint32_t *timecode1) {
  */
 static void _fpga_if_spi_write_data(SPI_HandleTypeDef *hspi, uint32_t add, uint32_t txdata, uint32_t *rxdata) {
   uint8_t txbuf[2 + 4] = {0};
+  uint8_t rxbuf[2 + 4] = {0};
   txbuf[0]             = add & 0xFF;
   txbuf[1]             = (add >> 8) & 0xFF;
   txbuf[1] |= 0x80;  // write flag
@@ -76,8 +92,12 @@ static void _fpga_if_spi_write_data(SPI_HandleTypeDef *hspi, uint32_t add, uint3
   txbuf[4] = (txdata >> 16) & 0xFF;
   txbuf[5] = (txdata >> 24) & 0xFF;
 
-  HAL_SPI_TransmitReceive(hspi, txbuf, txbuf, 2 + 4, 1000);
-  *rxdata = txbuf[2] | (txbuf[3] << 8) | (txbuf[4] << 16) | (txbuf[5] << 24);
+  HAL_SPI_TransmitReceive_DMA(hspi, txbuf, rxbuf, 2 + 4);
+  while (HAL_SPI_GetState(hspi) != HAL_SPI_STATE_READY) {
+  }
+
+  // HAL_SPI_Transmit(hspi, txbuf, 2 + 4, 1000);
+  *rxdata = rxbuf[2] | (rxbuf[3] << 8) | (rxbuf[4] << 16) | (rxbuf[5] << 24);
 }
 /**
  * @brief SPI寄存器读指令
@@ -87,19 +107,31 @@ static void _fpga_if_spi_write_data(SPI_HandleTypeDef *hspi, uint32_t add, uint3
  */
 static void _fpga_if_spi_read_data(SPI_HandleTypeDef *hspi, uint32_t add, uint32_t *rxdata) {
   uint8_t txbuf[2 + 4] = {0};
-  txbuf[0]             = add & 0xFF;
-  txbuf[1]             = (add >> 8) & 0xFF;
-  txbuf[2]             = 0;
-  txbuf[3]             = 0;
-  txbuf[4]             = 0;
-  txbuf[5]             = 0;
-  HAL_SPI_TransmitReceive(hspi, txbuf, txbuf, 2 + 4, 1000);
-  *rxdata = txbuf[2] | (txbuf[3] << 8) | (txbuf[4] << 16) | (txbuf[5] << 24);
-}
+  uint8_t rxbuf[2 + 4] = {0};
 
-void fpga_if_spi_write_data_01(uint32_t add, uint32_t txdata, uint32_t *rxdata) { _fpga_if_spi_write_data(fpga_if.spi1, add, txdata, rxdata); }
-void fpga_if_spi_read_data_01(uint32_t add, uint32_t *rxdata) { _fpga_if_spi_read_data(fpga_if.spi1, add, rxdata); }
+  txbuf[0] = add & 0xFF;
+  txbuf[1] = (add >> 8) & 0xFF;
+  txbuf[2] = 0;
+  txbuf[3] = 0;
+  txbuf[4] = 0;
+  txbuf[5] = 0;
+  HAL_SPI_TransmitReceive_DMA(hspi, txbuf, rxbuf, 2 + 4);
+  while (HAL_SPI_GetState(hspi) != HAL_SPI_STATE_READY) {
+  }
+  *rxdata = rxbuf[2] | (rxbuf[3] << 8) | (rxbuf[4] << 16) | (rxbuf[5] << 24);
+}
 
+void fpga_if_spi_write_data_01(uint32_t add, uint32_t txdata, uint32_t *rxdata) {
+  // ZLOGI(TAG, "fpga_if_spi_write_data_01 add:%d txdata:%d", add, txdata);
+  xs_gpio_write(&spi1_cs, false);
+  _fpga_if_spi_write_data(fpga_if.spi1, add, txdata, rxdata);
+  xs_gpio_write(&spi1_cs, true);
+}
+void fpga_if_spi_read_data_01(uint32_t add, uint32_t *rxdata) {
+  xs_gpio_write(&spi1_cs, false);
+  _fpga_if_spi_read_data(fpga_if.spi1, add, rxdata);
+  xs_gpio_write(&spi1_cs, true);
+}
 void fpga_if_spi_write_data_02(uint32_t add, uint32_t txdata, uint32_t *rxdata) { _fpga_if_spi_write_data(fpga_if.spi2, add, txdata, rxdata); }
 void fpga_if_spi_read_data_02(uint32_t add, uint32_t *rxdata) { _fpga_if_spi_read_data(fpga_if.spi2, add, rxdata); }
 
diff --git a/usrc/base_service/fpga_if.h b/usrc/base_service/fpga_if.h
index b03149f..bae9763 100644
--- a/usrc/base_service/fpga_if.h
+++ b/usrc/base_service/fpga_if.h
@@ -6,7 +6,6 @@
 extern "C" {
 #endif
 
-
 typedef struct {
   /**
    * @brief 指令SPI 接口
diff --git a/usrc/main.cpp b/usrc/main.cpp
index 83b27fb..9817ba3 100644
--- a/usrc/main.cpp
+++ b/usrc/main.cpp
@@ -137,6 +137,8 @@ void umain() {
   ZLOGI(TAG, "system init done");
 
   while (true) {
+    // HAL_SPI_Transmit(&hspi1, (uint8_t*)"hello", 5, 1000);
+    // HAL_SPI_Transmit(&hspi2, (uint8_t*)"hello", 5, 1000);
     osDelay(10);
     debug_light_ctrl();
     // factory_reset_key_detect();
diff --git a/usrc/service/extern_if_service.c b/usrc/service/extern_if_service.c
index 765a795..f353253 100644
--- a/usrc/service/extern_if_service.c
+++ b/usrc/service/extern_if_service.c
@@ -95,7 +95,7 @@ static void udp_on_packet(udp_t *server, struct sockaddr_in *client, uint8_t *da
 
     receipt[0] = 0;                             // receipt
     receipt[1] = reg_manager_read_reg(regadd);  // regdata
-    ZLOGI(TAG, "regadd: %d, regdata: 0x%08x", regadd, receipt[1]);
+    // ZLOGI(TAG, "regadd: %d, regdata: 0x%08x", regadd, receipt[1]);
     create_and_send_receipt(&cx, receipt, 2);
   } else if (rxpacket->cmd == kxsync_packet_type_reg_write) {
     uint32_t regadd = rxpacket->data[0];
diff --git a/usrc/service/global_flag.c b/usrc/service/global_flag.c
new file mode 100644
index 0000000..e69de29
diff --git a/usrc/service/global_flag.h b/usrc/service/global_flag.h
new file mode 100644
index 0000000..e69de29
diff --git a/usrc/service/reg_manager.c b/usrc/service/reg_manager.c
index 51b9d12..1de8eef 100644
--- a/usrc/service/reg_manager.c
+++ b/usrc/service/reg_manager.c
@@ -17,6 +17,7 @@ void reg_manager_init() {}
 static uint32_t doaction(uint32_t action, uint32_t val) {
   if (action == xsync_stm32_action_generator_new_mac) {
     config_generate_random_mac();
+    config_flush();
     return 0;
   } else if (action == xsync_stm32_action_factory_reset) {
     config_factory_reset();
@@ -85,7 +86,7 @@ uint32_t reg_manager_read_reg(uint32_t addr) {
   /*******************************************************************************
    *                             FPGA芯片寄存器读写                              *
    *******************************************************************************/
-  else if (addr > XYSNC_REG_FPGA_REG_START) {
+  else if (addr >= XYSNC_REG_FPGA_REG_START) {
     fpga_if_spi_read_data_01(addr, &readbak);
   }
   return readbak;
@@ -121,8 +122,7 @@ uint32_t reg_manager_write_reg(uint32_t addr, uint32_t value) {
     config_get()->netmask = value;
     readbak               = config_get()->netmask;
   } else if (addr == kxsync_reg_stm32_camera_sync_signal_count) {
-    // 清零
-    report_generator_service_xsync_clear_count();
+    report_generator_service_xsync_set_count(value);
     readbak = report_generator_service_xsync_get_count();
   } else if (addr == kxsync_reg_stm32_config0) {
     readbak = config_get()->config0;
@@ -142,7 +142,7 @@ uint32_t reg_manager_write_reg(uint32_t addr, uint32_t value) {
   /*******************************************************************************
    *                             FPGA芯片寄存器读写                              *
    *******************************************************************************/
-  else if (addr > XYSNC_REG_FPGA_REG_START) {
+  else if (addr >= XYSNC_REG_FPGA_REG_START) {
     fpga_if_spi_write_data_01(addr, value, &readbak);
   }
 
diff --git a/usrc/service/report_generator_service.c b/usrc/service/report_generator_service.c
index 8f5d8fd..91ab361 100644
--- a/usrc/service/report_generator_service.c
+++ b/usrc/service/report_generator_service.c
@@ -95,5 +95,7 @@ void report_generator_service_init() {
   m_xync_trigger_input_off     = fpga_if_get_instance()->camera_sync_code_irq_io.pinoff;
 }
 
-void     report_generator_service_xsync_clear_count(void) { m_sync_count = 0; }
+void report_generator_service_xsync_set_count(uint32_t count){
+  m_sync_count = count;
+}
 uint32_t report_generator_service_xsync_get_count(void) { return m_sync_count; }
\ No newline at end of file
diff --git a/usrc/service/report_generator_service.h b/usrc/service/report_generator_service.h
index 0f62aa6..0a6090c 100644
--- a/usrc/service/report_generator_service.h
+++ b/usrc/service/report_generator_service.h
@@ -34,7 +34,7 @@ void report_generator_service_irq_trigger(uint16_t gpiopin);
 /**
  * @brief 清除xync计数
  */
-void report_generator_service_xsync_clear_count(void);
+void report_generator_service_xsync_set_count(uint32_t count);
 /**
  * @brief 获取xync计数
  *
diff --git a/xsync_stm32.ioc b/xsync_stm32.ioc
index 5c03d9e..cf8603e 100644
--- a/xsync_stm32.ioc
+++ b/xsync_stm32.ioc
@@ -3,7 +3,51 @@ CAD.formats=
 CAD.pinconfig=
 CAD.provider=
 Dma.Request0=USART1_RX
-Dma.RequestsNb=1
+Dma.Request1=SPI2_TX
+Dma.Request2=SPI2_RX
+Dma.Request3=SPI1_RX
+Dma.Request4=SPI1_TX
+Dma.RequestsNb=5
+Dma.SPI1_RX.3.Direction=DMA_PERIPH_TO_MEMORY
+Dma.SPI1_RX.3.FIFOMode=DMA_FIFOMODE_DISABLE
+Dma.SPI1_RX.3.Instance=DMA2_Stream0
+Dma.SPI1_RX.3.MemDataAlignment=DMA_MDATAALIGN_BYTE
+Dma.SPI1_RX.3.MemInc=DMA_MINC_ENABLE
+Dma.SPI1_RX.3.Mode=DMA_NORMAL
+Dma.SPI1_RX.3.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
+Dma.SPI1_RX.3.PeriphInc=DMA_PINC_DISABLE
+Dma.SPI1_RX.3.Priority=DMA_PRIORITY_LOW
+Dma.SPI1_RX.3.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode
+Dma.SPI1_TX.4.Direction=DMA_MEMORY_TO_PERIPH
+Dma.SPI1_TX.4.FIFOMode=DMA_FIFOMODE_DISABLE
+Dma.SPI1_TX.4.Instance=DMA2_Stream3
+Dma.SPI1_TX.4.MemDataAlignment=DMA_MDATAALIGN_BYTE
+Dma.SPI1_TX.4.MemInc=DMA_MINC_ENABLE
+Dma.SPI1_TX.4.Mode=DMA_NORMAL
+Dma.SPI1_TX.4.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
+Dma.SPI1_TX.4.PeriphInc=DMA_PINC_DISABLE
+Dma.SPI1_TX.4.Priority=DMA_PRIORITY_LOW
+Dma.SPI1_TX.4.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode
+Dma.SPI2_RX.2.Direction=DMA_PERIPH_TO_MEMORY
+Dma.SPI2_RX.2.FIFOMode=DMA_FIFOMODE_DISABLE
+Dma.SPI2_RX.2.Instance=DMA1_Stream3
+Dma.SPI2_RX.2.MemDataAlignment=DMA_MDATAALIGN_BYTE
+Dma.SPI2_RX.2.MemInc=DMA_MINC_ENABLE
+Dma.SPI2_RX.2.Mode=DMA_NORMAL
+Dma.SPI2_RX.2.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
+Dma.SPI2_RX.2.PeriphInc=DMA_PINC_DISABLE
+Dma.SPI2_RX.2.Priority=DMA_PRIORITY_LOW
+Dma.SPI2_RX.2.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode
+Dma.SPI2_TX.1.Direction=DMA_MEMORY_TO_PERIPH
+Dma.SPI2_TX.1.FIFOMode=DMA_FIFOMODE_DISABLE
+Dma.SPI2_TX.1.Instance=DMA1_Stream4
+Dma.SPI2_TX.1.MemDataAlignment=DMA_MDATAALIGN_BYTE
+Dma.SPI2_TX.1.MemInc=DMA_MINC_ENABLE
+Dma.SPI2_TX.1.Mode=DMA_NORMAL
+Dma.SPI2_TX.1.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
+Dma.SPI2_TX.1.PeriphInc=DMA_PINC_DISABLE
+Dma.SPI2_TX.1.Priority=DMA_PRIORITY_LOW
+Dma.SPI2_TX.1.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode
 Dma.USART1_RX.0.Direction=DMA_PERIPH_TO_MEMORY
 Dma.USART1_RX.0.FIFOMode=DMA_FIFOMODE_DISABLE
 Dma.USART1_RX.0.Instance=DMA2_Stream2
@@ -118,7 +162,11 @@ Mcu.UserName=STM32F407VETx
 MxCube.Version=6.7.0
 MxDb.Version=DB.6.0.70
 NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false
+NVIC.DMA1_Stream3_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true
+NVIC.DMA1_Stream4_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true
+NVIC.DMA2_Stream0_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true
 NVIC.DMA2_Stream2_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true
+NVIC.DMA2_Stream3_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true
 NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false
 NVIC.ETH_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true
 NVIC.ForceEnableDMAVector=true
@@ -127,6 +175,8 @@ NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:
 NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false
 NVIC.PendSV_IRQn=true\:15\:0\:false\:false\:false\:true\:false\:false\:false
 NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SPI1_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true\:true
+NVIC.SPI2_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true\:true
 NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:false\:false\:false\:false\:false
 NVIC.SavedPendsvIrqHandlerGenerated=true
 NVIC.SavedSvcallIrqHandlerGenerated=true
@@ -259,22 +309,23 @@ RCC.VCOI2SOutputFreq_Value=128000000
 RCC.VCOInputFreq_Value=2000000
 RCC.VCOOutputFreq_Value=288000000
 RCC.VcooutputI2S=64000000
-SPI1.BaudRatePrescaler=SPI_BAUDRATEPRESCALER_4
+SPI1.BaudRatePrescaler=SPI_BAUDRATEPRESCALER_16
 SPI1.CLKPhase=SPI_PHASE_2EDGE
 SPI1.CLKPolarity=SPI_POLARITY_HIGH
-SPI1.CalculateBaudRate=18.0 MBits/s
+SPI1.CalculateBaudRate=4.5 MBits/s
 SPI1.Direction=SPI_DIRECTION_2LINES
 SPI1.FirstBit=SPI_FIRSTBIT_LSB
 SPI1.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate,VirtualNSS,BaudRatePrescaler,FirstBit,CLKPolarity,CLKPhase
 SPI1.Mode=SPI_MODE_MASTER
 SPI1.VirtualNSS=VM_NSSHARD
 SPI1.VirtualType=VM_MASTER
+SPI2.BaudRatePrescaler=SPI_BAUDRATEPRESCALER_8
 SPI2.CLKPhase=SPI_PHASE_2EDGE
 SPI2.CLKPolarity=SPI_POLARITY_HIGH
-SPI2.CalculateBaudRate=18.0 MBits/s
+SPI2.CalculateBaudRate=4.5 MBits/s
 SPI2.Direction=SPI_DIRECTION_2LINES
 SPI2.FirstBit=SPI_FIRSTBIT_LSB
-SPI2.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate,VirtualNSS,CLKPolarity,CLKPhase,FirstBit
+SPI2.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate,VirtualNSS,CLKPolarity,CLKPhase,FirstBit,BaudRatePrescaler
 SPI2.Mode=SPI_MODE_MASTER
 SPI2.VirtualNSS=VM_NSSHARD
 SPI2.VirtualType=VM_MASTER