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dbdb_liquid_path_control_protocol_v1
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V2

master
zhaohe 1 year ago
parent
c6566e530e
commit
3745f1bb29
9 changed files with 324 additions and 74 deletions
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  1. 4
      .settings/language.settings.xml
  2. 2
      .vscode/c_cpp_properties.json
  3. 9
      .vscode/settings.json
  4. 2
      iflytop_xsync_protocol
  5. 44
      usrc/base_service/fpga_if.c
  6. 2
      usrc/base_service/fpga_if.h
  7. 260
      usrc/base_service/xsync_regs.hpp
  8. 7
      usrc/service/reg_manager.c
  9. 68
      usrc/service/report_generator_service.c

4
.settings/language.settings.xml
View File

@ -5,7 +5,7 @@
<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
<provider class="com.st.stm32cube.ide.mcu.toolchain.armnone.setup.CrossBuiltinSpecsDetector" console="false" env-hash="-561685569534312857" id="com.st.stm32cube.ide.mcu.toolchain.armnone.setup.CrossBuiltinSpecsDetector" keep-relative-paths="false" name="MCU ARM GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
<provider class="com.st.stm32cube.ide.mcu.toolchain.armnone.setup.CrossBuiltinSpecsDetector" console="false" env-hash="1904270345635912855" id="com.st.stm32cube.ide.mcu.toolchain.armnone.setup.CrossBuiltinSpecsDetector" keep-relative-paths="false" name="MCU ARM GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
<language-scope id="org.eclipse.cdt.core.gcc"/>
<language-scope id="org.eclipse.cdt.core.g++"/>
</provider>
@ -16,7 +16,7 @@
<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
<provider class="com.st.stm32cube.ide.mcu.toolchain.armnone.setup.CrossBuiltinSpecsDetector" console="false" env-hash="-676323101783886248" id="com.st.stm32cube.ide.mcu.toolchain.armnone.setup.CrossBuiltinSpecsDetector" keep-relative-paths="false" name="MCU ARM GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
<provider class="com.st.stm32cube.ide.mcu.toolchain.armnone.setup.CrossBuiltinSpecsDetector" console="false" env-hash="1789632813386339464" id="com.st.stm32cube.ide.mcu.toolchain.armnone.setup.CrossBuiltinSpecsDetector" keep-relative-paths="false" name="MCU ARM GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
<language-scope id="org.eclipse.cdt.core.gcc"/>
<language-scope id="org.eclipse.cdt.core.g++"/>
</provider>

2
.vscode/c_cpp_properties.json
View File

@ -13,7 +13,6 @@
"./Drivers/CMSIS/Include",
"C:/ST/STM32CubeIDE_1.13.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/arm-none-eabi/include",
"./usrc/",
"./sdk",
"Middlewares/Third_Party/LwIP/src/include/",
"LWIP/Target/",
"LWIP/App/",
@ -25,6 +24,7 @@
"USE_HAL_DRIVER",
"STM32F407xx"
],
"compilerPath": "C:/ST/STM32CubeIDE_1.13.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/arm-none-eabi-g++.exe",
"intelliSenseMode": "${default}"
}
],

9
.vscode/settings.json
View File

@ -97,7 +97,14 @@
"fpga_if.h": "c",
"rng.h": "c",
"report_generator_service.h": "c",
"task_level_config.h": "c"
"task_level_config.h": "c",
"charconv": "c",
"format": "c",
"ranges": "c",
"xutility": "c",
"cstring": "cpp",
"optional": "cpp",
"span": "cpp"
},
"files.autoGuessEncoding": false,
"files.encoding": "gbk"

2
iflytop_xsync_protocol

@ -1 +1 @@
Subproject commit 055f9672881d39e8fddcec7bc4e0a164245c797f
Subproject commit 6f8c0e94e9d830196ae42bfa6ea7dc447fe230ad

44
usrc/base_service/fpga_if.c
View File

@ -1,5 +1,6 @@
#include "fpga_if.h"
#include "xsync_regs.hpp"
/**
* @brief fpga_if³õʼ»¯
*/
@ -41,48 +42,13 @@ void fpga_if_init() { //
xs_gpio_write(&fpga_if.reset_pin_io, true);
#endif
}
/**
* @brief ÁÈ¡µ±Ç°timecode
*
* @param timecode0
* @param timecode1
*/
static uint8_t _fpga_if_get_timecode_u8(uint8_t add) {
xs_gpio_write(&fpga_if.timecode_add[0], add & 0x01);
xs_gpio_write(&fpga_if.timecode_add[1], add & 0x02);
xs_gpio_write(&fpga_if.timecode_add[2], add & 0x04);
xs_gpio_write(&fpga_if.timecode_add[3], add & 0x08);
xs_delay_us(2);
uint8_t data = 0;
for (size_t i = 0; i < 8; i++) {
data |= xs_gpio_read(&fpga_if.timecode_data[i]) << i;
}
return data;
}
void fpga_if_get_timecode(uint32_t *timecode0, uint32_t *timecode1) {
// *timecode0 = 1;
// *timecode1 = 2;
#if 0
*timecode0 = 0;
*timecode1 = 0;
*timecode0 |= fpga_if_get_timecode_u8(0) << 0;
*timecode0 |= fpga_if_get_timecode_u8(1) << 8;
*timecode0 |= fpga_if_get_timecode_u8(2) << 16;
*timecode0 |= fpga_if_get_timecode_u8(3) << 24;
*timecode1 |= fpga_if_get_timecode_u8(4) << 0;
*timecode1 |= fpga_if_get_timecode_u8(5) << 8;
#endif
fpga_if_spi_read_data_02(577, timecode0);
fpga_if_spi_read_data_02(578, timecode1);
fpga_if_spi_read_data_02(sys_timecode_data0, timecode0);
fpga_if_spi_read_data_02(sys_timecode_data1, timecode1);
return;
}
void fpga_if_get_workstate(uint32_t *workstate) {
fpga_if_spi_read_data_02(60, workstate);
void fpga_if_get_record_state(uint32_t *recordstate) {
fpga_if_spi_read_data_02(record_sig_gen_record_state, recordstate);
return;
}
/**

2
usrc/base_service/fpga_if.h
View File

@ -78,7 +78,7 @@ void fpga_if_spi_write_data_02(uint32_t add, uint32_t txdata, uint32_t *rxdata);
*/
void fpga_if_spi_read_data_02(uint32_t add, uint32_t *rxdata);
void fpga_if_get_workstate(uint32_t *workstate);
void fpga_if_get_record_state(uint32_t *workstate);
fpga_if_t *fpga_if_get_instance();

260
usrc/base_service/xsync_regs.hpp
View File

@ -0,0 +1,260 @@
#pragma once
#define REG_ADD_OFF_STM32 (0x0000)
#define REG_ADD_OFF_STM32_CONFIG_START_ADD (0x0010)
#define REGADDOFF__FPGA_INFO (0x0020)
#define REGADDOFF__TTLIN (0x0100)
#define REGADDOFF__EXTERNAL_TIMECODE (0x0120)
#define REGADDOFF__EXTERNAL_GENLOCK (0x0130)
#define REGADDOFF__INTERNAL_TIMECODE (0x0300)
#define REGADDOFF__INTERNAL_GENLOCK (0x0310)
#define REGADDOFF__INTERNAL_CLOCK (0x0320)
#define REGADDOFF__TTLOUT1 (0x0200)
#define REGADDOFF__TTLOUT2 (0x0210)
#define REGADDOFF__TTLOUT3 (0x0220)
#define REGADDOFF__TTLOUT4 (0x0230)
#define REGADDOFF__TIMECODE_OUT (0x0240)
#define REGADDOFF__GENLOCK_OUT (0x0250)
#define REGADDOFF__CAMERA_SYNC_OUT (0x0260)
#define REGADDOFF__SYS_TIMECODE (0x0400)
#define REGADDOFF__SYS_GENLOCK (0x0410)
#define REGADDOFF__SYS_CLOCK (0x0420)
#define REGADDOFF__RECORD_SIG_GENERATOR (0x0500)
typedef enum {
/**
* @brief
* REG 0(16) 设备信息基础寄存器
*/
ksoftware_version = 0,
kmanufacturer0 = 1,
kmanufacturer1 = 2,
kproduct_type_id = 3,
ksn_id0 = 4,
ksn_id1 = 5,
ksn_id2 = 6,
kmac0 = 7,
kmac1 = 8,
/**
* @brief
* REG 16(32) STM32配置寄存器0
*/
kstm32_obtaining_ip_mode = REG_ADD_OFF_STM32_CONFIG_START_ADD + 0,
kstm32_ip = REG_ADD_OFF_STM32_CONFIG_START_ADD + 1,
kstm32_gw = REG_ADD_OFF_STM32_CONFIG_START_ADD + 2,
kstm32_netmask = REG_ADD_OFF_STM32_CONFIG_START_ADD + 3,
kstm32_config0 = REG_ADD_OFF_STM32_CONFIG_START_ADD + 4, // bit0: timecode report enable, bit1: camera sync report enable
kstm32_camera_sync_signal_count = REG_ADD_OFF_STM32_CONFIG_START_ADD + 5, // 写任意数值之后清零
kstm32_camera_sync_signal_count_report_period = REG_ADD_OFF_STM32_CONFIG_START_ADD + 6, // 上报周期，单位为帧数
kstm32_action0 = REG_ADD_OFF_STM32_CONFIG_START_ADD + 14, // action reg
kstm32_action_val0 = REG_ADD_OFF_STM32_CONFIG_START_ADD + 15, // action val reg
/**
* @brief
* REG 48(32) FPGA配置寄存器0
*/
kfpga_info_reg0 = REGADDOFF__FPGA_INFO + 0,
kfpga_info_reg1 = REGADDOFF__FPGA_INFO + 1,
kfpga_info_reg2 = REGADDOFF__FPGA_INFO + 2,
kfpga_info_reg3 = REGADDOFF__FPGA_INFO + 3,
kfpga_info_reg4 = REGADDOFF__FPGA_INFO + 4,
kfpga_info_reg5 = REGADDOFF__FPGA_INFO + 5,
kfpga_info_reg6 = REGADDOFF__FPGA_INFO + 6,
kfpga_info_reg7 = REGADDOFF__FPGA_INFO + 7,
kfpga_info_reg8 = REGADDOFF__FPGA_INFO + 8,
kfpga_info_reg9 = REGADDOFF__FPGA_INFO + 9,
kfpga_info_rega = REGADDOFF__FPGA_INFO + 10,
kfpga_info_regb = REGADDOFF__FPGA_INFO + 11,
kfpga_info_regc = REGADDOFF__FPGA_INFO + 12,
kfpga_info_regd = REGADDOFF__FPGA_INFO + 13,
kfpga_info_rege = REGADDOFF__FPGA_INFO + 14,
kfpga_info_regf = REGADDOFF__FPGA_INFO + 15,
/*******************************************************************************
* TTL输入模块 *
*******************************************************************************/
k_ttlin_module = REGADDOFF__TTLIN + 0,
k_ttlin_en_reg = REGADDOFF__TTLIN + 1,
k_ttlin1_freq_detector_reg = REGADDOFF__TTLIN + 2,
k_ttlin2_freq_detector_reg = REGADDOFF__TTLIN + 3,
k_ttlin3_freq_detector_reg = REGADDOFF__TTLIN + 4,
k_ttlin4_freq_detector_reg = REGADDOFF__TTLIN + 5,
k_ttlin1_filter_factor_reg = REGADDOFF__TTLIN + 6,
k_ttlin2_filter_factor_reg = REGADDOFF__TTLIN + 7,
k_ttlin3_filter_factor_reg = REGADDOFF__TTLIN + 8,
k_ttlin4_filter_factor_reg = REGADDOFF__TTLIN + 9,
/*******************************************************************************
* TTL输出模块 *
*******************************************************************************/
kreg_ttlout1_module = REGADDOFF__TTLOUT1 + 0,
kreg_ttlout1_signal_process_mode = REGADDOFF__TTLOUT1 + 1,
kreg_ttlout1_input_signal_select = REGADDOFF__TTLOUT1 + 2,
kreg_ttlout1_pllout_freq_division_ctrl = REGADDOFF__TTLOUT1 + 3,
kreg_ttlout1_pllout_freq_multiplication_ctrl = REGADDOFF__TTLOUT1 + 4,
kreg_ttlout1_pllout_polarity_ctrl = REGADDOFF__TTLOUT1 + 5,
kreg_ttlout1_pllout_trigger_edge_select = REGADDOFF__TTLOUT1 + 6,
kreg_ttlout1_forward_mode_polarity_ctrl = REGADDOFF__TTLOUT1 + 7,
kreg_ttlout1_placeholder0 = REGADDOFF__TTLOUT1 + 8,
kreg_ttlout1_freq_detect_bias = REGADDOFF__TTLOUT1 + 9,
kreg_ttlout1_sig_in_freq_detect = REGADDOFF__TTLOUT1 + 0xE,
kreg_ttlout1_sig_out_freq_detect = REGADDOFF__TTLOUT1 + 0xF,
kreg_ttlout2_module = REGADDOFF__TTLOUT2 + 0,
kreg_ttlout2_signal_process_mode = REGADDOFF__TTLOUT2 + 1,
kreg_ttlout2_input_signal_select = REGADDOFF__TTLOUT2 + 2,
kreg_ttlout2_pllout_freq_division_ctrl = REGADDOFF__TTLOUT2 + 3,
kreg_ttlout2_pllout_freq_multiplication_ctrl = REGADDOFF__TTLOUT2 + 4,
kreg_ttlout2_pllout_polarity_ctrl = REGADDOFF__TTLOUT2 + 5,
kreg_ttlout2_pllout_trigger_edge_select = REGADDOFF__TTLOUT2 + 6,
kreg_ttlout2_forward_mode_polarity_ctrl = REGADDOFF__TTLOUT2 + 7,
kreg_ttlout2_placeholder0 = REGADDOFF__TTLOUT2 + 8,
kreg_ttlout2_freq_detect_bias = REGADDOFF__TTLOUT2 + 9,
kreg_ttlout2_sig_in_freq_detect = REGADDOFF__TTLOUT2 + 0xE,
kreg_ttlout2_sig_out_freq_detect = REGADDOFF__TTLOUT2 + 0xF,
kreg_ttlout3_module = REGADDOFF__TTLOUT3 + 0,
kreg_ttlout3_signal_process_mode = REGADDOFF__TTLOUT3 + 1,
kreg_ttlout3_input_signal_select = REGADDOFF__TTLOUT3 + 2,
kreg_ttlout3_pllout_freq_division_ctrl = REGADDOFF__TTLOUT3 + 3,
kreg_ttlout3_pllout_freq_multiplication_ctrl = REGADDOFF__TTLOUT3 + 4,
kreg_ttlout3_pllout_polarity_ctrl = REGADDOFF__TTLOUT3 + 5,
kreg_ttlout3_pllout_trigger_edge_select = REGADDOFF__TTLOUT3 + 6,
kreg_ttlout3_forward_mode_polarity_ctrl = REGADDOFF__TTLOUT3 + 7,
kreg_ttlout3_placeholder0 = REGADDOFF__TTLOUT3 + 8,
kreg_ttlout3_freq_detect_bias = REGADDOFF__TTLOUT3 + 9,
kreg_ttlout3_sig_in_freq_detect = REGADDOFF__TTLOUT3 + 0xE,
kreg_ttlout3_sig_out_freq_detect = REGADDOFF__TTLOUT3 + 0xF,
kreg_ttlout4_module = REGADDOFF__TTLOUT4 + 0,
kreg_ttlout4_signal_process_mode = REGADDOFF__TTLOUT4 + 1,
kreg_ttlout4_input_signal_select = REGADDOFF__TTLOUT4 + 2,
kreg_ttlout4_pllout_freq_division_ctrl = REGADDOFF__TTLOUT4 + 3,
kreg_ttlout4_pllout_freq_multiplication_ctrl = REGADDOFF__TTLOUT4 + 4,
kreg_ttlout4_pllout_polarity_ctrl = REGADDOFF__TTLOUT4 + 5,
kreg_ttlout4_pllout_trigger_edge_select = REGADDOFF__TTLOUT4 + 6,
kreg_ttlout4_forward_mode_polarity_ctrl = REGADDOFF__TTLOUT4 + 7,
kreg_ttlout4_placeholder0 = REGADDOFF__TTLOUT4 + 8,
kreg_ttlout4_freq_detect_bias = REGADDOFF__TTLOUT4 + 9,
kreg_ttlout4_sig_in_freq_detect = REGADDOFF__TTLOUT4 + 0xE,
kreg_ttlout4_sig_out_freq_detect = REGADDOFF__TTLOUT4 + 0xF,
/*******************************************************************************
* TIMECODE输入模块 *
*******************************************************************************/
external_timecode_module = REGADDOFF__EXTERNAL_TIMECODE + 0,
external_timecode_sig_selt = REGADDOFF__EXTERNAL_TIMECODE + 1,
external_timecode_format = REGADDOFF__EXTERNAL_TIMECODE + 2,
external_timecode_code0 = REGADDOFF__EXTERNAL_TIMECODE + 3,
external_timecode_code1 = REGADDOFF__EXTERNAL_TIMECODE + 4,
/*******************************************************************************
* 内部TIMECODE模块 *
*******************************************************************************/
internal_timecode_module = REGADDOFF__INTERNAL_TIMECODE + 0,
internal_timecode_en = REGADDOFF__INTERNAL_TIMECODE + 1,
internal_timecode_format = REGADDOFF__INTERNAL_TIMECODE + 2,
internal_timecode_data0 = REGADDOFF__INTERNAL_TIMECODE + 3,
internal_timecode_data1 = REGADDOFF__INTERNAL_TIMECODE + 4,
/*******************************************************************************
* SYS_TIMECODE *
*******************************************************************************/
sys_timecode_module = REGADDOFF__SYS_TIMECODE,
sys_timecode_select = REGADDOFF__SYS_TIMECODE + 1,
sys_timecode_format = REGADDOFF__SYS_TIMECODE + 2,
sys_timecode_data0 = REGADDOFF__SYS_TIMECODE + 3,
sys_timecode_data1 = REGADDOFF__SYS_TIMECODE + 4,
/*******************************************************************************
* TIMECODE输出模块 *
*******************************************************************************/
timecode_output_module = REGADDOFF__TIMECODE_OUT + 0,
timecode_output_timecode0 = REGADDOFF__TIMECODE_OUT + 1,
timecode_output_timecode1 = REGADDOFF__TIMECODE_OUT + 2,
timecode_output_timecode_format = REGADDOFF__TIMECODE_OUT + 3,
timecode_output_bnc_outut_level_select = REGADDOFF__TIMECODE_OUT + 4,
timecode_output_headphone_outut_level_select = REGADDOFF__TIMECODE_OUT + 5,
/*******************************************************************************
* 外部GENLOCK *
*******************************************************************************/
external_genlock_module = REGADDOFF__EXTERNAL_GENLOCK + 0,
external_genlock_freq_detect_bias = REGADDOFF__EXTERNAL_GENLOCK + 1,
external_genlock_freq = REGADDOFF__EXTERNAL_GENLOCK + 2,
/*******************************************************************************
* 内部GENLOCK *
*******************************************************************************/
internal_genlock_module = REGADDOFF__INTERNAL_GENLOCK + 0,
internal_genlock_ctrl_mode = REGADDOFF__INTERNAL_GENLOCK + 1,
internal_genlock_en = REGADDOFF__INTERNAL_GENLOCK + 2,
internal_genlock_format = REGADDOFF__INTERNAL_GENLOCK + 3,
internal_genlock_freq = REGADDOFF__INTERNAL_GENLOCK + 4,
/*******************************************************************************
* SYSGENLOCK *
*******************************************************************************/
sys_genlock_module = REGADDOFF__SYS_GENLOCK,
sys_genlock_source = REGADDOFF__SYS_GENLOCK + 1,
sys_genlock_freq_detect_bias = REGADDOFF__SYS_GENLOCK + 2,
sys_genlock_freq = REGADDOFF__SYS_GENLOCK + 3,
/*******************************************************************************
* 内部CLOCK *
*******************************************************************************/
internal_clock_module = REGADDOFF__INTERNAL_CLOCK + 0,
internal_clock_ctrl_mode = REGADDOFF__INTERNAL_CLOCK + 1,
internal_clock_en = REGADDOFF__INTERNAL_CLOCK + 2,
internal_clock_freq = REGADDOFF__INTERNAL_CLOCK + 3,
/*******************************************************************************
* SYSCLOCK *
*******************************************************************************/
sys_clock_module = REGADDOFF__SYS_CLOCK,
sys_clock_source = REGADDOFF__SYS_CLOCK + 1,
sys_clock_freq_division_ctrl = REGADDOFF__SYS_CLOCK + 2,
sys_clock_freq_multiplication_ctrl = REGADDOFF__SYS_CLOCK + 3,
sys_clock_freq_detect_bias = REGADDOFF__SYS_CLOCK + 4,
sys_clock_trigger_edge_select = REGADDOFF__SYS_CLOCK + 5,
sys_clock_infreq_detect = REGADDOFF__SYS_CLOCK + 0xE,
sys_clock_outfreq_detect = REGADDOFF__SYS_CLOCK + 0xF,
/*******************************************************************************
* record_sig_gen *
*******************************************************************************/
record_sig_gen_module = REGADDOFF__RECORD_SIG_GENERATOR + 0,
record_sig_gen_ctrl_control_mode = REGADDOFF__RECORD_SIG_GENERATOR + 1,
record_sig_gen_timecode_start0 = REGADDOFF__RECORD_SIG_GENERATOR + 2,
record_sig_gen_timecode_start1 = REGADDOFF__RECORD_SIG_GENERATOR + 3,
record_sig_gen_timecode_stop0 = REGADDOFF__RECORD_SIG_GENERATOR + 4,
record_sig_gen_timecode_stop1 = REGADDOFF__RECORD_SIG_GENERATOR + 5,
record_sig_gen_timecode_control_flag = REGADDOFF__RECORD_SIG_GENERATOR + 6,
record_sig_gen_ttlin_trigger_sig_source = REGADDOFF__RECORD_SIG_GENERATOR + 7,
record_sig_gen_ttlin_trigger_level = REGADDOFF__RECORD_SIG_GENERATOR + 8,
record_sig_gen_exposure_time = REGADDOFF__RECORD_SIG_GENERATOR + 9,
record_sig_gen_exposure_offset_time = REGADDOFF__RECORD_SIG_GENERATOR + 10,
record_sig_gen_manual_ctrl = REGADDOFF__RECORD_SIG_GENERATOR + 11,
record_sig_gen_timecode_snapshot0 = REGADDOFF__RECORD_SIG_GENERATOR + 13,
record_sig_gen_timecode_snapshot1 = REGADDOFF__RECORD_SIG_GENERATOR + 14,
record_sig_gen_record_state = REGADDOFF__RECORD_SIG_GENERATOR + 15,
/*******************************************************************************
* camera_sync_module *
*******************************************************************************/
camera_sync_module = REGADDOFF__CAMERA_SYNC_OUT + 0,
camera_sync_pulse_mode_valid_len = REGADDOFF__CAMERA_SYNC_OUT + 1,
} RegAdd_t;

7
usrc/service/reg_manager.c
View File

@ -73,9 +73,7 @@ uint32_t reg_manager_read_reg(uint32_t addr) {
readbak = config_get()->config0;
} else if (addr == kxsync_reg_stm32_camera_sync_signal_count) {
readbak = ReportGeneratorService_xsync_get_count();
} else if (addr == kxsync_reg_stm32_camera_sync_signal_report_period) {
readbak = ReportGeneratorService_get_camera_sync_code_report_period();
}
}
/*******************************************************************************
* ACTION *
@ -129,10 +127,7 @@ uint32_t reg_manager_write_reg(uint32_t addr, uint32_t value) {
} else if (addr == kxsync_reg_stm32_camera_sync_signal_count) {
ReportGeneratorService_xsync_set_count(value);
readbak = ReportGeneratorService_xsync_get_count();
} else if (addr == kxsync_reg_stm32_camera_sync_signal_report_period) {
readbak = ReportGeneratorService_set_camera_sync_code_report_period(value);
}
/*******************************************************************************
* ACTION *
*******************************************************************************/

68
usrc/service/report_generator_service.c
View File

@ -4,6 +4,7 @@
//
#include "base_service/fpga_if.h"
#include "base_service/task_level_config.h"
#include "base_service/xsync_regs.hpp"
#include "iflytop_xsync\xs_udp.h"
#include "reg_manager.h"
@ -13,13 +14,13 @@ static udp_broadcast_handler_t m_udp_camera_timecode_sender; //
osThreadId timecode_report_thread_id;
osThreadId xync_signal_report_thread_id;
static uint32_t m_sync_count = 0;
static uint32_t m_camera_sync_packet_report_period = 1;
static uint32_t m_sync_count = 0;
// static uint32_t m_camera_sync_packet_report_period = 1;
static uint32_t m_xsync_workstate_start_sig_irq_pin_off;
static uint32_t m_timecode_trigger_input_off;
static uint32_t m_xync_trigger_input_off;
static uint32_t m_xync_trigger_input_off;
static uint32_t m_xyns_camera_sync_packet_last_report_tp;
#define TAG "timecode"
/**
* @brief 构建并发送时间码数据包
@ -37,12 +38,16 @@ static void create_and_send_timecode(uint32_t timecode0, uint32_t timecode1) {
txpacket->data[1] = timecode1;
xs_udp_broadcast(&m_udp_camera_timecode_sender, IFLYTOP_XSYNC_EVENT_REPORT_PC_PORT, txbuf, sizeof(iflytop_xsync_event_report_packet_t) + 8);
}
static void create_and_send_sync_workstate_packet(uint32_t workstate) {
static void create_and_send_sync_record_state_packet(uint32_t workstate, uint32_t timecode0, uint32_t timecode1) {
static uint8_t txbuf[256];
iflytop_xsync_event_report_packet_t *txpacket = (iflytop_xsync_event_report_packet_t *)txbuf;
txpacket->eventid = kxsync_work_state_report_event;
txpacket->data[0] = workstate;
xs_udp_broadcast(&m_udp_camera_timecode_sender, IFLYTOP_XSYNC_EVENT_REPORT_PC_PORT, txbuf, sizeof(iflytop_xsync_event_report_packet_t) + 4);
uint32_t packetdatalen = 3;
iflytop_xsync_event_report_packet_t *txpacket = (iflytop_xsync_event_report_packet_t *)txbuf;
txpacket->eventid = kxsync_work_state_report_event;
txpacket->data[0] = workstate;
txpacket->data[1] = timecode0;
txpacket->data[2] = timecode1;
xs_udp_broadcast(&m_udp_camera_timecode_sender, IFLYTOP_XSYNC_EVENT_REPORT_PC_PORT, txbuf, sizeof(iflytop_xsync_event_report_packet_t) + 4 * packetdatalen);
}
/**
* @brief 构建并发送相机同步数据包
@ -65,15 +70,26 @@ static void create_and_send_camera_sync_msg(uint32_t count) {
static void timecode_report_thread(void const *argument) {
while (true) {
osEvent signal = osSignalWait(0x03, osWaitForever);
osEvent signal = osSignalWait(0x07, osWaitForever);
if (signal.value.signals & 0x01) {
uint32_t timecode0, timecode1;
fpga_if_get_timecode(&timecode0, &timecode1);
create_and_send_timecode(timecode0, timecode1);
} else if (signal.value.signals & 0x02) {
uint32_t workstate;
fpga_if_get_workstate(&workstate);
create_and_send_sync_workstate_packet(workstate);
// 开始录制
uint32_t timecode0 = 0;
uint32_t timecode1 = 0;
fpga_if_spi_read_data_02(record_sig_gen_timecode_snapshot0, &timecode0);
fpga_if_spi_read_data_02(record_sig_gen_timecode_snapshot1, &timecode1);
create_and_send_sync_record_state_packet(1, timecode0, timecode1);
} else if (signal.value.signals & 0x04) {
// 结束录制
uint32_t timecode0 = 0;
uint32_t timecode1 = 0;
fpga_if_spi_read_data_02(record_sig_gen_timecode_snapshot0, &timecode0);
fpga_if_spi_read_data_02(record_sig_gen_timecode_snapshot1, &timecode1);
create_and_send_sync_record_state_packet(0, timecode0, timecode1);
m_sync_count = 0;
}
}
}
@ -81,10 +97,18 @@ static void xync_signal_report_thread(void const *argument) {
while (true) {
osEvent signal = osSignalWait(0x01, osWaitForever);
if (signal.value.signals == 0x01) {
if (m_sync_count % m_camera_sync_packet_report_period == 0) {
if (m_sync_count == 0) {
m_xyns_camera_sync_packet_last_report_tp = HAL_GetTick();
create_and_send_camera_sync_msg(m_sync_count);
m_sync_count++;
} else if (xs_has_passedms(m_xyns_camera_sync_packet_last_report_tp) >= 998) {
// TODO:此处这么写，当拍摄频率大于500HZ的时候，就不能完全满足刚好卡在1s上报一次消息
m_xyns_camera_sync_packet_last_report_tp = HAL_GetTick();
create_and_send_camera_sync_msg(m_sync_count);
m_sync_count++;
} else {
m_sync_count++;
}
m_sync_count++;
}
// osSignalClear(xync_signal_report_thread_id, 0x01);
}
@ -92,13 +116,18 @@ static void xync_signal_report_thread(void const *argument) {
void ReportGeneratorService_irq_trigger(uint16_t gpiopin) {
if (gpiopin == m_timecode_trigger_input_off) {
// timecode trigger sig
osSignalSet(timecode_report_thread_id, 0x01);
}
if (m_xsync_workstate_start_sig_irq_pin_off == gpiopin) {
osSignalSet(timecode_report_thread_id, 0x02);
if (xs_gpio_read(&fpga_if_get_instance()->xsync_workstate_start_sig_irq_io)) {
osSignalSet(timecode_report_thread_id, 0x02); // 开始工作信号
} else {
osSignalSet(timecode_report_thread_id, 0x04); // 结束工作信号
}
}
if (gpiopin == m_xync_trigger_input_off) {
// printf("2trigger\n");
// 相机同步信号
osSignalSet(xync_signal_report_thread_id, 0x01);
}
}
@ -124,10 +153,3 @@ void ReportGeneratorService_init() {
void ReportGeneratorService_xsync_set_count(uint32_t count) { m_sync_count = count; }
uint32_t ReportGeneratorService_xsync_get_count(void) { return m_sync_count; }
uint32_t ReportGeneratorService_set_camera_sync_code_report_period(uint32_t period) {
if (period == 0) period = 1;
m_camera_sync_packet_report_period = period;
return period;
}
uint32_t ReportGeneratorService_get_camera_sync_code_report_period(void) { return m_camera_sync_packet_report_period; }
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