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@ -3,54 +3,33 @@ CAD.formats= |
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CAD.pinconfig= |
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CAD.provider= |
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Dma.Request0=USART1_RX |
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Dma.Request1=SPI2_TX |
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Dma.Request2=SPI2_RX |
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Dma.Request3=SPI1_RX |
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Dma.Request4=SPI1_TX |
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Dma.Request5=USART3_RX |
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Dma.Request6=USART6_RX |
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Dma.Request7=USART6_TX |
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Dma.RequestsNb=8 |
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Dma.SPI1_RX.3.Direction=DMA_PERIPH_TO_MEMORY |
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Dma.SPI1_RX.3.FIFOMode=DMA_FIFOMODE_DISABLE |
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Dma.SPI1_RX.3.Instance=DMA2_Stream0 |
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Dma.SPI1_RX.3.MemDataAlignment=DMA_MDATAALIGN_BYTE |
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Dma.SPI1_RX.3.MemInc=DMA_MINC_ENABLE |
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Dma.SPI1_RX.3.Mode=DMA_NORMAL |
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Dma.SPI1_RX.3.PeriphDataAlignment=DMA_PDATAALIGN_BYTE |
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Dma.SPI1_RX.3.PeriphInc=DMA_PINC_DISABLE |
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Dma.SPI1_RX.3.Priority=DMA_PRIORITY_LOW |
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Dma.SPI1_RX.3.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode |
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Dma.SPI1_TX.4.Direction=DMA_MEMORY_TO_PERIPH |
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Dma.SPI1_TX.4.FIFOMode=DMA_FIFOMODE_DISABLE |
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Dma.SPI1_TX.4.Instance=DMA2_Stream3 |
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Dma.SPI1_TX.4.MemDataAlignment=DMA_MDATAALIGN_BYTE |
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Dma.SPI1_TX.4.MemInc=DMA_MINC_ENABLE |
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Dma.SPI1_TX.4.Mode=DMA_NORMAL |
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Dma.SPI1_TX.4.PeriphDataAlignment=DMA_PDATAALIGN_BYTE |
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Dma.SPI1_TX.4.PeriphInc=DMA_PINC_DISABLE |
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Dma.SPI1_TX.4.Priority=DMA_PRIORITY_LOW |
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Dma.SPI1_TX.4.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode |
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Dma.SPI2_RX.2.Direction=DMA_PERIPH_TO_MEMORY |
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Dma.SPI2_RX.2.FIFOMode=DMA_FIFOMODE_DISABLE |
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Dma.SPI2_RX.2.Instance=DMA1_Stream3 |
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Dma.SPI2_RX.2.MemDataAlignment=DMA_MDATAALIGN_BYTE |
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Dma.SPI2_RX.2.MemInc=DMA_MINC_ENABLE |
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Dma.SPI2_RX.2.Mode=DMA_NORMAL |
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Dma.SPI2_RX.2.PeriphDataAlignment=DMA_PDATAALIGN_BYTE |
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Dma.SPI2_RX.2.PeriphInc=DMA_PINC_DISABLE |
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Dma.SPI2_RX.2.Priority=DMA_PRIORITY_LOW |
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Dma.SPI2_RX.2.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode |
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Dma.SPI2_TX.1.Direction=DMA_MEMORY_TO_PERIPH |
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Dma.SPI2_TX.1.FIFOMode=DMA_FIFOMODE_DISABLE |
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Dma.SPI2_TX.1.Instance=DMA1_Stream4 |
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Dma.SPI2_TX.1.MemDataAlignment=DMA_MDATAALIGN_BYTE |
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Dma.SPI2_TX.1.MemInc=DMA_MINC_ENABLE |
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Dma.SPI2_TX.1.Mode=DMA_NORMAL |
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Dma.SPI2_TX.1.PeriphDataAlignment=DMA_PDATAALIGN_BYTE |
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Dma.SPI2_TX.1.PeriphInc=DMA_PINC_DISABLE |
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Dma.SPI2_TX.1.Priority=DMA_PRIORITY_LOW |
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Dma.SPI2_TX.1.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode |
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Dma.Request1=SPI1_RX |
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Dma.Request2=SPI1_TX |
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Dma.Request3=USART3_RX |
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Dma.Request4=USART6_RX |
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Dma.Request5=USART6_TX |
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Dma.Request6=USART3_TX |
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Dma.RequestsNb=7 |
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Dma.SPI1_RX.1.Direction=DMA_PERIPH_TO_MEMORY |
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Dma.SPI1_RX.1.FIFOMode=DMA_FIFOMODE_DISABLE |
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Dma.SPI1_RX.1.Instance=DMA2_Stream0 |
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Dma.SPI1_RX.1.MemDataAlignment=DMA_MDATAALIGN_BYTE |
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Dma.SPI1_RX.1.MemInc=DMA_MINC_ENABLE |
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Dma.SPI1_RX.1.Mode=DMA_NORMAL |
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Dma.SPI1_RX.1.PeriphDataAlignment=DMA_PDATAALIGN_BYTE |
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Dma.SPI1_RX.1.PeriphInc=DMA_PINC_DISABLE |
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Dma.SPI1_RX.1.Priority=DMA_PRIORITY_LOW |
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Dma.SPI1_RX.1.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode |
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Dma.SPI1_TX.2.Direction=DMA_MEMORY_TO_PERIPH |
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Dma.SPI1_TX.2.FIFOMode=DMA_FIFOMODE_DISABLE |
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Dma.SPI1_TX.2.Instance=DMA2_Stream3 |
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Dma.SPI1_TX.2.MemDataAlignment=DMA_MDATAALIGN_BYTE |
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Dma.SPI1_TX.2.MemInc=DMA_MINC_ENABLE |
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Dma.SPI1_TX.2.Mode=DMA_NORMAL |
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Dma.SPI1_TX.2.PeriphDataAlignment=DMA_PDATAALIGN_BYTE |
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Dma.SPI1_TX.2.PeriphInc=DMA_PINC_DISABLE |
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Dma.SPI1_TX.2.Priority=DMA_PRIORITY_LOW |
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Dma.SPI1_TX.2.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode |
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Dma.USART1_RX.0.Direction=DMA_PERIPH_TO_MEMORY |
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Dma.USART1_RX.0.FIFOMode=DMA_FIFOMODE_DISABLE |
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Dma.USART1_RX.0.Instance=DMA2_Stream2 |
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@ -61,36 +40,46 @@ Dma.USART1_RX.0.PeriphDataAlignment=DMA_PDATAALIGN_BYTE |
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Dma.USART1_RX.0.PeriphInc=DMA_PINC_DISABLE |
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Dma.USART1_RX.0.Priority=DMA_PRIORITY_LOW |
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Dma.USART1_RX.0.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode |
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Dma.USART3_RX.5.Direction=DMA_PERIPH_TO_MEMORY |
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Dma.USART3_RX.5.FIFOMode=DMA_FIFOMODE_DISABLE |
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Dma.USART3_RX.5.Instance=DMA1_Stream1 |
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Dma.USART3_RX.5.MemDataAlignment=DMA_MDATAALIGN_BYTE |
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Dma.USART3_RX.5.MemInc=DMA_MINC_ENABLE |
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Dma.USART3_RX.5.Mode=DMA_NORMAL |
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Dma.USART3_RX.5.PeriphDataAlignment=DMA_PDATAALIGN_BYTE |
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Dma.USART3_RX.5.PeriphInc=DMA_PINC_DISABLE |
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Dma.USART3_RX.5.Priority=DMA_PRIORITY_LOW |
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Dma.USART3_RX.5.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode |
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Dma.USART6_RX.6.Direction=DMA_PERIPH_TO_MEMORY |
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Dma.USART6_RX.6.FIFOMode=DMA_FIFOMODE_DISABLE |
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Dma.USART6_RX.6.Instance=DMA2_Stream1 |
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Dma.USART6_RX.6.MemDataAlignment=DMA_MDATAALIGN_BYTE |
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Dma.USART6_RX.6.MemInc=DMA_MINC_ENABLE |
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Dma.USART6_RX.6.Mode=DMA_NORMAL |
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Dma.USART6_RX.6.PeriphDataAlignment=DMA_PDATAALIGN_BYTE |
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Dma.USART6_RX.6.PeriphInc=DMA_PINC_DISABLE |
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Dma.USART6_RX.6.Priority=DMA_PRIORITY_LOW |
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Dma.USART6_RX.6.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode |
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Dma.USART6_TX.7.Direction=DMA_MEMORY_TO_PERIPH |
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Dma.USART6_TX.7.FIFOMode=DMA_FIFOMODE_DISABLE |
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Dma.USART6_TX.7.Instance=DMA2_Stream6 |
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Dma.USART6_TX.7.MemDataAlignment=DMA_MDATAALIGN_BYTE |
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Dma.USART6_TX.7.MemInc=DMA_MINC_ENABLE |
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Dma.USART6_TX.7.Mode=DMA_NORMAL |
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Dma.USART6_TX.7.PeriphDataAlignment=DMA_PDATAALIGN_BYTE |
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Dma.USART6_TX.7.PeriphInc=DMA_PINC_DISABLE |
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Dma.USART6_TX.7.Priority=DMA_PRIORITY_LOW |
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Dma.USART6_TX.7.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode |
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Dma.USART3_RX.3.Direction=DMA_PERIPH_TO_MEMORY |
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Dma.USART3_RX.3.FIFOMode=DMA_FIFOMODE_DISABLE |
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Dma.USART3_RX.3.Instance=DMA1_Stream1 |
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Dma.USART3_RX.3.MemDataAlignment=DMA_MDATAALIGN_BYTE |
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Dma.USART3_RX.3.MemInc=DMA_MINC_ENABLE |
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Dma.USART3_RX.3.Mode=DMA_NORMAL |
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Dma.USART3_RX.3.PeriphDataAlignment=DMA_PDATAALIGN_BYTE |
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Dma.USART3_RX.3.PeriphInc=DMA_PINC_DISABLE |
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Dma.USART3_RX.3.Priority=DMA_PRIORITY_LOW |
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Dma.USART3_RX.3.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode |
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Dma.USART3_TX.6.Direction=DMA_MEMORY_TO_PERIPH |
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Dma.USART3_TX.6.FIFOMode=DMA_FIFOMODE_DISABLE |
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Dma.USART3_TX.6.Instance=DMA1_Stream3 |
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Dma.USART3_TX.6.MemDataAlignment=DMA_MDATAALIGN_BYTE |
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Dma.USART3_TX.6.MemInc=DMA_MINC_ENABLE |
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Dma.USART3_TX.6.Mode=DMA_NORMAL |
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Dma.USART3_TX.6.PeriphDataAlignment=DMA_PDATAALIGN_BYTE |
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Dma.USART3_TX.6.PeriphInc=DMA_PINC_DISABLE |
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Dma.USART3_TX.6.Priority=DMA_PRIORITY_LOW |
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Dma.USART3_TX.6.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode |
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Dma.USART6_RX.4.Direction=DMA_PERIPH_TO_MEMORY |
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Dma.USART6_RX.4.FIFOMode=DMA_FIFOMODE_DISABLE |
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Dma.USART6_RX.4.Instance=DMA2_Stream1 |
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Dma.USART6_RX.4.MemDataAlignment=DMA_MDATAALIGN_BYTE |
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Dma.USART6_RX.4.MemInc=DMA_MINC_ENABLE |
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Dma.USART6_RX.4.Mode=DMA_NORMAL |
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Dma.USART6_RX.4.PeriphDataAlignment=DMA_PDATAALIGN_BYTE |
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Dma.USART6_RX.4.PeriphInc=DMA_PINC_DISABLE |
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Dma.USART6_RX.4.Priority=DMA_PRIORITY_LOW |
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Dma.USART6_RX.4.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode |
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Dma.USART6_TX.5.Direction=DMA_MEMORY_TO_PERIPH |
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Dma.USART6_TX.5.FIFOMode=DMA_FIFOMODE_DISABLE |
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Dma.USART6_TX.5.Instance=DMA2_Stream6 |
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Dma.USART6_TX.5.MemDataAlignment=DMA_MDATAALIGN_BYTE |
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Dma.USART6_TX.5.MemInc=DMA_MINC_ENABLE |
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Dma.USART6_TX.5.Mode=DMA_NORMAL |
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Dma.USART6_TX.5.PeriphDataAlignment=DMA_PDATAALIGN_BYTE |
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Dma.USART6_TX.5.PeriphInc=DMA_PINC_DISABLE |
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Dma.USART6_TX.5.Priority=DMA_PRIORITY_LOW |
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Dma.USART6_TX.5.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode |
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ETH.IPParameters=MediaInterface,RxBuffLen,RxMode,PHY_Name_RMII,PHY_User_Name,PHY_SR,PHY_SPEED_STATUS,PHY_DUPLEX_STATUS,MACAddr |
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ETH.MACAddr=00\:80\:E1\:00\:00\:01 |
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ETH.MediaInterface=HAL_ETH_RMII_MODE |
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@ -159,18 +148,18 @@ Mcu.Package=LQFP100 |
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Mcu.Pin0=PH0-OSC_IN |
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Mcu.Pin1=PH1-OSC_OUT |
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Mcu.Pin10=PC5 |
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Mcu.Pin11=PB10 |
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Mcu.Pin12=PB11 |
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Mcu.Pin13=PB12 |
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Mcu.Pin14=PB13 |
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Mcu.Pin15=PD9 |
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Mcu.Pin16=PC6 |
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Mcu.Pin17=PC7 |
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Mcu.Pin18=PA9 |
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Mcu.Pin19=PA10 |
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Mcu.Pin11=PB11 |
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Mcu.Pin12=PB12 |
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Mcu.Pin13=PB13 |
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Mcu.Pin14=PC6 |
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Mcu.Pin15=PC7 |
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Mcu.Pin16=PA9 |
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Mcu.Pin17=PA10 |
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Mcu.Pin18=PA13 |
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Mcu.Pin19=PA14 |
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Mcu.Pin2=PC1 |
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Mcu.Pin20=PA13 |
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Mcu.Pin21=PA14 |
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Mcu.Pin20=PC10 |
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Mcu.Pin21=PC11 |
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Mcu.Pin22=PD3 |
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Mcu.Pin23=PB5 |
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Mcu.Pin24=VP_CRC_VS_CRC |
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@ -198,7 +187,6 @@ MxDb.Version=DB.6.0.70 |
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NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false |
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NVIC.DMA1_Stream1_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true |
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NVIC.DMA1_Stream3_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true |
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NVIC.DMA1_Stream4_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true |
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NVIC.DMA2_Stream0_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true |
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NVIC.DMA2_Stream1_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true |
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NVIC.DMA2_Stream2_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true |
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@ -246,8 +234,6 @@ PA7.Signal=ETH_CRS_DV |
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PA9.Locked=true |
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PA9.Mode=Asynchronous |
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PA9.Signal=USART1_TX |
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PB10.Mode=Asynchronous |
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PB10.Signal=USART3_TX |
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PB11.Mode=RMII |
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PB11.Signal=ETH_TX_EN |
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PB12.Mode=RMII |
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@ -258,6 +244,12 @@ PB5.Mode=Full_Duplex_Master |
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PB5.Signal=SPI1_MOSI |
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PC1.Mode=RMII |
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PC1.Signal=ETH_MDC |
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PC10.Locked=true |
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PC10.Mode=Asynchronous |
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PC10.Signal=USART3_TX |
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PC11.Locked=true |
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PC11.Mode=Asynchronous |
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PC11.Signal=USART3_RX |
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PC4.Mode=RMII |
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PC4.Signal=ETH_RXD0 |
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PC5.Mode=RMII |
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@ -268,8 +260,6 @@ PC7.Mode=Asynchronous |
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PC7.Signal=USART6_RX |
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PD3.Locked=true |
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PD3.Signal=GPIO_Output |
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PD9.Mode=Asynchronous |
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PD9.Signal=USART3_RX |
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PH0-OSC_IN.Mode=HSE-External-Oscillator |
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PH0-OSC_IN.Signal=RCC_OSC_IN |
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PH1-OSC_OUT.Mode=HSE-External-Oscillator |
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