diff --git a/.cproject b/.cproject
index 4db673b..cec58b3 100644
--- a/.cproject
+++ b/.cproject
@@ -146,13 +146,13 @@
+
+
-
-
-
+
@@ -279,13 +279,13 @@
+
+
-
-
-
+
diff --git a/.vscode/settings.json b/.vscode/settings.json
index 521da32..79826a1 100644
--- a/.vscode/settings.json
+++ b/.vscode/settings.json
@@ -104,7 +104,11 @@
"xutility": "c",
"cstring": "cpp",
"optional": "cpp",
- "span": "cpp"
+ "span": "cpp",
+ "zaf_log.h": "c",
+ "zaf_id.h": "c",
+ "zaf_bean.h": "c",
+ "zaf.h": "c"
},
"files.autoGuessEncoding": false,
"files.encoding": "gbk"
diff --git a/Core/Inc/spi.h b/Core/Inc/spi.h
index 43636ac..6a5279d 100644
--- a/Core/Inc/spi.h
+++ b/Core/Inc/spi.h
@@ -34,14 +34,11 @@ extern "C" {
extern SPI_HandleTypeDef hspi1;
-extern SPI_HandleTypeDef hspi2;
-
/* USER CODE BEGIN Private defines */
/* USER CODE END Private defines */
void MX_SPI1_Init(void);
-void MX_SPI2_Init(void);
/* USER CODE BEGIN Prototypes */
diff --git a/Core/Inc/stm32f4xx_it.h b/Core/Inc/stm32f4xx_it.h
index 9730164..10e1eed 100644
--- a/Core/Inc/stm32f4xx_it.h
+++ b/Core/Inc/stm32f4xx_it.h
@@ -52,17 +52,20 @@ void MemManage_Handler(void);
void BusFault_Handler(void);
void UsageFault_Handler(void);
void DebugMon_Handler(void);
+void DMA1_Stream1_IRQHandler(void);
void DMA1_Stream3_IRQHandler(void);
void DMA1_Stream4_IRQHandler(void);
void TIM1_TRG_COM_TIM11_IRQHandler(void);
void SPI1_IRQHandler(void);
-void SPI2_IRQHandler(void);
+void USART3_IRQHandler(void);
void TIM6_DAC_IRQHandler(void);
void TIM7_IRQHandler(void);
void DMA2_Stream0_IRQHandler(void);
+void DMA2_Stream1_IRQHandler(void);
void DMA2_Stream2_IRQHandler(void);
void DMA2_Stream3_IRQHandler(void);
void ETH_IRQHandler(void);
+void DMA2_Stream6_IRQHandler(void);
/* USER CODE BEGIN EFP */
/* USER CODE END EFP */
diff --git a/Core/Inc/usart.h b/Core/Inc/usart.h
index b86eff0..1928839 100644
--- a/Core/Inc/usart.h
+++ b/Core/Inc/usart.h
@@ -34,11 +34,17 @@ extern "C" {
extern UART_HandleTypeDef huart1;
+extern UART_HandleTypeDef huart3;
+
+extern UART_HandleTypeDef huart6;
+
/* USER CODE BEGIN Private defines */
/* USER CODE END Private defines */
void MX_USART1_UART_Init(void);
+void MX_USART3_UART_Init(void);
+void MX_USART6_UART_Init(void);
/* USER CODE BEGIN Prototypes */
diff --git a/Core/Src/dma.c b/Core/Src/dma.c
index f66ceff..ff7e72c 100644
--- a/Core/Src/dma.c
+++ b/Core/Src/dma.c
@@ -44,6 +44,9 @@ void MX_DMA_Init(void)
__HAL_RCC_DMA1_CLK_ENABLE();
/* DMA interrupt init */
+ /* DMA1_Stream1_IRQn interrupt configuration */
+ HAL_NVIC_SetPriority(DMA1_Stream1_IRQn, 5, 0);
+ HAL_NVIC_EnableIRQ(DMA1_Stream1_IRQn);
/* DMA1_Stream3_IRQn interrupt configuration */
HAL_NVIC_SetPriority(DMA1_Stream3_IRQn, 5, 0);
HAL_NVIC_EnableIRQ(DMA1_Stream3_IRQn);
@@ -53,12 +56,18 @@ void MX_DMA_Init(void)
/* DMA2_Stream0_IRQn interrupt configuration */
HAL_NVIC_SetPriority(DMA2_Stream0_IRQn, 5, 0);
HAL_NVIC_EnableIRQ(DMA2_Stream0_IRQn);
+ /* DMA2_Stream1_IRQn interrupt configuration */
+ HAL_NVIC_SetPriority(DMA2_Stream1_IRQn, 5, 0);
+ HAL_NVIC_EnableIRQ(DMA2_Stream1_IRQn);
/* DMA2_Stream2_IRQn interrupt configuration */
HAL_NVIC_SetPriority(DMA2_Stream2_IRQn, 5, 0);
HAL_NVIC_EnableIRQ(DMA2_Stream2_IRQn);
/* DMA2_Stream3_IRQn interrupt configuration */
HAL_NVIC_SetPriority(DMA2_Stream3_IRQn, 5, 0);
HAL_NVIC_EnableIRQ(DMA2_Stream3_IRQn);
+ /* DMA2_Stream6_IRQn interrupt configuration */
+ HAL_NVIC_SetPriority(DMA2_Stream6_IRQn, 5, 0);
+ HAL_NVIC_EnableIRQ(DMA2_Stream6_IRQn);
}
diff --git a/Core/Src/gpio.c b/Core/Src/gpio.c
index bbfbb82..e608524 100644
--- a/Core/Src/gpio.c
+++ b/Core/Src/gpio.c
@@ -70,10 +70,10 @@ void MX_GPIO_Init(void)
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
/*Configure GPIO pins : PC13 PC14 PC15 PC0
- PC6 PC7 PC8 PC9
+ PC2 PC3 PC8 PC9
PC10 PC11 PC12 */
GPIO_InitStruct.Pin = GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15|GPIO_PIN_0
- |GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9
+ |GPIO_PIN_2|GPIO_PIN_3|GPIO_PIN_8|GPIO_PIN_9
|GPIO_PIN_10|GPIO_PIN_11|GPIO_PIN_12;
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
GPIO_InitStruct.Pull = GPIO_NOPULL;
@@ -97,14 +97,14 @@ void MX_GPIO_Init(void)
GPIO_InitStruct.Pull = GPIO_NOPULL;
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
- /*Configure GPIO pins : PD8 PD9 PD10 PD11
- PD12 PD13 PD14 PD15
- PD0 PD1 PD2 PD4
- PD5 PD6 PD7 */
- GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11
- |GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15
- |GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_4
- |GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7;
+ /*Configure GPIO pins : PD8 PD10 PD11 PD12
+ PD13 PD14 PD15 PD0
+ PD1 PD2 PD4 PD5
+ PD6 PD7 */
+ GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_10|GPIO_PIN_11|GPIO_PIN_12
+ |GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15|GPIO_PIN_0
+ |GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_4|GPIO_PIN_5
+ |GPIO_PIN_6|GPIO_PIN_7;
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
GPIO_InitStruct.Pull = GPIO_NOPULL;
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
diff --git a/Core/Src/main.c b/Core/Src/main.c
index 1917bf5..ab5d587 100644
--- a/Core/Src/main.c
+++ b/Core/Src/main.c
@@ -102,7 +102,8 @@ int main(void)
MX_TIM6_Init();
MX_TIM1_Init();
MX_SPI1_Init();
- MX_SPI2_Init();
+ MX_USART3_UART_Init();
+ MX_USART6_UART_Init();
/* USER CODE BEGIN 2 */
/* USER CODE END 2 */
diff --git a/Core/Src/spi.c b/Core/Src/spi.c
index e257860..ebf7089 100644
--- a/Core/Src/spi.c
+++ b/Core/Src/spi.c
@@ -25,11 +25,8 @@
/* USER CODE END 0 */
SPI_HandleTypeDef hspi1;
-SPI_HandleTypeDef hspi2;
DMA_HandleTypeDef hdma_spi1_rx;
DMA_HandleTypeDef hdma_spi1_tx;
-DMA_HandleTypeDef hdma_spi2_tx;
-DMA_HandleTypeDef hdma_spi2_rx;
/* SPI1 init function */
void MX_SPI1_Init(void)
@@ -63,38 +60,6 @@ void MX_SPI1_Init(void)
/* USER CODE END SPI1_Init 2 */
}
-/* SPI2 init function */
-void MX_SPI2_Init(void)
-{
-
- /* USER CODE BEGIN SPI2_Init 0 */
-
- /* USER CODE END SPI2_Init 0 */
-
- /* USER CODE BEGIN SPI2_Init 1 */
-
- /* USER CODE END SPI2_Init 1 */
- hspi2.Instance = SPI2;
- hspi2.Init.Mode = SPI_MODE_MASTER;
- hspi2.Init.Direction = SPI_DIRECTION_2LINES;
- hspi2.Init.DataSize = SPI_DATASIZE_8BIT;
- hspi2.Init.CLKPolarity = SPI_POLARITY_HIGH;
- hspi2.Init.CLKPhase = SPI_PHASE_2EDGE;
- hspi2.Init.NSS = SPI_NSS_SOFT;
- hspi2.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_64;
- hspi2.Init.FirstBit = SPI_FIRSTBIT_LSB;
- hspi2.Init.TIMode = SPI_TIMODE_DISABLE;
- hspi2.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
- hspi2.Init.CRCPolynomial = 10;
- if (HAL_SPI_Init(&hspi2) != HAL_OK)
- {
- Error_Handler();
- }
- /* USER CODE BEGIN SPI2_Init 2 */
-
- /* USER CODE END SPI2_Init 2 */
-
-}
void HAL_SPI_MspInit(SPI_HandleTypeDef* spiHandle)
{
@@ -174,79 +139,6 @@ void HAL_SPI_MspInit(SPI_HandleTypeDef* spiHandle)
/* USER CODE END SPI1_MspInit 1 */
}
- else if(spiHandle->Instance==SPI2)
- {
- /* USER CODE BEGIN SPI2_MspInit 0 */
-
- /* USER CODE END SPI2_MspInit 0 */
- /* SPI2 clock enable */
- __HAL_RCC_SPI2_CLK_ENABLE();
-
- __HAL_RCC_GPIOC_CLK_ENABLE();
- __HAL_RCC_GPIOB_CLK_ENABLE();
- /**SPI2 GPIO Configuration
- PC2 ------> SPI2_MISO
- PC3 ------> SPI2_MOSI
- PB10 ------> SPI2_SCK
- */
- GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3;
- GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
- GPIO_InitStruct.Pull = GPIO_NOPULL;
- GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
- GPIO_InitStruct.Alternate = GPIO_AF5_SPI2;
- HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
-
- GPIO_InitStruct.Pin = GPIO_PIN_10;
- GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
- GPIO_InitStruct.Pull = GPIO_NOPULL;
- GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
- GPIO_InitStruct.Alternate = GPIO_AF5_SPI2;
- HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
-
- /* SPI2 DMA Init */
- /* SPI2_TX Init */
- hdma_spi2_tx.Instance = DMA1_Stream4;
- hdma_spi2_tx.Init.Channel = DMA_CHANNEL_0;
- hdma_spi2_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
- hdma_spi2_tx.Init.PeriphInc = DMA_PINC_DISABLE;
- hdma_spi2_tx.Init.MemInc = DMA_MINC_ENABLE;
- hdma_spi2_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
- hdma_spi2_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
- hdma_spi2_tx.Init.Mode = DMA_NORMAL;
- hdma_spi2_tx.Init.Priority = DMA_PRIORITY_LOW;
- hdma_spi2_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
- if (HAL_DMA_Init(&hdma_spi2_tx) != HAL_OK)
- {
- Error_Handler();
- }
-
- __HAL_LINKDMA(spiHandle,hdmatx,hdma_spi2_tx);
-
- /* SPI2_RX Init */
- hdma_spi2_rx.Instance = DMA1_Stream3;
- hdma_spi2_rx.Init.Channel = DMA_CHANNEL_0;
- hdma_spi2_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;
- hdma_spi2_rx.Init.PeriphInc = DMA_PINC_DISABLE;
- hdma_spi2_rx.Init.MemInc = DMA_MINC_ENABLE;
- hdma_spi2_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
- hdma_spi2_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
- hdma_spi2_rx.Init.Mode = DMA_NORMAL;
- hdma_spi2_rx.Init.Priority = DMA_PRIORITY_LOW;
- hdma_spi2_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
- if (HAL_DMA_Init(&hdma_spi2_rx) != HAL_OK)
- {
- Error_Handler();
- }
-
- __HAL_LINKDMA(spiHandle,hdmarx,hdma_spi2_rx);
-
- /* SPI2 interrupt Init */
- HAL_NVIC_SetPriority(SPI2_IRQn, 5, 0);
- HAL_NVIC_EnableIRQ(SPI2_IRQn);
- /* USER CODE BEGIN SPI2_MspInit 1 */
-
- /* USER CODE END SPI2_MspInit 1 */
- }
}
void HAL_SPI_MspDeInit(SPI_HandleTypeDef* spiHandle)
@@ -280,33 +172,6 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef* spiHandle)
/* USER CODE END SPI1_MspDeInit 1 */
}
- else if(spiHandle->Instance==SPI2)
- {
- /* USER CODE BEGIN SPI2_MspDeInit 0 */
-
- /* USER CODE END SPI2_MspDeInit 0 */
- /* Peripheral clock disable */
- __HAL_RCC_SPI2_CLK_DISABLE();
-
- /**SPI2 GPIO Configuration
- PC2 ------> SPI2_MISO
- PC3 ------> SPI2_MOSI
- PB10 ------> SPI2_SCK
- */
- HAL_GPIO_DeInit(GPIOC, GPIO_PIN_2|GPIO_PIN_3);
-
- HAL_GPIO_DeInit(GPIOB, GPIO_PIN_10);
-
- /* SPI2 DMA DeInit */
- HAL_DMA_DeInit(spiHandle->hdmatx);
- HAL_DMA_DeInit(spiHandle->hdmarx);
-
- /* SPI2 interrupt Deinit */
- HAL_NVIC_DisableIRQ(SPI2_IRQn);
- /* USER CODE BEGIN SPI2_MspDeInit 1 */
-
- /* USER CODE END SPI2_MspDeInit 1 */
- }
}
/* USER CODE BEGIN 1 */
diff --git a/Core/Src/stm32f4xx_it.c b/Core/Src/stm32f4xx_it.c
index 08022fc..d54c1a4 100644
--- a/Core/Src/stm32f4xx_it.c
+++ b/Core/Src/stm32f4xx_it.c
@@ -58,14 +58,15 @@
extern ETH_HandleTypeDef heth;
extern DMA_HandleTypeDef hdma_spi1_rx;
extern DMA_HandleTypeDef hdma_spi1_tx;
-extern DMA_HandleTypeDef hdma_spi2_tx;
-extern DMA_HandleTypeDef hdma_spi2_rx;
extern SPI_HandleTypeDef hspi1;
-extern SPI_HandleTypeDef hspi2;
extern TIM_HandleTypeDef htim1;
extern TIM_HandleTypeDef htim6;
extern TIM_HandleTypeDef htim7;
extern DMA_HandleTypeDef hdma_usart1_rx;
+extern DMA_HandleTypeDef hdma_usart3_rx;
+extern DMA_HandleTypeDef hdma_usart6_rx;
+extern DMA_HandleTypeDef hdma_usart6_tx;
+extern UART_HandleTypeDef huart3;
extern TIM_HandleTypeDef htim11;
/* USER CODE BEGIN EV */
@@ -171,6 +172,20 @@ void DebugMon_Handler(void)
/******************************************************************************/
/**
+ * @brief This function handles DMA1 stream1 global interrupt.
+ */
+void DMA1_Stream1_IRQHandler(void)
+{
+ /* USER CODE BEGIN DMA1_Stream1_IRQn 0 */
+
+ /* USER CODE END DMA1_Stream1_IRQn 0 */
+ HAL_DMA_IRQHandler(&hdma_usart3_rx);
+ /* USER CODE BEGIN DMA1_Stream1_IRQn 1 */
+
+ /* USER CODE END DMA1_Stream1_IRQn 1 */
+}
+
+/**
* @brief This function handles DMA1 stream3 global interrupt.
*/
void DMA1_Stream3_IRQHandler(void)
@@ -178,7 +193,6 @@ void DMA1_Stream3_IRQHandler(void)
/* USER CODE BEGIN DMA1_Stream3_IRQn 0 */
/* USER CODE END DMA1_Stream3_IRQn 0 */
- HAL_DMA_IRQHandler(&hdma_spi2_rx);
/* USER CODE BEGIN DMA1_Stream3_IRQn 1 */
/* USER CODE END DMA1_Stream3_IRQn 1 */
@@ -192,7 +206,6 @@ void DMA1_Stream4_IRQHandler(void)
/* USER CODE BEGIN DMA1_Stream4_IRQn 0 */
/* USER CODE END DMA1_Stream4_IRQn 0 */
- HAL_DMA_IRQHandler(&hdma_spi2_tx);
/* USER CODE BEGIN DMA1_Stream4_IRQn 1 */
/* USER CODE END DMA1_Stream4_IRQn 1 */
@@ -228,17 +241,17 @@ void SPI1_IRQHandler(void)
}
/**
- * @brief This function handles SPI2 global interrupt.
+ * @brief This function handles USART3 global interrupt.
*/
-void SPI2_IRQHandler(void)
+void USART3_IRQHandler(void)
{
- /* USER CODE BEGIN SPI2_IRQn 0 */
+ /* USER CODE BEGIN USART3_IRQn 0 */
- /* USER CODE END SPI2_IRQn 0 */
- HAL_SPI_IRQHandler(&hspi2);
- /* USER CODE BEGIN SPI2_IRQn 1 */
+ /* USER CODE END USART3_IRQn 0 */
+ HAL_UART_IRQHandler(&huart3);
+ /* USER CODE BEGIN USART3_IRQn 1 */
- /* USER CODE END SPI2_IRQn 1 */
+ /* USER CODE END USART3_IRQn 1 */
}
/**
@@ -284,6 +297,20 @@ void DMA2_Stream0_IRQHandler(void)
}
/**
+ * @brief This function handles DMA2 stream1 global interrupt.
+ */
+void DMA2_Stream1_IRQHandler(void)
+{
+ /* USER CODE BEGIN DMA2_Stream1_IRQn 0 */
+
+ /* USER CODE END DMA2_Stream1_IRQn 0 */
+ HAL_DMA_IRQHandler(&hdma_usart6_rx);
+ /* USER CODE BEGIN DMA2_Stream1_IRQn 1 */
+
+ /* USER CODE END DMA2_Stream1_IRQn 1 */
+}
+
+/**
* @brief This function handles DMA2 stream2 global interrupt.
*/
void DMA2_Stream2_IRQHandler(void)
@@ -325,6 +352,20 @@ void ETH_IRQHandler(void)
/* USER CODE END ETH_IRQn 1 */
}
+/**
+ * @brief This function handles DMA2 stream6 global interrupt.
+ */
+void DMA2_Stream6_IRQHandler(void)
+{
+ /* USER CODE BEGIN DMA2_Stream6_IRQn 0 */
+
+ /* USER CODE END DMA2_Stream6_IRQn 0 */
+ HAL_DMA_IRQHandler(&hdma_usart6_tx);
+ /* USER CODE BEGIN DMA2_Stream6_IRQn 1 */
+
+ /* USER CODE END DMA2_Stream6_IRQn 1 */
+}
+
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */
diff --git a/Core/Src/usart.c b/Core/Src/usart.c
index 1c84365..6fb5bab 100644
--- a/Core/Src/usart.c
+++ b/Core/Src/usart.c
@@ -25,7 +25,12 @@
/* USER CODE END 0 */
UART_HandleTypeDef huart1;
+UART_HandleTypeDef huart3;
+UART_HandleTypeDef huart6;
DMA_HandleTypeDef hdma_usart1_rx;
+DMA_HandleTypeDef hdma_usart3_rx;
+DMA_HandleTypeDef hdma_usart6_rx;
+DMA_HandleTypeDef hdma_usart6_tx;
/* USART1 init function */
@@ -56,6 +61,64 @@ void MX_USART1_UART_Init(void)
/* USER CODE END USART1_Init 2 */
}
+/* USART3 init function */
+
+void MX_USART3_UART_Init(void)
+{
+
+ /* USER CODE BEGIN USART3_Init 0 */
+
+ /* USER CODE END USART3_Init 0 */
+
+ /* USER CODE BEGIN USART3_Init 1 */
+
+ /* USER CODE END USART3_Init 1 */
+ huart3.Instance = USART3;
+ huart3.Init.BaudRate = 115200;
+ huart3.Init.WordLength = UART_WORDLENGTH_8B;
+ huart3.Init.StopBits = UART_STOPBITS_1;
+ huart3.Init.Parity = UART_PARITY_NONE;
+ huart3.Init.Mode = UART_MODE_TX_RX;
+ huart3.Init.HwFlowCtl = UART_HWCONTROL_NONE;
+ huart3.Init.OverSampling = UART_OVERSAMPLING_16;
+ if (HAL_UART_Init(&huart3) != HAL_OK)
+ {
+ Error_Handler();
+ }
+ /* USER CODE BEGIN USART3_Init 2 */
+
+ /* USER CODE END USART3_Init 2 */
+
+}
+/* USART6 init function */
+
+void MX_USART6_UART_Init(void)
+{
+
+ /* USER CODE BEGIN USART6_Init 0 */
+
+ /* USER CODE END USART6_Init 0 */
+
+ /* USER CODE BEGIN USART6_Init 1 */
+
+ /* USER CODE END USART6_Init 1 */
+ huart6.Instance = USART6;
+ huart6.Init.BaudRate = 115200;
+ huart6.Init.WordLength = UART_WORDLENGTH_8B;
+ huart6.Init.StopBits = UART_STOPBITS_1;
+ huart6.Init.Parity = UART_PARITY_NONE;
+ huart6.Init.Mode = UART_MODE_TX_RX;
+ huart6.Init.HwFlowCtl = UART_HWCONTROL_NONE;
+ huart6.Init.OverSampling = UART_OVERSAMPLING_16;
+ if (HAL_UART_Init(&huart6) != HAL_OK)
+ {
+ Error_Handler();
+ }
+ /* USER CODE BEGIN USART6_Init 2 */
+
+ /* USER CODE END USART6_Init 2 */
+
+}
void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle)
{
@@ -104,6 +167,121 @@ void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle)
/* USER CODE END USART1_MspInit 1 */
}
+ else if(uartHandle->Instance==USART3)
+ {
+ /* USER CODE BEGIN USART3_MspInit 0 */
+
+ /* USER CODE END USART3_MspInit 0 */
+ /* USART3 clock enable */
+ __HAL_RCC_USART3_CLK_ENABLE();
+
+ __HAL_RCC_GPIOB_CLK_ENABLE();
+ __HAL_RCC_GPIOD_CLK_ENABLE();
+ /**USART3 GPIO Configuration
+ PB10 ------> USART3_TX
+ PD9 ------> USART3_RX
+ */
+ GPIO_InitStruct.Pin = GPIO_PIN_10;
+ GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+ GPIO_InitStruct.Alternate = GPIO_AF7_USART3;
+ HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+ GPIO_InitStruct.Pin = GPIO_PIN_9;
+ GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+ GPIO_InitStruct.Alternate = GPIO_AF7_USART3;
+ HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
+
+ /* USART3 DMA Init */
+ /* USART3_RX Init */
+ hdma_usart3_rx.Instance = DMA1_Stream1;
+ hdma_usart3_rx.Init.Channel = DMA_CHANNEL_4;
+ hdma_usart3_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;
+ hdma_usart3_rx.Init.PeriphInc = DMA_PINC_DISABLE;
+ hdma_usart3_rx.Init.MemInc = DMA_MINC_ENABLE;
+ hdma_usart3_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
+ hdma_usart3_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
+ hdma_usart3_rx.Init.Mode = DMA_NORMAL;
+ hdma_usart3_rx.Init.Priority = DMA_PRIORITY_LOW;
+ hdma_usart3_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
+ if (HAL_DMA_Init(&hdma_usart3_rx) != HAL_OK)
+ {
+ Error_Handler();
+ }
+
+ __HAL_LINKDMA(uartHandle,hdmarx,hdma_usart3_rx);
+
+ /* USART3 interrupt Init */
+ HAL_NVIC_SetPriority(USART3_IRQn, 5, 0);
+ HAL_NVIC_EnableIRQ(USART3_IRQn);
+ /* USER CODE BEGIN USART3_MspInit 1 */
+
+ /* USER CODE END USART3_MspInit 1 */
+ }
+ else if(uartHandle->Instance==USART6)
+ {
+ /* USER CODE BEGIN USART6_MspInit 0 */
+
+ /* USER CODE END USART6_MspInit 0 */
+ /* USART6 clock enable */
+ __HAL_RCC_USART6_CLK_ENABLE();
+
+ __HAL_RCC_GPIOC_CLK_ENABLE();
+ /**USART6 GPIO Configuration
+ PC6 ------> USART6_TX
+ PC7 ------> USART6_RX
+ */
+ GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7;
+ GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+ GPIO_InitStruct.Alternate = GPIO_AF8_USART6;
+ HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
+
+ /* USART6 DMA Init */
+ /* USART6_RX Init */
+ hdma_usart6_rx.Instance = DMA2_Stream1;
+ hdma_usart6_rx.Init.Channel = DMA_CHANNEL_5;
+ hdma_usart6_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;
+ hdma_usart6_rx.Init.PeriphInc = DMA_PINC_DISABLE;
+ hdma_usart6_rx.Init.MemInc = DMA_MINC_ENABLE;
+ hdma_usart6_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
+ hdma_usart6_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
+ hdma_usart6_rx.Init.Mode = DMA_NORMAL;
+ hdma_usart6_rx.Init.Priority = DMA_PRIORITY_LOW;
+ hdma_usart6_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
+ if (HAL_DMA_Init(&hdma_usart6_rx) != HAL_OK)
+ {
+ Error_Handler();
+ }
+
+ __HAL_LINKDMA(uartHandle,hdmarx,hdma_usart6_rx);
+
+ /* USART6_TX Init */
+ hdma_usart6_tx.Instance = DMA2_Stream6;
+ hdma_usart6_tx.Init.Channel = DMA_CHANNEL_5;
+ hdma_usart6_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
+ hdma_usart6_tx.Init.PeriphInc = DMA_PINC_DISABLE;
+ hdma_usart6_tx.Init.MemInc = DMA_MINC_ENABLE;
+ hdma_usart6_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
+ hdma_usart6_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
+ hdma_usart6_tx.Init.Mode = DMA_NORMAL;
+ hdma_usart6_tx.Init.Priority = DMA_PRIORITY_LOW;
+ hdma_usart6_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
+ if (HAL_DMA_Init(&hdma_usart6_tx) != HAL_OK)
+ {
+ Error_Handler();
+ }
+
+ __HAL_LINKDMA(uartHandle,hdmatx,hdma_usart6_tx);
+
+ /* USER CODE BEGIN USART6_MspInit 1 */
+
+ /* USER CODE END USART6_MspInit 1 */
+ }
}
void HAL_UART_MspDeInit(UART_HandleTypeDef* uartHandle)
@@ -129,6 +307,52 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* uartHandle)
/* USER CODE END USART1_MspDeInit 1 */
}
+ else if(uartHandle->Instance==USART3)
+ {
+ /* USER CODE BEGIN USART3_MspDeInit 0 */
+
+ /* USER CODE END USART3_MspDeInit 0 */
+ /* Peripheral clock disable */
+ __HAL_RCC_USART3_CLK_DISABLE();
+
+ /**USART3 GPIO Configuration
+ PB10 ------> USART3_TX
+ PD9 ------> USART3_RX
+ */
+ HAL_GPIO_DeInit(GPIOB, GPIO_PIN_10);
+
+ HAL_GPIO_DeInit(GPIOD, GPIO_PIN_9);
+
+ /* USART3 DMA DeInit */
+ HAL_DMA_DeInit(uartHandle->hdmarx);
+
+ /* USART3 interrupt Deinit */
+ HAL_NVIC_DisableIRQ(USART3_IRQn);
+ /* USER CODE BEGIN USART3_MspDeInit 1 */
+
+ /* USER CODE END USART3_MspDeInit 1 */
+ }
+ else if(uartHandle->Instance==USART6)
+ {
+ /* USER CODE BEGIN USART6_MspDeInit 0 */
+
+ /* USER CODE END USART6_MspDeInit 0 */
+ /* Peripheral clock disable */
+ __HAL_RCC_USART6_CLK_DISABLE();
+
+ /**USART6 GPIO Configuration
+ PC6 ------> USART6_TX
+ PC7 ------> USART6_RX
+ */
+ HAL_GPIO_DeInit(GPIOC, GPIO_PIN_6|GPIO_PIN_7);
+
+ /* USART6 DMA DeInit */
+ HAL_DMA_DeInit(uartHandle->hdmarx);
+ HAL_DMA_DeInit(uartHandle->hdmatx);
+ /* USER CODE BEGIN USART6_MspDeInit 1 */
+
+ /* USER CODE END USART6_MspDeInit 1 */
+ }
}
/* USER CODE BEGIN 1 */
diff --git a/camera_light_src_timing_controller_stm32.ioc b/camera_light_src_timing_controller_stm32.ioc
index 49f0669..e637d0a 100644
--- a/camera_light_src_timing_controller_stm32.ioc
+++ b/camera_light_src_timing_controller_stm32.ioc
@@ -7,7 +7,10 @@ Dma.Request1=SPI2_TX
Dma.Request2=SPI2_RX
Dma.Request3=SPI1_RX
Dma.Request4=SPI1_TX
-Dma.RequestsNb=5
+Dma.Request5=USART3_RX
+Dma.Request6=USART6_RX
+Dma.Request7=USART6_TX
+Dma.RequestsNb=8
Dma.SPI1_RX.3.Direction=DMA_PERIPH_TO_MEMORY
Dma.SPI1_RX.3.FIFOMode=DMA_FIFOMODE_DISABLE
Dma.SPI1_RX.3.Instance=DMA2_Stream0
@@ -58,6 +61,36 @@ Dma.USART1_RX.0.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
Dma.USART1_RX.0.PeriphInc=DMA_PINC_DISABLE
Dma.USART1_RX.0.Priority=DMA_PRIORITY_LOW
Dma.USART1_RX.0.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode
+Dma.USART3_RX.5.Direction=DMA_PERIPH_TO_MEMORY
+Dma.USART3_RX.5.FIFOMode=DMA_FIFOMODE_DISABLE
+Dma.USART3_RX.5.Instance=DMA1_Stream1
+Dma.USART3_RX.5.MemDataAlignment=DMA_MDATAALIGN_BYTE
+Dma.USART3_RX.5.MemInc=DMA_MINC_ENABLE
+Dma.USART3_RX.5.Mode=DMA_NORMAL
+Dma.USART3_RX.5.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
+Dma.USART3_RX.5.PeriphInc=DMA_PINC_DISABLE
+Dma.USART3_RX.5.Priority=DMA_PRIORITY_LOW
+Dma.USART3_RX.5.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode
+Dma.USART6_RX.6.Direction=DMA_PERIPH_TO_MEMORY
+Dma.USART6_RX.6.FIFOMode=DMA_FIFOMODE_DISABLE
+Dma.USART6_RX.6.Instance=DMA2_Stream1
+Dma.USART6_RX.6.MemDataAlignment=DMA_MDATAALIGN_BYTE
+Dma.USART6_RX.6.MemInc=DMA_MINC_ENABLE
+Dma.USART6_RX.6.Mode=DMA_NORMAL
+Dma.USART6_RX.6.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
+Dma.USART6_RX.6.PeriphInc=DMA_PINC_DISABLE
+Dma.USART6_RX.6.Priority=DMA_PRIORITY_LOW
+Dma.USART6_RX.6.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode
+Dma.USART6_TX.7.Direction=DMA_MEMORY_TO_PERIPH
+Dma.USART6_TX.7.FIFOMode=DMA_FIFOMODE_DISABLE
+Dma.USART6_TX.7.Instance=DMA2_Stream6
+Dma.USART6_TX.7.MemDataAlignment=DMA_MDATAALIGN_BYTE
+Dma.USART6_TX.7.MemInc=DMA_MINC_ENABLE
+Dma.USART6_TX.7.Mode=DMA_NORMAL
+Dma.USART6_TX.7.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
+Dma.USART6_TX.7.PeriphInc=DMA_PINC_DISABLE
+Dma.USART6_TX.7.Priority=DMA_PRIORITY_LOW
+Dma.USART6_TX.7.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode
ETH.IPParameters=MediaInterface,RxBuffLen,RxMode,PHY_Name_RMII,PHY_User_Name,PHY_SR,PHY_SPEED_STATUS,PHY_DUPLEX_STATUS,MACAddr
ETH.MACAddr=00\:80\:E1\:00\:00\:01
ETH.MediaInterface=HAL_ETH_RMII_MODE
@@ -105,12 +138,13 @@ Mcu.CPN=STM32F407VET6
Mcu.Family=STM32F4
Mcu.IP0=CRC
Mcu.IP1=DMA
-Mcu.IP10=SYS
-Mcu.IP11=TIM1
-Mcu.IP12=TIM3
-Mcu.IP13=TIM6
-Mcu.IP14=TIM7
-Mcu.IP15=USART1
+Mcu.IP10=TIM1
+Mcu.IP11=TIM3
+Mcu.IP12=TIM6
+Mcu.IP13=TIM7
+Mcu.IP14=USART1
+Mcu.IP15=USART3
+Mcu.IP16=USART6
Mcu.IP2=ETH
Mcu.IP3=FREERTOS
Mcu.IP4=LWIP
@@ -118,54 +152,58 @@ Mcu.IP5=NVIC
Mcu.IP6=RCC
Mcu.IP7=RNG
Mcu.IP8=SPI1
-Mcu.IP9=SPI2
-Mcu.IPNb=16
+Mcu.IP9=SYS
+Mcu.IPNb=17
Mcu.Name=STM32F407V(E-G)Tx
Mcu.Package=LQFP100
Mcu.Pin0=PH0-OSC_IN
Mcu.Pin1=PH1-OSC_OUT
-Mcu.Pin10=PA7
-Mcu.Pin11=PC4
-Mcu.Pin12=PC5
-Mcu.Pin13=PB10
-Mcu.Pin14=PB11
-Mcu.Pin15=PB12
-Mcu.Pin16=PB13
-Mcu.Pin17=PA9
-Mcu.Pin18=PA10
-Mcu.Pin19=PA13
+Mcu.Pin10=PC5
+Mcu.Pin11=PB10
+Mcu.Pin12=PB11
+Mcu.Pin13=PB12
+Mcu.Pin14=PB13
+Mcu.Pin15=PD9
+Mcu.Pin16=PC6
+Mcu.Pin17=PC7
+Mcu.Pin18=PA9
+Mcu.Pin19=PA10
Mcu.Pin2=PC1
-Mcu.Pin20=PA14
-Mcu.Pin21=PD3
-Mcu.Pin22=PB5
-Mcu.Pin23=VP_CRC_VS_CRC
-Mcu.Pin24=VP_FREERTOS_VS_CMSIS_V1
-Mcu.Pin25=VP_LWIP_VS_Enabled
-Mcu.Pin26=VP_RNG_VS_RNG
-Mcu.Pin27=VP_SYS_VS_tim11
-Mcu.Pin28=VP_TIM1_VS_ClockSourceINT
-Mcu.Pin29=VP_TIM3_VS_ClockSourceINT
-Mcu.Pin3=PC2
-Mcu.Pin30=VP_TIM6_VS_ClockSourceINT
-Mcu.Pin31=VP_TIM7_VS_ClockSourceINT
-Mcu.Pin4=PC3
-Mcu.Pin5=PA1
-Mcu.Pin6=PA2
-Mcu.Pin7=PA4
-Mcu.Pin8=PA5
-Mcu.Pin9=PA6
-Mcu.PinsNb=32
+Mcu.Pin20=PA13
+Mcu.Pin21=PA14
+Mcu.Pin22=PD3
+Mcu.Pin23=PB5
+Mcu.Pin24=VP_CRC_VS_CRC
+Mcu.Pin25=VP_FREERTOS_VS_CMSIS_V1
+Mcu.Pin26=VP_LWIP_VS_Enabled
+Mcu.Pin27=VP_RNG_VS_RNG
+Mcu.Pin28=VP_SYS_VS_tim11
+Mcu.Pin29=VP_TIM1_VS_ClockSourceINT
+Mcu.Pin3=PA1
+Mcu.Pin30=VP_TIM3_VS_ClockSourceINT
+Mcu.Pin31=VP_TIM6_VS_ClockSourceINT
+Mcu.Pin32=VP_TIM7_VS_ClockSourceINT
+Mcu.Pin4=PA2
+Mcu.Pin5=PA4
+Mcu.Pin6=PA5
+Mcu.Pin7=PA6
+Mcu.Pin8=PA7
+Mcu.Pin9=PC4
+Mcu.PinsNb=33
Mcu.ThirdPartyNb=0
Mcu.UserConstants=
Mcu.UserName=STM32F407VETx
MxCube.Version=6.7.0
MxDb.Version=DB.6.0.70
NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false
+NVIC.DMA1_Stream1_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true
NVIC.DMA1_Stream3_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true
NVIC.DMA1_Stream4_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true
NVIC.DMA2_Stream0_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true
+NVIC.DMA2_Stream1_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true
NVIC.DMA2_Stream2_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true
NVIC.DMA2_Stream3_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true
+NVIC.DMA2_Stream6_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true
NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false
NVIC.ETH_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true
NVIC.ForceEnableDMAVector=true
@@ -175,7 +213,6 @@ NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:fa
NVIC.PendSV_IRQn=true\:15\:0\:false\:false\:false\:true\:false\:false\:false
NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
NVIC.SPI1_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true\:true
-NVIC.SPI2_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true\:true
NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:false\:false\:false\:false\:false
NVIC.SavedPendsvIrqHandlerGenerated=true
NVIC.SavedSvcallIrqHandlerGenerated=true
@@ -186,6 +223,7 @@ NVIC.TIM6_DAC_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true\:true
NVIC.TIM7_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true\:true
NVIC.TimeBase=TIM1_TRG_COM_TIM11_IRQn
NVIC.TimeBaseIP=TIM11
+NVIC.USART3_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true\:true
NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false
PA1.Mode=RMII
PA1.Signal=ETH_REF_CLK
@@ -208,8 +246,8 @@ PA7.Signal=ETH_CRS_DV
PA9.Locked=true
PA9.Mode=Asynchronous
PA9.Signal=USART1_TX
-PB10.Mode=Full_Duplex_Master
-PB10.Signal=SPI2_SCK
+PB10.Mode=Asynchronous
+PB10.Signal=USART3_TX
PB11.Mode=RMII
PB11.Signal=ETH_TX_EN
PB12.Mode=RMII
@@ -220,16 +258,18 @@ PB5.Mode=Full_Duplex_Master
PB5.Signal=SPI1_MOSI
PC1.Mode=RMII
PC1.Signal=ETH_MDC
-PC2.Mode=Full_Duplex_Master
-PC2.Signal=SPI2_MISO
-PC3.Mode=Full_Duplex_Master
-PC3.Signal=SPI2_MOSI
PC4.Mode=RMII
PC4.Signal=ETH_RXD0
PC5.Mode=RMII
PC5.Signal=ETH_RXD1
+PC6.Mode=Asynchronous
+PC6.Signal=USART6_TX
+PC7.Mode=Asynchronous
+PC7.Signal=USART6_RX
PD3.Locked=true
PD3.Signal=GPIO_Output
+PD9.Mode=Asynchronous
+PD9.Signal=USART3_RX
PH0-OSC_IN.Mode=HSE-External-Oscillator
PH0-OSC_IN.Signal=RCC_OSC_IN
PH1-OSC_OUT.Mode=HSE-External-Oscillator
@@ -265,7 +305,7 @@ ProjectManager.ToolChainLocation=
ProjectManager.UAScriptAfterPath=
ProjectManager.UAScriptBeforePath=
ProjectManager.UnderRoot=true
-ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_DMA_Init-DMA-false-HAL-true,4-MX_USART1_UART_Init-USART1-false-HAL-true,5-MX_TIM3_Init-TIM3-false-HAL-true,6-MX_CRC_Init-CRC-false-HAL-true,7-MX_RNG_Init-RNG-false-HAL-true,8-MX_TIM7_Init-TIM7-false-HAL-true,9-MX_TIM6_Init-TIM6-false-HAL-true,10-MX_TIM1_Init-TIM1-false-HAL-true,11-MX_LWIP_Init-LWIP-false-HAL-false,12-MX_SPI1_Init-SPI1-false-HAL-true,13-MX_SPI2_Init-SPI2-false-HAL-true
+ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_DMA_Init-DMA-false-HAL-true,4-MX_USART1_UART_Init-USART1-false-HAL-true,5-MX_TIM3_Init-TIM3-false-HAL-true,6-MX_CRC_Init-CRC-false-HAL-true,7-MX_RNG_Init-RNG-false-HAL-true,8-MX_TIM7_Init-TIM7-false-HAL-true,9-MX_TIM6_Init-TIM6-false-HAL-true,10-MX_TIM1_Init-TIM1-false-HAL-true,11-MX_LWIP_Init-LWIP-false-HAL-false,12-MX_SPI1_Init-SPI1-false-HAL-true,13-MX_USART3_UART_Init-USART3-false-HAL-true,14-MX_USART6_UART_Init-USART6-false-HAL-true
RCC.48MHZClocksFreq_Value=48000000
RCC.AHBFreq_Value=144000000
RCC.APB1CLKDivider=RCC_HCLK_DIV4
@@ -316,15 +356,6 @@ SPI1.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate,VirtualNSS,BaudRa
SPI1.Mode=SPI_MODE_MASTER
SPI1.VirtualNSS=VM_NSSHARD
SPI1.VirtualType=VM_MASTER
-SPI2.BaudRatePrescaler=SPI_BAUDRATEPRESCALER_64
-SPI2.CLKPhase=SPI_PHASE_2EDGE
-SPI2.CLKPolarity=SPI_POLARITY_HIGH
-SPI2.CalculateBaudRate=562.5 KBits/s
-SPI2.Direction=SPI_DIRECTION_2LINES
-SPI2.FirstBit=SPI_FIRSTBIT_LSB
-SPI2.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate,CLKPolarity,CLKPhase,FirstBit,BaudRatePrescaler
-SPI2.Mode=SPI_MODE_MASTER
-SPI2.VirtualType=VM_MASTER
TIM1.IPParameters=Period,Prescaler
TIM1.Period=9999
TIM1.Prescaler=143
@@ -338,6 +369,10 @@ TIM7.Prescaler=81
USART1.BaudRate=921600
USART1.IPParameters=VirtualMode,BaudRate
USART1.VirtualMode=VM_ASYNC
+USART3.IPParameters=VirtualMode
+USART3.VirtualMode=VM_ASYNC
+USART6.IPParameters=VirtualMode
+USART6.VirtualMode=VM_ASYNC
VP_CRC_VS_CRC.Mode=CRC_Activate
VP_CRC_VS_CRC.Signal=CRC_VS_CRC
VP_FREERTOS_VS_CMSIS_V1.Mode=CMSIS_V1
diff --git a/libzaf/zaf.h b/libzaf/zaf.h
index 4e8e217..3c58086 100644
--- a/libzaf/zaf.h
+++ b/libzaf/zaf.h
@@ -11,6 +11,7 @@ extern "C" {
#include "zaf_log.h"
#include "zaf_id.h"
#include "zaf_udp.h"
+#include "zaf_bean.h"
#ifdef __cplusplus
}
#endif
\ No newline at end of file
diff --git a/libzaf/zaf_bean.h b/libzaf/zaf_bean.h
new file mode 100644
index 0000000..2330982
--- /dev/null
+++ b/libzaf/zaf_bean.h
@@ -0,0 +1,6 @@
+#pragma once
+#include
+typedef struct {
+ uint8_t* data;
+ uint32_t len;
+} zaf_buf_t;
diff --git a/usrc/base_service/config_service.c b/usrc/base_service/config_service.c
index 12a5bb7..1d12793 100644
--- a/usrc/base_service/config_service.c
+++ b/usrc/base_service/config_service.c
@@ -22,15 +22,14 @@ static void create_default_config(config_t *now_cfg, bool cfg_is_error, config_t
IP4_ADDR((ip4_addr_t *)&default_cfg->netmask, 255, 255, 255, 0);
default_cfg->obtaining_ip_mode = obtaining_ip_mode_type_static; // dhcp
- default_cfg->config0 = KXSYNC_REG_STM32_CONFIG0_MASK_TIMECODE_REPORT_ENABLE | //
- KXSYNC_REG_STM32_CONFIG0_MASK_CAMERA_SYNC_REPORT_ENABLE;
+ default_cfg->config0 = 0;
static mac_t mac;
if (now_cfg->mac[0] == 0 && now_cfg->mac[1] == 0 && now_cfg->mac[2] == 0 && now_cfg->mac[3] == 0 && now_cfg->mac[4] == 0 && now_cfg->mac[5] == 0) {
- zaf_id_generate_random_mac(&mac);
+ zaf_id_generate_random_mac(&mac);
ZLOGI(TAG, "gen random mac is %02x:%02x:%02x:%02x:%02x:%02x", mac.mac[0], mac.mac[1], mac.mac[2], mac.mac[3], mac.mac[4], mac.mac[5]);
} else if (now_cfg->mac[0] == 0xff && now_cfg->mac[1] == 0xff && now_cfg->mac[2] == 0xff && now_cfg->mac[3] == 0xff && now_cfg->mac[4] == 0xff && now_cfg->mac[5] == 0xff) {
- zaf_id_generate_random_mac(&mac);
+ zaf_id_generate_random_mac(&mac);
ZLOGI(TAG, "gen random mac is %02x:%02x:%02x:%02x:%02x:%02x", mac.mac[0], mac.mac[1], mac.mac[2], mac.mac[3], mac.mac[4], mac.mac[5]);
} else {
memcpy(&mac.mac, now_cfg->mac, 6);
@@ -44,15 +43,15 @@ void config_init(void) {
/**
* @brief flash初始化
*/
- zaf_flash_init((uint32_t *)&_config, sizeof(config_t) / 4);
+ zaf_flash_init((uint32_t *)&_config, sizeof(config_t) / 4);
bool cfg_is_error = !zaf_flash_check();
create_default_config(&_config, cfg_is_error, &_default_val_config);
- zaf_flash_set_default_data((uint32_t *)&_default_val_config);
+ zaf_flash_set_default_data((uint32_t *)&_default_val_config);
if (cfg_is_error) {
- zaf_flash_factory_reset();
+ zaf_flash_factory_reset();
}
/**
* @brief 打印配置信息
@@ -60,12 +59,12 @@ void config_init(void) {
dump_config(&_config);
}
config_t *config_get(void) { return &_config; }
-void config_flush(void) {zaf_flash_flush(); }
-void config_factory_reset(void) {zaf_flash_factory_reset(); }
+void config_flush(void) { zaf_flash_flush(); }
+void config_factory_reset(void) { zaf_flash_factory_reset(); }
void config_generate_random_mac(void) {
static mac_t mac;
- zaf_id_generate_random_mac(&mac);
+ zaf_id_generate_random_mac(&mac);
ZLOGI(TAG, "gen random mac is %02x:%02x:%02x:%02x:%02x:%02x", mac.mac[0], mac.mac[1], mac.mac[2], mac.mac[3], mac.mac[4], mac.mac[5]);
memset(&_config.mac[0], 0, sizeof(_config.mac));
memcpy(&_config.mac[0], mac.mac, 6);
diff --git a/usrc/base_service/fpga_if.c b/usrc/base_service/fpga_if.c
index 1d728e9..897a105 100644
--- a/usrc/base_service/fpga_if.c
+++ b/usrc/base_service/fpga_if.c
@@ -1,17 +1,14 @@
#include "fpga_if.h"
-#include "xsync_regs.hpp"
/**
* @brief fpga_if初始化
*/
#define TAG "fpga_if"
static fpga_if_t fpga_if;
-zaf_gpio_t spi2_cs;
+zaf_gpio_t spi_cs;
SemaphoreHandle_t m_spilock;
void fpga_if_init() { //
- // fpga_if.spi1 = &hspi1;
- // fpga_if.spi2 = &hspi2;
uint8_t rxbuf[1];
m_spilock = xSemaphoreCreateRecursiveMutex();
/**
@@ -19,38 +16,36 @@ void fpga_if_init() { //
* 假传输一帧数据，使时钟线变为高电平。
*/
- fpga_if.spi2 = &hspi2;
- zaf_gpio_init_as_output(&spi2_cs, PB9, kxs_gpio_nopull, false, true);
- HAL_SPI_Receive(fpga_if.spi2, rxbuf, 1, 1000);
+ fpga_if.spi1 = &hspi1;
+ zaf_gpio_init_as_output(&spi_cs, SPI_CS, kxs_gpio_nopull, false, true);
+ HAL_SPI_Receive(fpga_if.spi1, rxbuf, 1, 1000);
- // fpga_if.spi2 = &hspi1;
- // HAL_SPI_Receive(fpga_if.spi2, rxbuf, 1, 1000);
-
- fpga_if.timecode_irq_pin = PD6;
- fpga_if.camera_sync_code_irq_pin = PD4;
- fpga_if.xsync_workstate_start_sig_irq_io_pin = PD5;
- fpga_if.reset_pin = PD7;
+ //! ioa0 临时用于当作复位引脚
+ zaf_gpio_init_as_output(&fpga_if.fpga_reserve_ioa0, FPGA_RESERVE_IOA0, kxs_gpio_od, false, false);
+
+ zaf_gpio_init_as_output(&fpga_if.fpga_reserve_ioa1, FPGA_RESERVE_IOA1, kxs_gpio_od, false, false);
+ zaf_gpio_init_as_output(&fpga_if.fpga_reserve_ioa2, FPGA_RESERVE_IOA2, kxs_gpio_od, false, false);
+ zaf_gpio_init_as_output(&fpga_if.fpga_reserve_ioa3, FPGA_RESERVE_IOA3, kxs_gpio_od, false, false);
+ zaf_gpio_init_as_output(&fpga_if.fpga_reserve_ioa4, FPGA_RESERVE_IOA4, kxs_gpio_od, false, false);
+ zaf_gpio_init_as_output(&fpga_if.fpga_reserve_ioa5, FPGA_RESERVE_IOA5, kxs_gpio_od, false, false);
+ zaf_gpio_init_as_output(&fpga_if.fpga_reserve_ioa6, FPGA_RESERVE_IOA6, kxs_gpio_od, false, false);
+ zaf_gpio_init_as_output(&fpga_if.fpga_reserve_ioa7, FPGA_RESERVE_IOA7, kxs_gpio_od, false, false);
+ zaf_gpio_init_as_output(&fpga_if.fpga_reserve_iob0, FPGA_RESERVE_IOB0, kxs_gpio_od, false, false);
+ zaf_gpio_init_as_output(&fpga_if.fpga_reserve_iob1, FPGA_RESERVE_IOB1, kxs_gpio_od, false, false);
+ zaf_gpio_init_as_output(&fpga_if.fpga_reserve_iob2, FPGA_RESERVE_IOB2, kxs_gpio_od, false, false);
+ zaf_gpio_init_as_output(&fpga_if.fpga_reserve_iob3, FPGA_RESERVE_IOB3, kxs_gpio_od, false, false);
+ zaf_gpio_init_as_output(&fpga_if.fpga_reserve_iob4, FPGA_RESERVE_IOB4, kxs_gpio_od, false, false);
+ zaf_gpio_init_as_output(&fpga_if.fpga_reserve_iob5, FPGA_RESERVE_IOB5, kxs_gpio_od, false, false);
+ zaf_gpio_init_as_output(&fpga_if.fpga_reserve_iob6, FPGA_RESERVE_IOB6, kxs_gpio_od, false, false);
+ zaf_gpio_init_as_output(&fpga_if.fpga_reserve_iob7, FPGA_RESERVE_IOB7, kxs_gpio_od, false, false);
#if 1
- zaf_gpio_init_as_input(&fpga_if.camera_sync_code_irq_io, fpga_if.camera_sync_code_irq_pin, kxs_gpio_pulldown, kxs_gpio_rising_irq, false);
- zaf_gpio_init_as_input(&fpga_if.timecode_irq_io, fpga_if.timecode_irq_pin, kxs_gpio_pulldown, kxs_gpio_rising_irq, false);
- zaf_gpio_init_as_input(&fpga_if.xsync_workstate_start_sig_irq_io, fpga_if.xsync_workstate_start_sig_irq_io_pin, kxs_gpio_pulldown, kxs_gpio_rising_and_falling_irq, false);
- zaf_gpio_init_as_output(&fpga_if.reset_pin_io, fpga_if.reset_pin, kxs_gpio_pullup, false, false);
-
- zaf_gpio_write(&fpga_if.reset_pin_io, false);
- zaf_delay_us(1);
- zaf_gpio_write(&fpga_if.reset_pin_io, true);
+ zaf_gpio_write(&fpga_if.fpga_reserve_ioa0, false);
+ zaf_delay_us(1);
+ zaf_gpio_write(&fpga_if.fpga_reserve_ioa0, true);
#endif
}
-void fpga_if_get_timecode(uint32_t *timecode0, uint32_t *timecode1) {
- fpga_if_spi_read_data_02(sys_timecode_data0, timecode0);
- fpga_if_spi_read_data_02(sys_timecode_data1, timecode1);
- return;
-}
-void fpga_if_get_record_state(uint32_t *recordstate) {
- fpga_if_spi_read_data_02(record_sig_gen_record_state, recordstate);
- return;
-}
+
/**
* @brief SPI寄存器写指令
*
@@ -98,28 +93,21 @@ static void _fpga_if_spi_read_data(SPI_HandleTypeDef *hspi, uint32_t add, uint32
*rxdata = rxbuf[2] | (rxbuf[3] << 8) | (rxbuf[4] << 16) | (rxbuf[5] << 24);
}
-void fpga_if_spi_write_data_01(uint32_t add, uint32_t txdata, uint32_t *rxdata) {
+void fpga_if_spi_write_data(uint32_t add, uint32_t txdata, uint32_t *rxdata) {
+ xSemaphoreTakeRecursive(m_spilock, portMAX_DELAY);
+ zaf_gpio_write(&spi_cs, false);
_fpga_if_spi_write_data(fpga_if.spi1, add, txdata, rxdata);
+ zaf_gpio_write(&spi_cs, true);
+ zaf_delay_us(1);
+ zaf_gpio_write(&spi_cs, false);
_fpga_if_spi_read_data(fpga_if.spi1, add, rxdata);
-}
-void fpga_if_spi_read_data_01(uint32_t add, uint32_t *rxdata) { _fpga_if_spi_read_data(fpga_if.spi1, add, rxdata); }
-void fpga_if_spi_write_data_02(uint32_t add, uint32_t txdata, uint32_t *rxdata) {
- xSemaphoreTakeRecursive(m_spilock, portMAX_DELAY);
- zaf_gpio_write(&spi2_cs, false);
- _fpga_if_spi_write_data(fpga_if.spi2, add, txdata, rxdata);
- zaf_gpio_write(&spi2_cs, true);
- zaf_delay_us(1);
- zaf_gpio_write(&spi2_cs, false);
- _fpga_if_spi_read_data(fpga_if.spi2, add, rxdata);
- zaf_gpio_write(&spi2_cs, true);
+ zaf_gpio_write(&spi_cs, true);
xSemaphoreGiveRecursive(m_spilock);
}
-void fpga_if_spi_read_data_02(uint32_t add, uint32_t *rxdata) {
+void fpga_if_spi_read_data(uint32_t add, uint32_t *rxdata) {
xSemaphoreTakeRecursive(m_spilock, portMAX_DELAY);
- zaf_gpio_write(&spi2_cs, false);
- _fpga_if_spi_read_data(fpga_if.spi2, add, rxdata);
- zaf_gpio_write(&spi2_cs, true);
+ zaf_gpio_write(&spi_cs, false);
+ _fpga_if_spi_read_data(fpga_if.spi1, add, rxdata);
+ zaf_gpio_write(&spi_cs, true);
xSemaphoreGiveRecursive(m_spilock);
}
-
-fpga_if_t *fpga_if_get_instance() { return &fpga_if; }
diff --git a/usrc/base_service/fpga_if.h b/usrc/base_service/fpga_if.h
index cbfc125..89d2079 100644
--- a/usrc/base_service/fpga_if.h
+++ b/usrc/base_service/fpga_if.h
@@ -11,27 +11,25 @@ typedef struct {
* @brief 指令SPI 接口
*/
SPI_HandleTypeDef *spi1;
- SPI_HandleTypeDef *spi2;
+ zaf_gpio_t reset_pin_io;
+
+ zaf_gpio_t fpga_reserve_ioa0;
+ zaf_gpio_t fpga_reserve_ioa1;
+ zaf_gpio_t fpga_reserve_ioa2;
+ zaf_gpio_t fpga_reserve_ioa3;
+ zaf_gpio_t fpga_reserve_ioa4;
+ zaf_gpio_t fpga_reserve_ioa5;
+ zaf_gpio_t fpga_reserve_ioa6;
+ zaf_gpio_t fpga_reserve_ioa7;
+ zaf_gpio_t fpga_reserve_iob0;
+ zaf_gpio_t fpga_reserve_iob1;
+ zaf_gpio_t fpga_reserve_iob2;
+ zaf_gpio_t fpga_reserve_iob3;
+ zaf_gpio_t fpga_reserve_iob4;
+ zaf_gpio_t fpga_reserve_iob5;
+ zaf_gpio_t fpga_reserve_iob6;
+ zaf_gpio_t fpga_reserve_iob7;
- /**
- * @brief timecode并口
- */
-
- zaf_gpio_t timecode_add[4];
- zaf_gpio_t timecode_data[8];
-
- Pin_t timecode_add_pin[4];
- Pin_t timecode_data_pin[8];
-
- Pin_t timecode_irq_pin;
- Pin_t camera_sync_code_irq_pin;
- Pin_t xsync_workstate_start_sig_irq_io_pin;
- Pin_t reset_pin;
-
- zaf_gpio_t timecode_irq_io;
- zaf_gpio_t camera_sync_code_irq_io;
- zaf_gpio_t xsync_workstate_start_sig_irq_io;
- zaf_gpio_t reset_pin_io;
} fpga_if_t;
/**
@@ -40,45 +38,20 @@ typedef struct {
*/
void fpga_if_init();
/**
- * @brief 读取当前timecode
- *
- * @param timecode0
- * @param timecode1
- */
-void fpga_if_get_timecode(uint32_t *timecode0, uint32_t *timecode1);
-/**
- * @brief SPI寄存器写指令_01 FPGA寄存器读写SPI
- *
- * @param add
- * @param txdata
- * @param rxdata
- */
-void fpga_if_spi_write_data_01(uint32_t add, uint32_t txdata, uint32_t *rxdata);
-/**
- * @brief SPI寄存器读指令 FPGA寄存器读写SPI
- *
- * @param add
- * @param rxdata
- */
-void fpga_if_spi_read_data_01(uint32_t add, uint32_t *rxdata);
-
-/**
* @brief SPI寄存器写指令 FPGA备用SPI
*
* @param add
* @param txdata
* @param rxdata
*/
-void fpga_if_spi_write_data_02(uint32_t add, uint32_t txdata, uint32_t *rxdata);
+void fpga_if_spi_write_data(uint32_t add, uint32_t txdata, uint32_t *rxdata);
/**
* @brief SPI寄存器读指令 FPGA备用SPI
*
* @param add
* @param rxdata
*/
-void fpga_if_spi_read_data_02(uint32_t add, uint32_t *rxdata);
-
-void fpga_if_get_record_state(uint32_t *workstate);
+void fpga_if_spi_read_data(uint32_t add, uint32_t *rxdata);
fpga_if_t *fpga_if_get_instance();
diff --git a/usrc/base_service/light_ctrl_service.c b/usrc/base_service/light_ctrl_service.c
new file mode 100644
index 0000000..9832a4b
--- /dev/null
+++ b/usrc/base_service/light_ctrl_service.c
@@ -0,0 +1,14 @@
+#include "light_ctrl_service.h"
+zaf_gpio_t rlight;
+zaf_gpio_t glight;
+zaf_gpio_t blight;
+
+void LightCtrlService_init() {
+ zaf_gpio_init_as_output(&rlight, LED_R_PIN, kxs_gpio_nopull, false, false);
+ zaf_gpio_init_as_output(&glight, LED_G_PIN, kxs_gpio_nopull, false, false);
+ zaf_gpio_init_as_output(&blight, LED_B_PIN, kxs_gpio_nopull, false, false);
+}
+
+void LightCtrlService_RedLight_setState(bool state) { zaf_gpio_write(&rlight, state); }
+void LightCtrlService_BlueLight_setState(bool state) { zaf_gpio_write(&blight, state); }
+void LightCtrlService_GreenLight_setState(bool state) { zaf_gpio_write(&glight, state); }
\ No newline at end of file
diff --git a/usrc/base_service/light_ctrl_service.h b/usrc/base_service/light_ctrl_service.h
new file mode 100644
index 0000000..e84109a
--- /dev/null
+++ b/usrc/base_service/light_ctrl_service.h
@@ -0,0 +1,17 @@
+#pragma once
+#include
+
+#include "project_dep.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void LightCtrlService_init();
+
+void LightCtrlService_RedLight_setState(bool state);
+void LightCtrlService_BlueLight_setState(bool state);
+void LightCtrlService_GreenLight_setState(bool state);
+
+#ifdef __cplusplus
+}
+#endif
\ No newline at end of file
diff --git a/usrc/base_service/mac_generator.h b/usrc/base_service/mac_generator.h
deleted file mode 100644
index e69de29..0000000
diff --git a/usrc/base_service/xsync_regs.hpp b/usrc/base_service/xsync_regs.hpp
deleted file mode 100644
index 32e416f..0000000
--- a/usrc/base_service/xsync_regs.hpp
+++ /dev/null
@@ -1,260 +0,0 @@
-#pragma once
-#define REG_ADD_OFF_STM32 (0x0000)
-#define REG_ADD_OFF_STM32_CONFIG_START_ADD (0x0010)
-
-#define REGADDOFF__FPGA_INFO (0x0020)
-#define REGADDOFF__TTLIN (0x0100)
-#define REGADDOFF__EXTERNAL_TIMECODE (0x0120)
-#define REGADDOFF__EXTERNAL_GENLOCK (0x0130)
-#define REGADDOFF__INTERNAL_TIMECODE (0x0300)
-#define REGADDOFF__INTERNAL_GENLOCK (0x0310)
-#define REGADDOFF__INTERNAL_CLOCK (0x0320)
-#define REGADDOFF__TTLOUT1 (0x0200)
-#define REGADDOFF__TTLOUT2 (0x0210)
-#define REGADDOFF__TTLOUT3 (0x0220)
-#define REGADDOFF__TTLOUT4 (0x0230)
-#define REGADDOFF__TIMECODE_OUT (0x0240)
-#define REGADDOFF__GENLOCK_OUT (0x0250)
-#define REGADDOFF__CAMERA_SYNC_OUT (0x0260)
-#define REGADDOFF__SYS_TIMECODE (0x0400)
-#define REGADDOFF__SYS_GENLOCK (0x0410)
-#define REGADDOFF__SYS_CLOCK (0x0420)
-#define REGADDOFF__RECORD_SIG_GENERATOR (0x0500)
-
-typedef enum {
- /**
- * @brief
- * REG 0(16) 设备信息基础寄存器
- */
- ksoftware_version = 0,
- kmanufacturer0 = 1,
- kmanufacturer1 = 2,
- kproduct_type_id = 3,
- ksn_id0 = 4,
- ksn_id1 = 5,
- ksn_id2 = 6,
- kmac0 = 7,
- kmac1 = 8,
-
- /**
- * @brief
- * REG 16(32) STM32配置寄存器0
- */
- kstm32_obtaining_ip_mode = REG_ADD_OFF_STM32_CONFIG_START_ADD + 0,
- kstm32_ip = REG_ADD_OFF_STM32_CONFIG_START_ADD + 1,
- kstm32_gw = REG_ADD_OFF_STM32_CONFIG_START_ADD + 2,
- kstm32_netmask = REG_ADD_OFF_STM32_CONFIG_START_ADD + 3,
- kstm32_config0 = REG_ADD_OFF_STM32_CONFIG_START_ADD + 4, // bit0: timecode report enable, bit1: camera sync report enable
- kstm32_camera_sync_signal_count = REG_ADD_OFF_STM32_CONFIG_START_ADD + 5, // 写任意数值之后清零
- kstm32_camera_sync_signal_count_report_period = REG_ADD_OFF_STM32_CONFIG_START_ADD + 6, // 上报周期，单位为帧数
-
- kstm32_action0 = REG_ADD_OFF_STM32_CONFIG_START_ADD + 14, // action reg
- kstm32_action_val0 = REG_ADD_OFF_STM32_CONFIG_START_ADD + 15, // action val reg
-
- /**
- * @brief
- * REG 48(32) FPGA配置寄存器0
- */
- kfpga_info_reg0 = REGADDOFF__FPGA_INFO + 0,
- kfpga_info_reg1 = REGADDOFF__FPGA_INFO + 1,
- kfpga_info_reg2 = REGADDOFF__FPGA_INFO + 2,
- kfpga_info_reg3 = REGADDOFF__FPGA_INFO + 3,
- kfpga_info_reg4 = REGADDOFF__FPGA_INFO + 4,
- kfpga_info_reg5 = REGADDOFF__FPGA_INFO + 5,
- kfpga_info_reg6 = REGADDOFF__FPGA_INFO + 6,
- kfpga_info_reg7 = REGADDOFF__FPGA_INFO + 7,
- kfpga_info_reg8 = REGADDOFF__FPGA_INFO + 8,
- kfpga_info_reg9 = REGADDOFF__FPGA_INFO + 9,
- kfpga_info_rega = REGADDOFF__FPGA_INFO + 10,
- kfpga_info_regb = REGADDOFF__FPGA_INFO + 11,
- kfpga_info_regc = REGADDOFF__FPGA_INFO + 12,
- kfpga_info_regd = REGADDOFF__FPGA_INFO + 13,
- kfpga_info_rege = REGADDOFF__FPGA_INFO + 14,
- kfpga_info_regf = REGADDOFF__FPGA_INFO + 15,
-
- /*******************************************************************************
- * TTL输入模块 *
- *******************************************************************************/
-
- k_ttlin_module = REGADDOFF__TTLIN + 0,
- k_ttlin_en_reg = REGADDOFF__TTLIN + 1,
- k_ttlin1_freq_detector_reg = REGADDOFF__TTLIN + 2,
- k_ttlin2_freq_detector_reg = REGADDOFF__TTLIN + 3,
- k_ttlin3_freq_detector_reg = REGADDOFF__TTLIN + 4,
- k_ttlin4_freq_detector_reg = REGADDOFF__TTLIN + 5,
- k_ttlin1_filter_factor_reg = REGADDOFF__TTLIN + 6,
- k_ttlin2_filter_factor_reg = REGADDOFF__TTLIN + 7,
- k_ttlin3_filter_factor_reg = REGADDOFF__TTLIN + 8,
- k_ttlin4_filter_factor_reg = REGADDOFF__TTLIN + 9,
-
- /*******************************************************************************
- * TTL输出模块 *
- *******************************************************************************/
-
- kreg_ttlout1_module = REGADDOFF__TTLOUT1 + 0,
- kreg_ttlout1_signal_process_mode = REGADDOFF__TTLOUT1 + 1,
- kreg_ttlout1_input_signal_select = REGADDOFF__TTLOUT1 + 2,
- kreg_ttlout1_pllout_freq_division_ctrl = REGADDOFF__TTLOUT1 + 3,
- kreg_ttlout1_pllout_freq_multiplication_ctrl = REGADDOFF__TTLOUT1 + 4,
- kreg_ttlout1_pllout_polarity_ctrl = REGADDOFF__TTLOUT1 + 5,
- kreg_ttlout1_pllout_trigger_edge_select = REGADDOFF__TTLOUT1 + 6,
- kreg_ttlout1_forward_mode_polarity_ctrl = REGADDOFF__TTLOUT1 + 7,
- kreg_ttlout1_placeholder0 = REGADDOFF__TTLOUT1 + 8,
- kreg_ttlout1_freq_detect_bias = REGADDOFF__TTLOUT1 + 9,
- kreg_ttlout1_sig_in_freq_detect = REGADDOFF__TTLOUT1 + 0xE,
- kreg_ttlout1_sig_out_freq_detect = REGADDOFF__TTLOUT1 + 0xF,
-
- kreg_ttlout2_module = REGADDOFF__TTLOUT2 + 0,
- kreg_ttlout2_signal_process_mode = REGADDOFF__TTLOUT2 + 1,
- kreg_ttlout2_input_signal_select = REGADDOFF__TTLOUT2 + 2,
- kreg_ttlout2_pllout_freq_division_ctrl = REGADDOFF__TTLOUT2 + 3,
- kreg_ttlout2_pllout_freq_multiplication_ctrl = REGADDOFF__TTLOUT2 + 4,
- kreg_ttlout2_pllout_polarity_ctrl = REGADDOFF__TTLOUT2 + 5,
- kreg_ttlout2_pllout_trigger_edge_select = REGADDOFF__TTLOUT2 + 6,
- kreg_ttlout2_forward_mode_polarity_ctrl = REGADDOFF__TTLOUT2 + 7,
- kreg_ttlout2_placeholder0 = REGADDOFF__TTLOUT2 + 8,
- kreg_ttlout2_freq_detect_bias = REGADDOFF__TTLOUT2 + 9,
- kreg_ttlout2_sig_in_freq_detect = REGADDOFF__TTLOUT2 + 0xE,
- kreg_ttlout2_sig_out_freq_detect = REGADDOFF__TTLOUT2 + 0xF,
-
- kreg_ttlout3_module = REGADDOFF__TTLOUT3 + 0,
- kreg_ttlout3_signal_process_mode = REGADDOFF__TTLOUT3 + 1,
- kreg_ttlout3_input_signal_select = REGADDOFF__TTLOUT3 + 2,
- kreg_ttlout3_pllout_freq_division_ctrl = REGADDOFF__TTLOUT3 + 3,
- kreg_ttlout3_pllout_freq_multiplication_ctrl = REGADDOFF__TTLOUT3 + 4,
- kreg_ttlout3_pllout_polarity_ctrl = REGADDOFF__TTLOUT3 + 5,
- kreg_ttlout3_pllout_trigger_edge_select = REGADDOFF__TTLOUT3 + 6,
- kreg_ttlout3_forward_mode_polarity_ctrl = REGADDOFF__TTLOUT3 + 7,
- kreg_ttlout3_placeholder0 = REGADDOFF__TTLOUT3 + 8,
- kreg_ttlout3_freq_detect_bias = REGADDOFF__TTLOUT3 + 9,
- kreg_ttlout3_sig_in_freq_detect = REGADDOFF__TTLOUT3 + 0xE,
- kreg_ttlout3_sig_out_freq_detect = REGADDOFF__TTLOUT3 + 0xF,
-
- kreg_ttlout4_module = REGADDOFF__TTLOUT4 + 0,
- kreg_ttlout4_signal_process_mode = REGADDOFF__TTLOUT4 + 1,
- kreg_ttlout4_input_signal_select = REGADDOFF__TTLOUT4 + 2,
- kreg_ttlout4_pllout_freq_division_ctrl = REGADDOFF__TTLOUT4 + 3,
- kreg_ttlout4_pllout_freq_multiplication_ctrl = REGADDOFF__TTLOUT4 + 4,
- kreg_ttlout4_pllout_polarity_ctrl = REGADDOFF__TTLOUT4 + 5,
- kreg_ttlout4_pllout_trigger_edge_select = REGADDOFF__TTLOUT4 + 6,
- kreg_ttlout4_forward_mode_polarity_ctrl = REGADDOFF__TTLOUT4 + 7,
- kreg_ttlout4_placeholder0 = REGADDOFF__TTLOUT4 + 8,
- kreg_ttlout4_freq_detect_bias = REGADDOFF__TTLOUT4 + 9,
- kreg_ttlout4_sig_in_freq_detect = REGADDOFF__TTLOUT4 + 0xE,
- kreg_ttlout4_sig_out_freq_detect = REGADDOFF__TTLOUT4 + 0xF,
-
- /*******************************************************************************
- * TIMECODE输入模块 *
- *******************************************************************************/
-
- external_timecode_module = REGADDOFF__EXTERNAL_TIMECODE + 0,
- external_timecode_sig_selt = REGADDOFF__EXTERNAL_TIMECODE + 1,
- external_timecode_format = REGADDOFF__EXTERNAL_TIMECODE + 2,
- external_timecode_code0 = REGADDOFF__EXTERNAL_TIMECODE + 3,
- external_timecode_code1 = REGADDOFF__EXTERNAL_TIMECODE + 4,
-
- /*******************************************************************************
- * 内部TIMECODE模块 *
- *******************************************************************************/
-
- internal_timecode_module = REGADDOFF__INTERNAL_TIMECODE + 0,
- internal_timecode_en = REGADDOFF__INTERNAL_TIMECODE + 1,
- internal_timecode_format = REGADDOFF__INTERNAL_TIMECODE + 2,
- internal_timecode_data0 = REGADDOFF__INTERNAL_TIMECODE + 3,
- internal_timecode_data1 = REGADDOFF__INTERNAL_TIMECODE + 4,
-
- /*******************************************************************************
- * SYS_TIMECODE *
- *******************************************************************************/
-
- sys_timecode_module = REGADDOFF__SYS_TIMECODE,
- sys_timecode_select = REGADDOFF__SYS_TIMECODE + 1,
- sys_timecode_format = REGADDOFF__SYS_TIMECODE + 2,
- sys_timecode_data0 = REGADDOFF__SYS_TIMECODE + 3,
- sys_timecode_data1 = REGADDOFF__SYS_TIMECODE + 4,
-
- /*******************************************************************************
- * TIMECODE输出模块 *
- *******************************************************************************/
-
- timecode_output_module = REGADDOFF__TIMECODE_OUT + 0,
- timecode_output_timecode0 = REGADDOFF__TIMECODE_OUT + 1,
- timecode_output_timecode1 = REGADDOFF__TIMECODE_OUT + 2,
- timecode_output_timecode_format = REGADDOFF__TIMECODE_OUT + 3,
- timecode_output_bnc_outut_level_select = REGADDOFF__TIMECODE_OUT + 4,
- timecode_output_headphone_outut_level_select = REGADDOFF__TIMECODE_OUT + 5,
-
- /*******************************************************************************
- * 外部GENLOCK *
- *******************************************************************************/
-
- external_genlock_module = REGADDOFF__EXTERNAL_GENLOCK + 0,
- external_genlock_freq_detect_bias = REGADDOFF__EXTERNAL_GENLOCK + 1,
- external_genlock_freq = REGADDOFF__EXTERNAL_GENLOCK + 2,
-
- /*******************************************************************************
- * 内部GENLOCK *
- *******************************************************************************/
- internal_genlock_module = REGADDOFF__INTERNAL_GENLOCK + 0,
- internal_genlock_ctrl_mode = REGADDOFF__INTERNAL_GENLOCK + 1,
- internal_genlock_en = REGADDOFF__INTERNAL_GENLOCK + 2,
- internal_genlock_format = REGADDOFF__INTERNAL_GENLOCK + 3,
- internal_genlock_freq = REGADDOFF__INTERNAL_GENLOCK + 4,
-
- /*******************************************************************************
- * SYSGENLOCK *
- *******************************************************************************/
- sys_genlock_module = REGADDOFF__SYS_GENLOCK,
- sys_genlock_source = REGADDOFF__SYS_GENLOCK + 1,
- sys_genlock_freq_detect_bias = REGADDOFF__SYS_GENLOCK + 2,
- sys_genlock_freq = REGADDOFF__SYS_GENLOCK + 3,
-
- /*******************************************************************************
- * 内部CLOCK *
- *******************************************************************************/
-
- internal_clock_module = REGADDOFF__INTERNAL_CLOCK + 0,
- internal_clock_ctrl_mode = REGADDOFF__INTERNAL_CLOCK + 1,
- internal_clock_en = REGADDOFF__INTERNAL_CLOCK + 2,
- internal_clock_freq = REGADDOFF__INTERNAL_CLOCK + 3,
-
- /*******************************************************************************
- * SYSCLOCK *
- *******************************************************************************/
- sys_clock_module = REGADDOFF__SYS_CLOCK,
- sys_clock_source = REGADDOFF__SYS_CLOCK + 1,
- sys_clock_freq_division_ctrl = REGADDOFF__SYS_CLOCK + 2,
- sys_clock_freq_multiplication_ctrl = REGADDOFF__SYS_CLOCK + 3,
- sys_clock_freq_detect_bias = REGADDOFF__SYS_CLOCK + 4,
- sys_clock_trigger_edge_select = REGADDOFF__SYS_CLOCK + 5,
- sys_clock_infreq_detect = REGADDOFF__SYS_CLOCK + 0xE,
- sys_clock_outfreq_detect = REGADDOFF__SYS_CLOCK + 0xF,
-
- /*******************************************************************************
- * record_sig_gen *
- *******************************************************************************/
- record_sig_gen_module = REGADDOFF__RECORD_SIG_GENERATOR + 0,
- record_sig_gen_ctrl_control_mode = REGADDOFF__RECORD_SIG_GENERATOR + 1,
- record_sig_gen_timecode_start0 = REGADDOFF__RECORD_SIG_GENERATOR + 2,
- record_sig_gen_timecode_start1 = REGADDOFF__RECORD_SIG_GENERATOR + 3,
- record_sig_gen_timecode_stop0 = REGADDOFF__RECORD_SIG_GENERATOR + 4,
- record_sig_gen_timecode_stop1 = REGADDOFF__RECORD_SIG_GENERATOR + 5,
- record_sig_gen_timecode_control_flag = REGADDOFF__RECORD_SIG_GENERATOR + 6,
-
- record_sig_gen_ttlin_trigger_sig_source = REGADDOFF__RECORD_SIG_GENERATOR + 7,
- record_sig_gen_ttlin_trigger_level = REGADDOFF__RECORD_SIG_GENERATOR + 8,
- record_sig_gen_exposure_time = REGADDOFF__RECORD_SIG_GENERATOR + 9,
- record_sig_gen_exposure_offset_time = REGADDOFF__RECORD_SIG_GENERATOR + 10,
- record_sig_gen_manual_ctrl = REGADDOFF__RECORD_SIG_GENERATOR + 11,
-
- record_sig_gen_timecode_snapshot0 = REGADDOFF__RECORD_SIG_GENERATOR + 13,
- record_sig_gen_timecode_snapshot1 = REGADDOFF__RECORD_SIG_GENERATOR + 14,
- record_sig_gen_record_state = REGADDOFF__RECORD_SIG_GENERATOR + 15,
-
- /*******************************************************************************
- * camera_sync_module *
- *******************************************************************************/
- camera_sync_module = REGADDOFF__CAMERA_SYNC_OUT + 0,
- camera_sync_pulse_mode_valid_len = REGADDOFF__CAMERA_SYNC_OUT + 1,
-
-} RegAdd_t;
diff --git a/usrc/main.cpp b/usrc/main.cpp
index e8766e6..5659bcb 100644
--- a/usrc/main.cpp
+++ b/usrc/main.cpp
@@ -4,11 +4,11 @@
//
#include "base_service/base_service.h"
#include "base_service/fpga_if.h"
+#include "base_service/light_ctrl_service.h"
#include "service/device_info.hpp"
#include "service/extern_if_service.h"
#include "service/network_service.h"
#include "service/reg_manager.h"
-#include "service/report_generator_service.h"
//
#define TAG "main"
using namespace std;
@@ -26,20 +26,17 @@ void StartDefaultTask(void const* argument) { umain(); }
* @brief
* | extern_if_service |
* ========================================
- * | reg_manager |
- * config_service ========================================
- * | report_generator | device_info |
- * =================== ==============
- * | fpage_if |
+ * | reg_manager | device_info |
* ========================================
+ * | fpage_if |
+ * =========================
*
*/
zaf_gpio_t m_debug_led;
zaf_gpio_t m_factory_reset_key;
-zaf_gpio_t m_power_led;
extern "C" {
-void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) { ReportGeneratorService_irq_trigger(GPIO_Pin); }
+void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) {}
}
void debug_light_ctrl() {
@@ -47,8 +44,8 @@ void debug_light_ctrl() {
static bool light_status = false;
if (zaf_has_passedms(lastcall) > 100) {
light_status = !light_status;
- zaf_gpio_write(&m_debug_led, light_status);
- lastcall =zaf_get_ticket();
+ zaf_gpio_write(&m_debug_led, light_status);
+ lastcall = zaf_get_ticket();
}
}
@@ -57,7 +54,7 @@ void factory_reset_key_detect() {
static bool reset_key_triggered = false;
if (!reset_key_triggered) {
if (zaf_gpio_read(&m_factory_reset_key)) {
- reset_key_trigger_tp =zaf_get_ticket();
+ reset_key_trigger_tp = zaf_get_ticket();
reset_key_triggered = true;
}
}
@@ -72,9 +69,9 @@ void factory_reset_key_detect() {
// m_power_led
while (zaf_gpio_read(&m_factory_reset_key)) {
- zaf_gpio_write(&m_power_led, false);
+ LightCtrlService_GreenLight_setState(false);
osDelay(100);
- zaf_gpio_write(&m_power_led, true);
+ LightCtrlService_GreenLight_setState(true);
osDelay(100);
}
ZLOGI(TAG, "system reset");
@@ -92,8 +89,8 @@ void umain() {
sn_t sn;
device_info_init();
device_info_get_sn(&sn);
- ZLOGI(TAG, "%s:%d", PC_PROJECT_NAME, PC_VERSION);
- ZLOGI(TAG, "sn: %x:%x:%x", sn.sn0, sn.sn1, sn.sn2);
+ ZLOGI(TAG, "%s:%d", PC_PROJECT_NAME, PC_VERSION);
+ ZLOGI(TAG, "sn: %x:%x:%x", sn.sn0, sn.sn1, sn.sn2);
/**
* @brief
@@ -101,9 +98,12 @@ void umain() {
* 2. 初始化电源指示灯
* 3. 初始化工厂复位按键
*/
- zaf_gpio_init_as_output(&m_debug_led, PC_DEBUG_LIGHT_GPIO, kxs_gpio_nopull, false, false);
- zaf_gpio_init_as_output(&m_power_led, POWER_LED_PIN, kxs_gpio_nopull, false, true);
- zaf_gpio_init_as_input(&m_factory_reset_key, FACTORY_RESET_KEY, kxs_gpio_nopull, kxs_gpio_no_irq, true);
+ zaf_gpio_init_as_output(&m_debug_led, PC_DEBUG_LIGHT_GPIO, kxs_gpio_nopull, false, false);
+
+ if (FACTORY_RESET_KEY != PinNull) {
+ zaf_gpio_init_as_input(&m_factory_reset_key, FACTORY_RESET_KEY, kxs_gpio_nopull, kxs_gpio_no_irq, true);
+ }
+
// m_power_led
/**
* @brief 配置初始化
@@ -118,11 +118,6 @@ void umain() {
*/
fpga_if_init();
/**
- * @brief report_generator init
- */
- // ReportGeneratorService_init(fpga_if_get_instance()->timecode_irq_pin, fpga_if_get_instance()->camera_sync_code_irq_pin);
-
- /**
* @brief reg_manager init
*/
reg_manager_init();
@@ -134,39 +129,15 @@ void umain() {
osDelay(1000);
extern_if_service_init();
- ZLOGI(TAG, "system init done");
+ ZLOGI(TAG, "system init done");
int32_t count = 0;
while (true) {
- // HAL_SPI_Transmit(&hspi1, (uint8_t*)"hello", 5, 1000);
- // HAL_SPI_Transmit(&hspi2, (uint8_t*)"hello", 5, 1000);
osDelay(10);
debug_light_ctrl();
- factory_reset_key_detect();
-
- if (zaf_has_passedms(0) >= 1* 60 * 60 * 1000) {
- //限制客户使用时长
- // reset_pin_io
- NVIC_SystemReset();
+ if (FACTORY_RESET_KEY != PinNull) {
+ factory_reset_key_detect();
}
-
- // ZLOGI(TAG,"factory_reset_key_state %d",zaf_gpio_read(&m_factory_reset_key));
-
- // osDelay(10);
- // fpga_if_spi_write_data_01(33, count, &rxdata);
- // osDelay(10);
- // fpga_if_spi_write_data_01(34, count, &rxdata);
- // osDelay(10);
- // fpga_if_spi_write_data_01(35, count, &rxdata);
- // osDelay(10);
- // fpga_if_spi_write_data_01(36, count, &rxdata);
- // osDelay(10);
- // if(count!=rxdata){
- // ZLOGI(TAG, "fpga_if_spi_write_data_01 error count: %d, rxdata: %d", count, rxdata);
- // }
- // count++;
- // ZLOGI(TAG, "fpga_if_init: %d",zaf_gpio_read(&fpga_if_get_instance()->xsync_workstate_start_sig_irq_io));
- // ZLOGI(TAG, "rxdata: %x", rxdata);
}
}
diff --git a/usrc/project_configs.h b/usrc/project_configs.h
index eb4115f..75bf41b 100644
--- a/usrc/project_configs.h
+++ b/usrc/project_configs.h
@@ -1,10 +1,15 @@
#pragma once
+/*******************************************************************************
+ * 项目基础配置 *
+ *******************************************************************************/
+
#define PC_VERSION 1
#define PC_MANUFACTURER0 ('i' | 'f' << 8 | 'l' << 16 | 'y' << 24)
#define PC_MANUFACTURER1 ('t' | 'o' << 8 | 'p' << 16 | '\0' << 24)
#define PC_PROJECT_NAME "zaf_lstc"
#define PC_IFLYTOP_ENABLE_OS 1
+#define PC_DEVICE_TYPE ('c' | 'l' << 8 | 's' << 16 | 't' << 24)
#define PC_DEBUG_UART huart1
#define PC_DEBUG_UART_DMA_HANDLER hdma_usart1_rx
@@ -19,9 +24,57 @@
#define PC_NVS_ENABLE 1
-// =====================================================================
-// =====================================================================
-// =====================================================================
+/*******************************************************************************
+ * 公板通用接口 *
+ *******************************************************************************/
+
+#define FACTORY_RESET_KEY PinNull
+
+/**
+ * @brief 状态指示灯
+ */
+#define LED_R_PIN PD9
+#define LED_G_PIN PD10
+#define LED_B_PIN PD11
+
+#define SPI_CS PA4
+
+#define FPGA_UART huart6
+#define FPGA_UART_DMA_HANDLER hdma_usart6_rx
+
+/**
+ * @brief FPGA并口
+ */
+#define FPGA_RESERVE_IOA0 PE0
+#define FPGA_RESERVE_IOA1 PE1
+#define FPGA_RESERVE_IOA2 PE2
+#define FPGA_RESERVE_IOA3 PE3
+#define FPGA_RESERVE_IOA4 PE4
+#define FPGA_RESERVE_IOA5 PE5
+#define FPGA_RESERVE_IOA6 PE6
+#define FPGA_RESERVE_IOA7 PE7
+#define FPGA_RESERVE_IOB0 PE8
+#define FPGA_RESERVE_IOB1 PE9
+#define FPGA_RESERVE_IOB2 PE10
+#define FPGA_RESERVE_IOB3 PE11
+#define FPGA_RESERVE_IOB4 PE12
+#define FPGA_RESERVE_IOB5 PE13
+#define FPGA_RESERVE_IOB6 PE14
+#define FPGA_RESERVE_IOB7 PE15
+
+/**
+ * @brief 命令串口
+ */
+#define COMMAND_UART huart3
+#define COMMAND_UART_DMA_HANDLER hdma_usart3_rx
+#define COMMAND_UART_RX_BUF_SIZE 1024
+
+/*******************************************************************************
+ * 项目相关接口 *
+ *******************************************************************************/
-#define FACTORY_RESET_KEY PB1
-#define POWER_LED_PIN PB2
\ No newline at end of file
+#define TEMPERATURE_SENSOR_PIN PD4 // 单总线温度传感器
+#define FAN0_POWER_PIN PD0 // 风扇0
+#define FAN0_FB_PIN PD5 // 风扇0-FB
+#define FAN1_POWER_PIN PD1 // 风扇1
+#define FAN1_FB_PIN PD6 // 风扇1-FB
diff --git a/usrc/service/extern_if_service.c b/usrc/service/extern_if_service.c
index be8a5ee..23e3e7c 100644
--- a/usrc/service/extern_if_service.c
+++ b/usrc/service/extern_if_service.c
@@ -2,8 +2,15 @@
#include "project_dep.h"
//
#include "reg_manager.h"
+#include "base_service/config_service.h"
+
#define TAG "extern_if_service"
+typedef struct {
+ zaf_packet_header_t *rxpacket;
+ zaf_buf_t receipt;
+} extern_if_service_context_t;
+
static udp_t m_udp_cmd_server; //
// static udp_broadcast_handler_t m_udp_camera_sync_sender; //
@@ -12,54 +19,99 @@ static bool m_last_rxpacket_client_valid = false;
static uint8_t txbuf[2048];
/*******************************************************************************
- * 上位机下发指令回执服务 *
+ * 包构造 *
*******************************************************************************/
-typedef struct {
- udp_t *server;
- struct sockaddr_in *client;
- iflytop_xsync_packet_header_t *rxpacket;
-} extern_if_service_context_t;
-/**
- * @brief 创建并发送回执数据包
- *
- * @param context
- * @param data
- * @param ndata
- */
-static void create_and_send_receipt(extern_if_service_context_t *context, uint32_t *data, size_t ndata) {
- iflytop_xsync_packet_header_t *txpacket = (iflytop_xsync_packet_header_t *)txbuf;
-
- txpacket->type = kxsync_packet_type_receipt;
- txpacket->index = context->rxpacket->index;
- txpacket->cmd = context->rxpacket->cmd;
- txpacket->ndata = ndata;
- memcpy(txpacket->data, data, ndata * sizeof(uint32_t));
- zaf_udp_send_message2(context->server, context->client, (const char *)txbuf, sizeof(iflytop_xsync_packet_header_t) + ndata * sizeof(uint32_t));
+static void create_receipt(extern_if_service_context_t *context, uint32_t ecode, uint32_t *data, size_t ndata) {
+ zaf_packet_header_t *txpacket = (zaf_packet_header_t *)txbuf;
+ uint32_t txpacklen = sizeof(zaf_packet_header_t) + (ndata + 1) * sizeof(uint32_t) + 1 /*checksum*/ + 2 /*tail*/;
+
+ txpacket->packet_header = PACKET_HEADER;
+ txpacket->packet_type = kzaf_packet_type_receipt;
+ txpacket->index = context->rxpacket->index;
+ txpacket->cmd = context->rxpacket->cmd;
+ txpacket->ndata = ndata + 1;
+ txpacket->data[0] = ecode;
+ memcpy(&txpacket->data[1], data, ndata * sizeof(uint32_t));
+
+ uint8_t checksum = 0;
+ for (int i = 2; i < txpacklen - 3; i++) {
+ checksum += txbuf[i];
+ }
+ txbuf[txpacklen - 3] = checksum;
+ txbuf[txpacklen - 2] = PACKET_TAIL & 0xFF;
+ txbuf[txpacklen - 1] = (PACKET_TAIL >> 8) & 0xFF;
+
+ zaf_buf_t buf;
+ buf.data = txbuf;
+ buf.len = txpacklen;
+
+ context->receipt = buf;
}
-#if 0
-/**
- * @brief 构建并发送时间码数据包
- *
- * @param client
- * @param timecode0
- * @param timecode1
- */
-static void create_and_send_timecode(struct sockaddr_in client, uint32_t timecode0, uint32_t timecode1) {
- iflytop_xsync_packet_header_t *txpacket = (iflytop_xsync_packet_header_t *)txbuf;
-
- txpacket->type = kxsync_packet_type_report;
- txpacket->index = 0;
- txpacket->cmd = kxsync_packet_type_timecode_report;
- txpacket->ndata = 2;
- txpacket->data[0] = timecode0;
- txpacket->data[1] = timecode1;
- zaf_udp_send_message2(&m_udp_cmd_server, &client, txbuf, sizeof(iflytop_xsync_packet_header_t) + 2 * sizeof(uint32_t));
+
+/*******************************************************************************
+ * 接收消息处理 *
+ *******************************************************************************/
+
+static bool process_rx_packet(extern_if_service_context_t *cx, uint8_t *data, uint16_t len) {
+ // ZLOGI(TAG, "udp_on_packet %d:", len);
+ // for (int i = 0; i < len; i++) {
+ // printf("%02x ", data[i]);
+ // }
+ // printf("\n");
+ zaf_packet_header_t *rxpacket = (zaf_packet_header_t *)data;
+ cx->rxpacket = rxpacket;
+
+ if (rxpacket->packet_type != kzaf_packet_type_cmd) return;
+
+ /*******************************************************************************
+ * 寄存器读 *
+ *******************************************************************************/
+ if (rxpacket->cmd == kzaf_cmd_reg_read) {
+ uint32_t readbak_regval = reg_manager_read_reg(rxpacket->data[0]); // regdata
+ create_receipt(cx, 0, &readbak_regval, 1);
+ }
+ /*******************************************************************************
+ * 寄存器写 *
+ *******************************************************************************/
+ else if (rxpacket->cmd == kzaf_cmd_reg_write) {
+ uint32_t readbak_regval = reg_manager_write_reg(rxpacket->data[0], rxpacket->data[1]);
+ create_receipt(cx, 0, &readbak_regval, 1);
+ }
+ /*******************************************************************************
+ * 多寄存器读 *
+ *******************************************************************************/
+ else if (rxpacket->cmd == kzaf_cmd_reg_read_regs) {
+ static uint32_t regcache[MAX_REG_NUM + 1];
+ uint32_t len = MAX_REG_NUM;
+
+ reg_manager_read_regs(rxpacket->data[0], rxpacket->data[1], ®cache[0], &len);
+ create_receipt(cx, 0, regcache, len);
+ }
+ /*******************************************************************************
+ * 产生新的MAC *
+ *******************************************************************************/
+ else if (rxpacket->cmd == kzaf_cmd_generator_new_mac) {
+ config_generate_random_mac();
+ config_flush();
+ create_receipt(cx, 0, NULL, 0);
+ } else if (rxpacket->cmd == kzaf_cmd_factory_reset) {
+ config_factory_reset();
+ NVIC_SystemReset();
+ } else if (rxpacket->cmd == kzaf_cmd_reboot) {
+ NVIC_SystemReset();
+ } else if (rxpacket->cmd == kzaf_cmd_storage_cfg) {
+ config_flush();
+ create_receipt(cx, 0, NULL, 0);
+ }
}
-#endif
+
+/*******************************************************************************
+ * 框架 *
+ *******************************************************************************/
/**
- * @brief 接收并解析从上位机下发下来的数据包
+ * @brief UDP消息接收消息处理
*
* @param server
* @param client
@@ -67,56 +119,16 @@ static void create_and_send_timecode(struct sockaddr_in client, uint32_t timecod
* @param len
*/
static void udp_on_packet(udp_t *server, struct sockaddr_in *client, uint8_t *data, uint16_t len) {
- // ZLOGI(TAG, "udp_on_packet %d:", len);
- // for (int i = 0; i < len; i++) {
- // printf("%02x ", data[i]);
- // }
- // printf("\n");
-
- /**
- * @brief
- */
- iflytop_xsync_packet_header_t *rxpacket = (iflytop_xsync_packet_header_t *)data;
- extern_if_service_context_t cx = {0};
- cx.client = client;
- cx.server = server;
- cx.rxpacket = rxpacket;
-
- if (rxpacket->type != kxsync_packet_type_cmd) return;
-
- m_last_rxpacket_client_valid = true;
- memcpy(&m_last_rxpacket_client, client, sizeof(struct sockaddr_in));
-
- if (rxpacket->cmd == kxsync_packet_type_reg_read) {
- uint32_t regadd = rxpacket->data[0];
- uint32_t receipt[2];
-
- receipt[0] = 0; // receipt
- receipt[1] = reg_manager_read_reg(regadd); // regdata
- // ZLOGI(TAG, "regadd: %d, regdata: 0x%08x", regadd, receipt[1]);
- create_and_send_receipt(&cx, receipt, 2);
- } else if (rxpacket->cmd == kxsync_packet_type_reg_write) {
- uint32_t regadd = rxpacket->data[0];
- uint32_t regval = rxpacket->data[1];
- uint32_t receipt[2];
-
- receipt[0] = 0; //
- receipt[1] = reg_manager_write_reg(regadd, regval);
- create_and_send_receipt(&cx, receipt, 2);
-
- } else if (rxpacket->cmd == kxsync_packet_type_reg_read_regs) {
- uint32_t start_regadd = rxpacket->data[0];
- uint32_t nreg = rxpacket->data[1];
+ extern_if_service_context_t cx;
+ bool ret = process_rx_packet(&cx, data, len);
+ if (ret) {
+ zaf_udp_send_message2(server, client, (const char *)cx.receipt.data, cx.receipt.len);
- static uint32_t regcache[MAX_REG_NUM + 1];
- uint32_t len = MAX_REG_NUM;
- regcache[0] = 0;
- reg_manager_read_regs(start_regadd, nreg, ®cache[1], &len);
- create_and_send_receipt(&cx, regcache, len);
+ m_last_rxpacket_client_valid = true;
+ memcpy(&m_last_rxpacket_client, client, sizeof(struct sockaddr_in));
}
}
-void extern_if_service_init() { ZASSERT(zaf_udp_init(&m_udp_cmd_server, "extern_if_udp", IFLYTOP_XSYNC_SERVICE_XSYNC_PORT, udp_on_packet, 1024, NULL)); }
-#if 0
-void extern_if_service_send_timecode(struct sockaddr_in client, uint32_t timecode0, uint32_t timecode1) { create_and_send_timecode(client, timecode0, timecode1); }
-#endif
+void extern_if_service_init() { //
+ ZASSERT(zaf_udp_init(&m_udp_cmd_server, "extern_if_udp", ZAF_SERVICE_DEVICE_PORT, udp_on_packet, 1024, NULL));
+}
diff --git a/usrc/service/extern_if_service.h b/usrc/service/extern_if_service.h
index edee1ed..4f789f3 100644
--- a/usrc/service/extern_if_service.h
+++ b/usrc/service/extern_if_service.h
@@ -15,16 +15,6 @@ extern "C" {
*
*/
void extern_if_service_init();
-#if 0
-/**
- * @brief 上报时间码
- *
- * @param client
- * @param timecode0
- * @param timecode1
- */
-void extern_if_service_send_timecode(struct sockaddr_in client, uint32_t timecode0, uint32_t timecode1);
-#endif
#ifdef __cplusplus
}
diff --git a/usrc/service/reg_manager.c b/usrc/service/reg_manager.c
index 077eae3..6a961c7 100644
--- a/usrc/service/reg_manager.c
+++ b/usrc/service/reg_manager.c
@@ -3,91 +3,67 @@
#include "base_service/config_service.h"
#include "base_service/fpga_if.h"
#include "device_info.hpp"
-#include "service/report_generator_service.h"
+#include "zaf_protocol/zaf_regs.hpp"
uint32_t m_action_val0;
uint32_t m_action_receipt;
void reg_manager_init() {}
-
-/*******************************************************************************
- * ACTION *
- *******************************************************************************/
-static uint32_t doaction(uint32_t action, uint32_t val) {
- if (action == xsync_stm32_action_generator_new_mac) {
- config_generate_random_mac();
- config_flush();
- return 0;
- } else if (action == xsync_stm32_action_factory_reset) {
- config_factory_reset();
- return 0;
- } else if (action == xsync_stm32_action_reboot) {
- NVIC_SystemReset();
- return 0;
- } else if (action == xsync_stm32_action_storage_cfg) {
- config_flush();
- return 0;
- }
- return 0;
-}
-
uint32_t reg_manager_read_reg(uint32_t addr) {
uint32_t readbak = 0;
static sn_t sncode;
- if (addr == kxsync_reg_software_version) { // read only
+ if (addr == kreg_software_version) { // read only
readbak = PC_VERSION;
- } else if (addr == kxsync_reg_manufacturer0) { // read only
+ } else if (addr == kreg_manufacturer0) { // read only
readbak = PC_MANUFACTURER0;
- } else if (addr == kxsync_reg_manufacturer1) { // read only
+ } else if (addr == kreg_manufacturer1) { // read only
readbak = PC_MANUFACTURER1;
- } else if (addr == kxsync_reg_product_type_id) { // read only
- readbak = kxsync_device_type_xsync;
- } else if (addr == kxsync_reg_sn_id0) { // read only
+ } else if (addr == kreg_product_type_id) { // read only
+ readbak = PC_DEVICE_TYPE;
+ } else if (addr == kreg_sn_id0) { // read only
device_info_get_sn(&sncode);
readbak = sncode.sn0;
- } else if (addr == kxsync_reg_sn_id1) { // read only
+ } else if (addr == kreg_sn_id1) { // read only
device_info_get_sn(&sncode);
readbak = sncode.sn1;
- } else if (addr == kxsync_reg_sn_id2) { // read only
+ } else if (addr == kreg_sn_id2) { // read only
device_info_get_sn(&sncode);
readbak = sncode.sn2;
- } else if (addr == kxsync_reg_mac0) { // read only
+ } else if (addr == kreg_mac0) { // read only
memcpy(&readbak, config_get()->mac, 4);
- } else if (addr == kxsync_reg_mac1) { // read only
+ } else if (addr == kreg_mac1) { // read only
memcpy(&readbak, config_get()->mac + 4, 4);
}
/*******************************************************************************
* CONFIG *
*******************************************************************************/
- else if (addr == kxsync_reg_stm32_obtaining_ip_mode) {
+ else if (addr == kreg_stm32_obtaining_ip_mode) {
readbak = config_get()->obtaining_ip_mode;
- } else if (addr == kxsync_reg_stm32_ip) {
+ } else if (addr == kreg_stm32_ip) {
readbak = config_get()->ip;
- } else if (addr == kxsync_reg_stm32_gw) {
+ } else if (addr == kreg_stm32_gw) {
readbak = config_get()->gw;
- } else if (addr == kxsync_reg_stm32_netmask) {
+ } else if (addr == kreg_stm32_netmask) {
readbak = config_get()->netmask;
- } else if (addr == kxsync_reg_stm32_config0) {
+ } else if (addr == kreg_stm32_config0) {
readbak = config_get()->config0;
- } else if (addr == kxsync_reg_stm32_camera_sync_signal_count) {
- readbak = ReportGeneratorService_xsync_get_count();
- }
+ }
/*******************************************************************************
* ACTION *
*******************************************************************************/
- else if (addr == kxsync_reg_stm32_action0) {
+ else if (addr == kreg_stm32_action0) {
readbak = m_action_receipt;
- } else if (addr == kxsync_reg_stm32_action_val0) {
+ } else if (addr == kreg_stm32_action_val0) {
readbak = m_action_val0;
}
/*******************************************************************************
* FPGA芯片寄存器读写 *
*******************************************************************************/
- else if (addr >= XYSNC_REG_FPGA_REG_START) {
- fpga_if_spi_read_data_02(addr, &readbak);
+ else if (addr >= REGADD__FPGA_START) {
+ fpga_if_spi_read_data(addr, &readbak);
}
return readbak;
}
@@ -97,54 +73,40 @@ uint32_t reg_manager_write_reg(uint32_t addr, uint32_t value) {
/*******************************************************************************
* INFO *
*******************************************************************************/
- if (addr == kxsync_reg_software_version) { // read only
+ if (addr == kreg_software_version) { // read only
readbak = reg_manager_read_reg(addr);
- } else if (addr == kxsync_reg_manufacturer0) { // read only
+ } else if (addr == kreg_manufacturer0) { // read only
readbak = reg_manager_read_reg(addr);
- } else if (addr == kxsync_reg_manufacturer1) { // read only
+ } else if (addr == kreg_manufacturer1) { // read only
readbak = reg_manager_read_reg(addr);
- } else if (addr == kxsync_reg_product_type_id) { // read only
+ } else if (addr == kreg_product_type_id) { // read only
readbak = reg_manager_read_reg(addr);
}
/*******************************************************************************
* CONFIG *
*******************************************************************************/
- else if (addr == kxsync_reg_stm32_obtaining_ip_mode) {
+ else if (addr == kreg_stm32_obtaining_ip_mode) {
config_get()->obtaining_ip_mode = value;
readbak = config_get()->obtaining_ip_mode;
- } else if (addr == kxsync_reg_stm32_ip) {
+ } else if (addr == kreg_stm32_ip) {
config_get()->ip = value;
readbak = config_get()->ip;
- } else if (addr == kxsync_reg_stm32_gw) {
+ } else if (addr == kreg_stm32_gw) {
config_get()->gw = value;
readbak = config_get()->gw;
- } else if (addr == kxsync_reg_stm32_netmask) {
+ } else if (addr == kreg_stm32_netmask) {
config_get()->netmask = value;
readbak = config_get()->netmask;
- } else if (addr == kxsync_reg_stm32_config0) {
+ } else if (addr == kreg_stm32_config0) {
readbak = config_get()->config0;
- } else if (addr == kxsync_reg_stm32_camera_sync_signal_count) {
- ReportGeneratorService_xsync_set_count(value);
- readbak = ReportGeneratorService_xsync_get_count();
- }
- /*******************************************************************************
- * ACTION *
- *******************************************************************************/
- else if (addr == kxsync_reg_stm32_action0) {
- readbak = doaction(value, m_action_val0);
- m_action_receipt = readbak;
- } else if (addr == kxsync_reg_stm32_action_val0) {
- m_action_val0 = value;
- readbak = value;
}
/*******************************************************************************
* FPGA芯片寄存器读写 *
*******************************************************************************/
- else if (addr >= XYSNC_REG_FPGA_REG_START) {
- fpga_if_spi_write_data_02(addr, value, &readbak);
+ else if (addr >= REGADD__FPGA_START) {
+ fpga_if_spi_write_data(addr, value, &readbak);
}
-
return readbak;
}
diff --git a/usrc/service/report_generator_service.c b/usrc/service/report_generator_service.c
deleted file mode 100644
index 7953004..0000000
--- a/usrc/service/report_generator_service.c
+++ /dev/null
@@ -1,154 +0,0 @@
-#include "report_generator_service.h"
-
-#include "base_service/fpga_if.h"
-#include "base_service/task_level_config.h"
-#include "base_service/xsync_regs.hpp"
-#include "reg_manager.h"
-
-static udp_broadcast_handler_t m_udp_camera_sync_sender; //
-static udp_broadcast_handler_t m_udp_camera_timecode_sender; //
-
-osThreadId timecode_report_thread_id;
-osThreadId xync_signal_report_thread_id;
-
-static uint32_t m_sync_count = 0;
-// static uint32_t m_camera_sync_packet_report_period = 1;
-
-static uint32_t m_xsync_workstate_start_sig_irq_pin_off;
-static uint32_t m_timecode_trigger_input_off;
-static uint32_t m_xync_trigger_input_off;
-static uint32_t m_xyns_camera_sync_packet_last_report_tp;
-#define TAG "timecode"
-/**
- * @brief 构建并发送时间码数据包
- *
- * @param client
- * @param timecode0
- * @param timecode1
- */
-
-static void create_and_send_timecode(uint32_t timecode0, uint32_t timecode1) {
- static uint8_t txbuf[256];
- iflytop_xsync_event_report_packet_t *txpacket = (iflytop_xsync_event_report_packet_t *)txbuf;
- txpacket->eventid = ktimecode_report_event;
- txpacket->data[0] = timecode0;
- txpacket->data[1] = timecode1;
- zaf_udp_broadcast(&m_udp_camera_timecode_sender, IFLYTOP_XSYNC_EVENT_REPORT_PC_PORT, txbuf, sizeof(iflytop_xsync_event_report_packet_t) + 8);
-}
-static void create_and_send_sync_record_state_packet(uint32_t workstate, uint32_t timecode0, uint32_t timecode1) {
- static uint8_t txbuf[256];
- uint32_t packetdatalen = 3;
- iflytop_xsync_event_report_packet_t *txpacket = (iflytop_xsync_event_report_packet_t *)txbuf;
- txpacket->eventid = kxsync_work_state_report_event;
- txpacket->data[0] = workstate;
- txpacket->data[1] = timecode0;
- txpacket->data[2] = timecode1;
-
- zaf_udp_broadcast(&m_udp_camera_timecode_sender, IFLYTOP_XSYNC_EVENT_REPORT_PC_PORT, txbuf, sizeof(iflytop_xsync_event_report_packet_t) + 4 * packetdatalen);
-}
-/**
- * @brief 构建并发送相机同步数据包
- *
- * @param count
- */
-static void create_and_send_camera_sync_msg(uint32_t count) {
- static uint8_t txbuf[] = {
- 0xF0, 0x00, 0x20, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0xF0, 0x42, 0x17, 0x00, 0x00, 0x00, 0xE1, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x78, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE6, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- };
-
- txbuf[7] = count & 0xFF;
- txbuf[6] = (count >> 8) & 0xFF;
- txbuf[5] = (count >> 16) & 0xFF;
- txbuf[4] = (count >> 24) & 0xFF;
-
- zaf_udp_broadcast(&m_udp_camera_sync_sender, IFLYTOP_XSYNC_CAMERA_SYNC_PACKET_PC_PORT, txbuf, sizeof(txbuf));
-}
-
-static void timecode_report_thread(void const *argument) {
- while (true) {
- osEvent signal = osSignalWait(0x07, osWaitForever);
- if (signal.value.signals & 0x01) {
- uint32_t timecode0, timecode1;
- fpga_if_get_timecode(&timecode0, &timecode1);
- create_and_send_timecode(timecode0, timecode1);
- }
- if (signal.value.signals & 0x02) {
- // 开始录制
- uint32_t timecode0 = 0;
- uint32_t timecode1 = 0;
- fpga_if_spi_read_data_02(record_sig_gen_timecode_snapshot0, &timecode0);
- fpga_if_spi_read_data_02(record_sig_gen_timecode_snapshot1, &timecode1);
- create_and_send_sync_record_state_packet(1, timecode0, timecode1);
- }
- if (signal.value.signals & 0x04) {
- // 结束录制
- uint32_t timecode0 = 0;
- uint32_t timecode1 = 0;
- fpga_if_spi_read_data_02(record_sig_gen_timecode_snapshot0, &timecode0);
- fpga_if_spi_read_data_02(record_sig_gen_timecode_snapshot1, &timecode1);
- create_and_send_sync_record_state_packet(0, timecode0, timecode1);
- m_sync_count = 0;
- }
- }
-}
-static void xync_signal_report_thread(void const *argument) {
- while (true) {
- osEvent signal = osSignalWait(0x01, osWaitForever);
- if (signal.value.signals == 0x01) {
- if (m_sync_count == 0) {
- m_xyns_camera_sync_packet_last_report_tp = HAL_GetTick();
- create_and_send_camera_sync_msg(m_sync_count);
- m_sync_count++;
- } else if (zaf_has_passedms(m_xyns_camera_sync_packet_last_report_tp) >= 998) {
- // TODO:此处这么写，当拍摄频率大于500HZ的时候，就不能完全满足刚好卡在1s上报一次消息
- m_xyns_camera_sync_packet_last_report_tp = HAL_GetTick();
- create_and_send_camera_sync_msg(m_sync_count);
- m_sync_count++;
- } else {
- m_sync_count++;
- }
- }
- // osSignalClear(xync_signal_report_thread_id, 0x01);
- }
-}
-
-void ReportGeneratorService_irq_trigger(uint16_t gpiopin) {
- if (gpiopin == m_timecode_trigger_input_off) {
- // timecode trigger sig
- osSignalSet(timecode_report_thread_id, 0x01);
- }
- if (m_xsync_workstate_start_sig_irq_pin_off == gpiopin) {
- if (zaf_gpio_read(&fpga_if_get_instance()->xsync_workstate_start_sig_irq_io)) {
- osSignalSet(timecode_report_thread_id, 0x02); // 开始工作信号
- } else {
- osSignalSet(timecode_report_thread_id, 0x04); // 结束工作信号
- }
- }
- if (gpiopin == m_xync_trigger_input_off) {
- // 相机同步信号
- osSignalSet(xync_signal_report_thread_id, 0x01);
- }
-}
-
-void ReportGeneratorService_init() {
- ZASSERT(xs_udp_broadcast_init(&m_udp_camera_sync_sender, IFLYTOP_XSYNC_CAMERA_SYNC_PACKET_XSYNC_PORT));
- ZASSERT(xs_udp_broadcast_init(&m_udp_camera_timecode_sender, IFLYTOP_XSYNC_EVENT_REPORT_XSYNC_PORT));
-
- //
- osThreadDef(timecode_report_thread, timecode_report_thread, TIMECODE_REPORT_TASK_LEVEL, 0, 512);
- timecode_report_thread_id = osThreadCreate(osThread(timecode_report_thread), NULL);
-
- osThreadDef(xync_signal_report_thread, xync_signal_report_thread, CAMERA_SYNC_SIG_REPORT_TASK_LEVEL, 0, 512);
- xync_signal_report_thread_id = osThreadCreate(osThread(xync_signal_report_thread), NULL);
-
- ZASSERT(timecode_report_thread_id != NULL);
- ZASSERT(xync_signal_report_thread_id != NULL);
-
- m_timecode_trigger_input_off = fpga_if_get_instance()->timecode_irq_io.pinoff;
- m_xync_trigger_input_off = fpga_if_get_instance()->camera_sync_code_irq_io.pinoff;
- m_xsync_workstate_start_sig_irq_pin_off = fpga_if_get_instance()->xsync_workstate_start_sig_irq_io.pinoff;
-}
-
-void ReportGeneratorService_xsync_set_count(uint32_t count) { m_sync_count = count; }
-uint32_t ReportGeneratorService_xsync_get_count(void) { return m_sync_count; }
diff --git a/usrc/service/report_generator_service.h b/usrc/service/report_generator_service.h
deleted file mode 100644
index 67fedb5..0000000
--- a/usrc/service/report_generator_service.h
+++ /dev/null
@@ -1,50 +0,0 @@
-#pragma once
-#include
-
-#include "project_dep.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * @brief 模块说明
- * 该模块监听FPGA秒时钟中断，和timecode中断
- * 当中断发生时，上报相应的数据。
- *
- * 该模块依赖:
- * fpag_if.c
- * config_service.c
- */
-
-/**
- * @brief 初始化上报模块
- *
- * @param timecode_trigger_pin
- * @param xync_trigger_pin
- */
-void ReportGeneratorService_init();
-
-/**
- * @brief 中断触发函数，当IO中断触发时，调用此方法
- *
- * @param gpiopin
- */
-void ReportGeneratorService_irq_trigger(uint16_t gpiopin);
-/**
- * @brief 清除xync计数
- */
-void ReportGeneratorService_xsync_set_count(uint32_t count);
-/**
- * @brief 获取xync计数
- *
- * @return uint32_t
- */
-uint32_t ReportGeneratorService_xsync_get_count(void);
-
-uint32_t ReportGeneratorService_set_camera_sync_code_report_period(uint32_t period);
-uint32_t ReportGeneratorService_get_camera_sync_code_report_period(void);
-
-#ifdef __cplusplus
-}
-#endif
\ No newline at end of file
diff --git a/zaf_protocol/zaf_ecode.c b/zaf_protocol/zaf_ecode.c
new file mode 100644
index 0000000..44c1587
--- /dev/null
+++ b/zaf_protocol/zaf_ecode.c
@@ -0,0 +1,26 @@
+#include "zaf_ecode.h"
+
+const char* zaf_error_code_2_str(zaf_error_code_t ecode) {
+ switch (ecode) {
+ case kxs_ec_success:
+ return "success";
+ case kxs_ec_overtime:
+ return "overtime";
+ case kxs_ec_socket_fail:
+ return "socket fail";
+ case kxs_ec_bind_fail:
+ return "bind fail";
+ case kxs_ec_send_fail:
+ return "send fail";
+ case kxs_ec_receive_fail:
+ return "receive fail";
+ case kxs_ec_setsockopt_rx_timeout_fail:
+ return "setsockopt rx timeout fail";
+ case kxs_ec_lose_connect:
+ return "lose connect";
+ case kxs_ec_param_error:
+ return "param error";
+ default:
+ return "unknown error";
+ }
+}
diff --git a/zaf_protocol/zaf_ecode.h b/zaf_protocol/zaf_ecode.h
new file mode 100644
index 0000000..64954a7
--- /dev/null
+++ b/zaf_protocol/zaf_ecode.h
@@ -0,0 +1,12 @@
+#pragma once
+typedef enum {
+ kxs_ec_success = 0,
+ kxs_ec_overtime = 1,
+ kxs_ec_socket_fail = 2,
+ kxs_ec_bind_fail = 3,
+ kxs_ec_send_fail = 4,
+ kxs_ec_receive_fail = 5,
+ kxs_ec_setsockopt_rx_timeout_fail = 6,
+ kxs_ec_lose_connect = 7,
+ kxs_ec_param_error = 8,
+} zaf_error_code_t;
diff --git a/zaf_protocol/zaf_port.h b/zaf_protocol/zaf_port.h
new file mode 100644
index 0000000..64b2141
--- /dev/null
+++ b/zaf_protocol/zaf_port.h
@@ -0,0 +1,5 @@
+#pragma once
+#include
+
+#define ZAF_SERVICE_DEVICE_PORT 20000 // 设备 端端口
+#define ZAF_SERVICE_PC_PORT 20001 // pc 端端口
\ No newline at end of file
diff --git a/zaf_protocol/zaf_protocol.c b/zaf_protocol/zaf_protocol.c
new file mode 100644
index 0000000..45b745a
--- /dev/null
+++ b/zaf_protocol/zaf_protocol.c
@@ -0,0 +1,2 @@
+#include "zaf_protocol.h"
+
diff --git a/zaf_protocol/zaf_protocol.h b/zaf_protocol/zaf_protocol.h
index fd48d4f..d93a2d3 100644
--- a/zaf_protocol/zaf_protocol.h
+++ b/zaf_protocol/zaf_protocol.h
@@ -1,183 +1,66 @@
#pragma once
#include
-/**
- * @brief XSYNC协议端口
- */
-#define IFLYTOP_XSYNC_SERVICE_XSYNC_PORT 19900 // xsync端端口
-#define IFLYTOP_XSYNC_SERVICE_PC_PORT 19901 // pc 端端口
+#include "zaf_ecode.h"
+#include "zaf_port.h"
+#include "zaf_regs.hpp"
-#define IFLYTOP_XSYNC_EVENT_REPORT_XSYNC_PORT 19902 // xsync端端口
-#define IFLYTOP_XSYNC_EVENT_REPORT_PC_PORT 19903 // pc端端口
+#pragma pack(1)
-#define IFLYTOP_XSYNC_CAMERA_SYNC_PACKET_XSYNC_PORT 13013 // xsync端端口
-#define IFLYTOP_XSYNC_CAMERA_SYNC_PACKET_PC_PORT 13014 // pc端端口
+/*******************************************************************************
+ * 通用指令包 *
+ *******************************************************************************/
+
+#define PACKET_HEADER 0x5A5A
+#define PACKET_TAIL 0xA5A5
/**
- * @brief
- * 协议说明
- *
- * kxsync_packet_type_reg_read:
- * tx: regadd
- * rx: ecode,regdata
*
- * kxsync_packet_type_reg_write
- * tx: regadd,regdata
- * rx: ecode,regdata
- *
- * kxsync_packet_type_reg_read_regs
- * tx: regstartadd,nreg
- * rx: ecode,regdatas
+ * 协议包分为:
+ * 包头(2Byte) 包类型(2Byte) Index(2Byte) 指令(2Byte） ndata(2byte) data[...] 和校验(1Byte) 包尾(2Byte)
*
*/
-typedef enum {
- kxsync_packet_type_none = 0,
- kxsync_packet_type_reg_read = 1,
- kxsync_packet_type_reg_write = 2,
- kxsync_packet_type_reg_read_regs = 3,
- kxsync_packet_type_timecode_report = 4,
-} xsync_protocol_cmd_t;
-
-typedef enum {
- kxsync_packet_type_cmd = 0,
- kxsync_packet_type_receipt = 1,
- kxsync_packet_type_report = 2,
-} xsync_protocol_packet_type_t;
-
-typedef enum {
- kxs_ec_success = 0,
- kxs_ec_overtime = 1,
- kxs_ec_socket_fail = 2,
- kxs_ec_bind_fail = 3,
- kxs_ec_send_fail = 4,
- kxs_ec_receive_fail = 5,
- kxs_ec_setsockopt_rx_timeout_fail = 6,
- kxs_ec_lose_connect = 7,
- kxs_ec_param_error = 8,
-}zaf_error_code_t;
-
-static inline const char*zaf_error_code_2_str(zaf_error_code_t ecode) {
- switch (ecode) {
- case kxs_ec_success:
- return "success";
- case kxs_ec_overtime:
- return "overtime";
- case kxs_ec_socket_fail:
- return "socket fail";
- case kxs_ec_bind_fail:
- return "bind fail";
- case kxs_ec_send_fail:
- return "send fail";
- case kxs_ec_receive_fail:
- return "receive fail";
- case kxs_ec_setsockopt_rx_timeout_fail:
- return "setsockopt rx timeout fail";
- case kxs_ec_lose_connect:
- return "lose connect";
- case kxs_ec_param_error:
- return "param error";
- default:
- return "unknown error";
- }
-}
-
-#pragma pack(1)
typedef struct {
- uint16_t type;
- uint16_t index;
- uint16_t cmd;
- uint16_t ndata;
- uint32_t data[]; // first is always checksum
-} iflytop_xsync_packet_header_t;
-
-typedef struct {
- uint32_t eventid;
- uint32_t data[];
-} iflytop_xsync_event_report_packet_t;
-
-typedef enum {
- ktimecode_report_event = 0,
- kxsync_work_state_report_event = 1,
-} iflytop_event_type_t;
-
-#define XYSNC_REG_DEVICE_INFO_START_ADD 0
-#define XYSNC_REG_STM32_CONFIG_START_ADD 16
-#define XYSNC_REG_FPGA_REG_START 32
-
-#define REG_ADD_OFF_STM32 (0x0000)
-#define REG_ADD_OFF_FPGA_TEST (0x00020)
-// 控制中心寄存器地址
-#define REG_ADD_OFF_CONTROL_SENSOR (0x00030)
-// 输入组件
-#define REG_ADD_OFF_TTLIN1 (0x0100)
-#define REG_ADD_OFF_TTLIN2 (0x0110)
-#define REG_ADD_OFF_TTLIN3 (0x0120)
-#define REG_ADD_OFF_TTLIN4 (0x0130)
-#define REG_ADD_OFF_TIMECODE_IN (0x0140)
-#define REG_ADD_OFF_GENLOCK_IN (0x0150)
-// 输出组件
-#define REG_ADD_OFF_TTLOUT1 (0x0200)
-#define REG_ADD_OFF_TTLOUT2 (0x0210)
-#define REG_ADD_OFF_TTLOUT3 (0x0220)
-#define REG_ADD_OFF_TTLOUT4 (0x0230)
-#define REG_ADD_OFF_TIMECODE_OUT (0x0240)
-#define REG_ADD_OFF_GENLOCK_OUT (0x0250)
-#define REG_ADD_OFF_STM32_IF (0x0260)
-// 调试组件
-#define REG_ADD_OFF_DEBUGER (0x0300)
+ uint16_t packet_header;
+ uint16_t packet_type; // zaf_protocol_packet_type_t
+ uint16_t index; //
+ uint16_t cmd; // zaf_protocol_cmd_t
+ uint16_t ndata; //
+ uint32_t data[]; // first is always checksum
+} zaf_packet_header_t;
+#pragma pack()
+/**
+ * @brief CMD
+ */
typedef enum {
- /**
- * @brief
- * REG 0(16) 设备信息基础寄存器
- */
- kxsync_reg_software_version = 0,
- kxsync_reg_manufacturer0 = 1,
- kxsync_reg_manufacturer1 = 2,
- kxsync_reg_product_type_id = 3,
- kxsync_reg_sn_id0 = 4,
- kxsync_reg_sn_id1 = 5,
- kxsync_reg_sn_id2 = 6,
- kxsync_reg_mac0 = 7,
- kxsync_reg_mac1 = 8,
-
- /**
- * @brief
- * REG 16(32) STM32配置寄存器0
- */
- kxsync_reg_stm32_obtaining_ip_mode = XYSNC_REG_STM32_CONFIG_START_ADD + 0,
- kxsync_reg_stm32_ip = XYSNC_REG_STM32_CONFIG_START_ADD + 1,
- kxsync_reg_stm32_gw = XYSNC_REG_STM32_CONFIG_START_ADD + 2,
- kxsync_reg_stm32_netmask = XYSNC_REG_STM32_CONFIG_START_ADD + 3,
- kxsync_reg_stm32_config0 = XYSNC_REG_STM32_CONFIG_START_ADD + 4, // bit0: timecode report enable, bit1: camera sync report enable
- kxsync_reg_stm32_camera_sync_signal_count = XYSNC_REG_STM32_CONFIG_START_ADD + 5, // 写任意数值之后清零
- // kxsync_reg_stm32_camera_sync_signal_report_period = XYSNC_REG_STM32_CONFIG_START_ADD + 6, // 多少帧上报一次
-
- kxsync_reg_stm32_action0 = XYSNC_REG_STM32_CONFIG_START_ADD + 14, // action reg
- kxsync_reg_stm32_action_val0 = XYSNC_REG_STM32_CONFIG_START_ADD + 15, // action val reg
-
-} xsync_reg_add_t;
-
-#define KXSYNC_REG_STM32_CONFIG0_MASK_TIMECODE_REPORT_ENABLE 0x01
-#define KXSYNC_REG_STM32_CONFIG0_MASK_CAMERA_SYNC_REPORT_ENABLE 0x02
+ kzaf_cmd_none = 0,
+ kzaf_cmd_reg_read = 1,
+ kzaf_cmd_reg_write = 2,
+ kzaf_cmd_reg_read_regs = 3,
+ kzaf_cmd_generator_new_mac = 4,
+ kzaf_cmd_factory_reset = 5,
+ kzaf_cmd_reboot = 6,
+ kzaf_cmd_storage_cfg = 7,
+} zaf_protocol_cmd_t;
+/**
+ * @brief 包类型
+ */
typedef enum {
- xsync_stm32_action_none, //
- xsync_stm32_action_generator_new_mac, //
- xsync_stm32_action_factory_reset, //
- xsync_stm32_action_reboot, //
- xsync_stm32_action_storage_cfg, //
-} xsync_stm32_action_t;
-
+ kzaf_packet_type_cmd = 0,
+ kzaf_packet_type_receipt = 1,
+ kzaf_packet_type_report = 2,
+} zaf_protocol_packet_type_t;
+
+/*******************************************************************************
+ * 业务逻辑枚举 *
+ *******************************************************************************/
typedef enum {
- kxsync_device_type_none = 0,
- kxsync_device_type_xsync = 1,
- kxsync_device_type_puck_station = 2,
- kxsync_device_type_encoder = 3,
-} xsync_device_type_t;
-
-typedef enum { obtaining_ip_mode_type_static = 0, obtaining_ip_mode_type_dhcp = 1 } obtaining_ip_mode_t;
+ obtaining_ip_mode_type_static = 0,
+ obtaining_ip_mode_type_dhcp = 1,
+} obtaining_ip_mode_t;
static inline const char* obtaining_ip_mode_to_string(obtaining_ip_mode_t mode) {
switch (mode) {
case obtaining_ip_mode_type_static:
@@ -188,4 +71,3 @@ static inline const char* obtaining_ip_mode_to_string(obtaining_ip_mode_t mode)
return "unknown";
}
}
-#pragma pack()
diff --git a/zaf_protocol/zaf_regs.hpp b/zaf_protocol/zaf_regs.hpp
new file mode 100644
index 0000000..eaa0d33
--- /dev/null
+++ b/zaf_protocol/zaf_regs.hpp
@@ -0,0 +1,37 @@
+#pragma once
+#define REGADD__STM32_COMMON (0x0010)
+#define REGADD__STM32_BUSINESS (0x0020)
+#define REGADD__FPGA_START (0x0100)
+
+typedef enum {
+ /**
+ * @brief
+ * REG 0(16) 设备信息基础寄存器
+ */
+ kreg_software_version = 0,
+ kreg_manufacturer0 = 1,
+ kreg_manufacturer1 = 2,
+ kreg_product_type_id = 3,
+ kreg_sn_id0 = 4,
+ kreg_sn_id1 = 5,
+ kreg_sn_id2 = 6,
+ kreg_mac0 = 7,
+ kreg_mac1 = 8,
+
+ /**
+ * @brief
+ * REG 16(32) STM32配置寄存器0
+ */
+ kreg_stm32_obtaining_ip_mode = REGADD__STM32_COMMON + 0,
+ kreg_stm32_ip = REGADD__STM32_COMMON + 1,
+ kreg_stm32_gw = REGADD__STM32_COMMON + 2,
+ kreg_stm32_netmask = REGADD__STM32_COMMON + 3,
+ kreg_stm32_config0 = REGADD__STM32_COMMON + 4, // bit0: timecode report enable, bit1: camera sync report enable
+
+ kreg_stm32_action0 = REGADD__STM32_COMMON + 14, // action reg
+ kreg_stm32_action_val0 = REGADD__STM32_COMMON + 15, // action val reg
+
+ kreg_stm32_temperature = REGADD__STM32_BUSINESS + 0,
+ kreg_stm32_fan0_error_flag = REGADD__STM32_BUSINESS + 1,
+
+} RegAdd_t;