p_transmit_disinfection_v2
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h2o2_ext_sensor_old_protocol
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zhaohe baa2e4a553
add timecode report logic 		2 years ago
.settings update 2 years ago
.vscode add timecode report logic 2 years ago
Core add timecode report logic 2 years ago
Drivers update 2 years ago
LWIP update 2 years ago
Middlewares/Third_Party init . 2 years ago
iflytop_xsync@6434f422ec add timecode report logic 2 years ago
iflytop_xsync_protocol@cb1114b21b update 2 years ago
usrc add timecode report logic 2 years ago
.clang-format update 2 years ago
.cproject init . 2 years ago
.gitignore update 2 years ago
.gitmodules add dep lib 2 years ago
.mxproject update 2 years ago
.project update 2 years ago
README.md add timecode report logic 2 years ago
STM32F407VETX_FLASH.ld update 2 years ago
STM32F407VETX_RAM.ld first commit 2 years ago
xsync_stm32 Debug.launch update 2 years ago
xsync_stm32.cfg Removed submodule sdk 2 years ago
xsync_stm32.ioc add timecode report logic 2 years ago
xsync_stm32.launch Removed submodule sdk 2 years ago
xsync_v3.pdf init project 2 years ago

README.md 

ref:https://iflytop1.feishu.cn/docx/FPqjdaTtkoBeU9x4qbjcD6vxnUc

FPGA


1. 将XyncInternal内部信号导出到ttl输出模块（包括内部timecode信号，外部timecode信号）OK
2. 完成XyncInternalPC端上位机相关配置 OK

2. 创建Timecode输出模块，监听Timecode输出信号到debug接口，完成timecodePC端上位机相关配置（输出同时输出到STM32）
        影响网口输出
        影响TIMECODE物理接口输出
3. 创建Genlock输出模块，完成Genlock输出模块PC端上位机相关配置（输出同时输出到STM32），计数清空信号
        影响网口输出
        影响GENLOCK物理接口输出

5. 实现Timecode输入解析。测试Timecode