syncbox16ch_fpga/source/src/zutils/zutils_pluse_generator_v2.v

module zutils_pluse_generator_v2 (
    input clk,   //clock input
    input rst_n, //asynchronous reset input, low active

    input  wire [31:0] pluse_width,
    input  wire [31:0] pluse_delay,
    input  wire        trigger,
    output reg         output_signal

);


  reg [31:0] counter = 0;
  reg [31:0] tohigh_count = 0;
  reg [31:0] counter_init_count = 0;

  always @(*) begin
    tohigh_count       <= pluse_width;
    counter_init_count <= pluse_width + pluse_delay;
  end

  always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
      counter       <= 0;
      output_signal <= 0;
    end else begin
      if (trigger) begin
        counter       <= counter_init_count;
        output_signal <= 0;
      end else begin
        if (counter != 0) begin

          counter <= counter - 1;
          if (counter == tohigh_count) begin
            output_signal <= 1;
          end

        end else begin
          output_signal <= 0;
          counter       <= 0;
        end
      end
    end
  end

endmodule