syncbox16ch_fpga/source/src/input/genlock_input_module.v

`include "../config.v"
module genlock_input_module #(
    parameter REG_START_ADD  = 0,
    parameter SYS_CLOCK_FREQ = 10000000
) (

    input clk,   //! 时钟输入
    input rst_n, //! 复位输入

    input       [31:0] addr,     //! 寄存器地址
    input       [31:0] wr_data,  //! 写入数据
    input              wr_en,    //! 写使能
    output wire [31:0] rd_data,  //! 读出数据

    input genlock_in_hsync,  //! genlock hsync
    input genlock_in_vsync,  //! genlock vsync
    input genlock_in_fsync,  //! genlock fsync

    output genlock_freq_signal,  //! genlock freq signal
    output genlock_in_state_led


);

  reg  [31:0] r1_genlock_freq_detect_bias;
  wire [31:0] r2_genlock_freq;

  wire [31:0] reg_wr_index;
  zutils_register_advanced #(
      .REG_START_ADD(REG_START_ADD)
  ) _register (
      .clk       (clk),
      .rst_n     (rst_n),
      .addr      (addr),
      .wr_data   (wr_data),
      .wr_en     (wr_en),
      .rd_data   (rd_data),
      .reg1      (r1_genlock_freq_detect_bias),
      .reg2      (r2_genlock_freq),
      .reg_wr_sig(reg_wr_sig),
      .reg_index (reg_wr_index)
  );

  always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
      r1_genlock_freq_detect_bias <= `FREQ_DETECT_BIAS_DEFAULT;
    end else begin
      if (reg_wr_sig) begin
        case (reg_wr_index)
          1: r1_genlock_freq_detect_bias <= wr_data;
          default: begin
          end
        endcase
      end
    end
  end

  zutils_freq_detector_v2 freq_detector1 (
      .clk             (clk),
      .rst_n           (rst_n),
      .freq_detect_bias(r1_genlock_freq_detect_bias),
      .pluse_input     (genlock_in_vsync),
      .pluse_width_cnt (r2_genlock_freq)
  );

  assign genlock_freq_signal  = genlock_in_vsync;
  assign genlock_in_state_led = 1;

endmodule