syncbox16ch_fpga/source/src/zutils/zutils_freq_detector.v

//
//  @功能:
//          1. 滤波(add later)
//          2. 频率探测
//          3. 输出灯光控制
//
module zutils_freq_detector
  (

    input clk,  //! 时钟输入
    input rst_n,     //! 复位输入

    input pluse_input, //! 输入信号1

    //处理后的信号输出
    output reg [31:0]pluse_width_cnt //! 输出捕获到的脉冲宽度
  );


  reg in_signal_last;
  reg in_signal_rising_edge; //! 上升沿
  //!in_signal_last 捕获
  always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
      in_signal_last <= 0;
    end
    else begin
      in_signal_last <= pluse_input;
    end
  end

  //!边沿捕获
  always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
      in_signal_rising_edge  <= 0;
    end
    else begin
      if (in_signal_last == 0 && pluse_input == 1) begin
        in_signal_rising_edge  <= 1;
      end
      else if (in_signal_last == 1 && pluse_input == 0) begin
        in_signal_rising_edge  <= 0;
      end
      else begin
        in_signal_rising_edge  <= 0;
      end
    end
  end



  // 计数器
  reg [31:0] pluse_width_cnt_reg;
  //!脉冲宽度计数
  always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
      pluse_width_cnt_reg <= 0;
      pluse_width_cnt <= 32'hffff_ffff;
    end
    else begin
      if (in_signal_rising_edge) begin
        pluse_width_cnt <= pluse_width_cnt_reg;
        pluse_width_cnt_reg <= 0;
      end
      else begin
        pluse_width_cnt_reg <= pluse_width_cnt_reg + 1;
        if(pluse_width_cnt_reg >= 32'd11000000) begin //TODO:支持可配置
          pluse_width_cnt <= 32'hffff_ffff;
          pluse_width_cnt_reg <= 0;
        end
      end
    end
  end

endmodule