syncbox16ch_fpga/ipcore/DebugCoreIst/DebugCoreIst.fdc

// Created by IP Generator (Version 2021.1-SP7 build 86875)



define_current_design {DebugCoreIst}

###==== BEGIN Header
create_clock {p:drck_in} -period {66.6666}

# Custom constraint commands may be added outside of the SCOPE tab sections bounded with BEGIN/END.
# These sections are generated from SCOPE spreadsheet tabs.

###==== END Header
###==== BEGIN Clocks - (Populated from tab in SCOPE, do not edit)

###==== END Clocks