syncbox16ch_fpga/source/src/timecode/timecode_comparator.v

module timecode_comparator (
    input [31:0] timecodeA0,
    input [31:0] timecodeA1,
    input [31:0] timecodeB0,
    input [31:0] timecodeB1,
    output  eq
);

  wire [7:0] a_frame;
  wire [7:0] a_frame10;
  wire [7:0] a_sec;
  wire [7:0] a_sec10;
  wire [7:0] a_min;
  wire [7:0] a_min10;
  wire [7:0] a_hour;
  wire [7:0] a_hour10;

  wire [7:0] b_frame;
  wire [7:0] b_frame10;
  wire [7:0] b_sec;
  wire [7:0] b_sec10;
  wire [7:0] b_min;
  wire [7:0] b_min10;
  wire [7:0] b_hour;
  wire [7:0] b_hour10;


  assign a_frame = timecodeA0[7:0] & 8'b0000_1111;
  assign a_frame10 = timecodeA0[15:8] & 8'b0000_0011;
  assign a_sec = timecodeA0[23:16] & 8'b0000_1111;
  assign a_sec10 = timecodeA0[31:24] & 8'b0000_0111;
  assign a_min = timecodeA1[7:0] & 8'b0000_1111;
  assign a_min10 = timecodeA1[15:8] & 8'b0000_0111;
  assign a_hour = timecodeA1[23:16] & 8'b0000_1111;
  assign a_hour10 = timecodeA1[31:24] & 8'b0000_0011;


  assign b_frame = timecodeB0[7:0] & 8'b0000_1111;
  assign b_frame10 = timecodeB0[15:8] & 8'b0000_0011;
  assign b_sec = timecodeB0[23:16] & 8'b0000_1111;
  assign b_sec10 = timecodeB0[31:24] & 8'b0000_0111;
  assign b_min = timecodeB1[7:0] & 8'b0000_1111;
  assign b_min10 = timecodeB1[15:8] & 8'b0000_0111;
  assign b_hour = timecodeB1[23:16] & 8'b0000_1111;
  assign b_hour10 = timecodeB1[31:24] & 8'b0000_0011;



  assign eq = a_frame == b_frame &&
                a_frame10 == b_frame10 &&
                a_sec == b_sec &&
                a_sec10 == b_sec10 &&
                a_min == b_min &&
                a_min10 == b_min10 &&
                a_hour == b_hour &&
                a_hour10 == b_hour10;

endmodule