syncbox16ch_fpga/source/src/transmitter.v

module transmitter (
    input wire [7:0] din,
    input wire wr_en,
    input wire clk_50m,
    input wire clken,
    input wire rest_n,
    output reg tx,
    output wire tx_busy,
    output wire [1:0] t_state,
    output wire [2:0] t_bitpos,
    output wire t_worksignal
);
  parameter STATE_IDLE = 2'b00;
  parameter STATE_START = 2'b01;
  parameter STATE_DATA = 2'b10;
  parameter STATE_STOP = 2'b11;
  initial begin
    tx = 1'b1;
  end


  reg [7:0] data = 8'h00;
  reg [2:0] bitpos = 3'h0;
  reg [1:0] state = STATE_IDLE;
  reg worksignal = 0;

  assign workflag = (state != STATE_IDLE);

  always @(posedge clken, posedge wr_en) begin
    if (wr_en) begin
      worksignal <= 1'b1;
      data <= din;
    end else begin
      if (!workflag) worksignal <= 1'b0;
    end
  end


  always @(posedge clken or negedge rest_n) begin
    if (!rest_n) begin
      state <= STATE_IDLE;
    end else begin
      case (state)
        STATE_IDLE: begin
          tx <= 1'b1;
          if (worksignal) begin
            state  <= STATE_START;
            bitpos <= 0;
          end
        end
        STATE_START: begin
          tx <= 1'b0;
          state <= STATE_DATA;
        end
        STATE_DATA: begin
          if (bitpos == 3'h7) state <= STATE_STOP;
          else bitpos <= bitpos + 3'h1;
          tx <= data[bitpos];
        end
        STATE_STOP: begin
          tx <= 1'b1;
          state <= STATE_IDLE;
        end
        default begin
          tx <= 1'b1;
          state <= STATE_IDLE;
        end
      endcase
    end
  end

  assign tx_busy = (state != STATE_IDLE);
  assign t_state = state;
  assign t_bitpos = bitpos;
  assign t_worksignal = worksignal;
endmodule