syncbox16ch_fpga/source/src/zutils/zutils_debug_led.v

module zutils_debug_led #(
    parameter PERIOD_COUNT = 1000000
) (
    input clk,  //clock input
    input rst_n,  //asynchronous reset input, low active
    output reg debug_led
);

    reg [31:0] counter = 0;

    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            counter <= 0;
            debug_led <= 1'b0;
        end else begin
            if (counter == PERIOD_COUNT - 1) begin
                counter <= 0;
                debug_led <= ~debug_led;
            end else begin
                counter <= counter + 1;
            end
        end
    end

endmodule