syncbox16ch_fpga/source/src/zutils/zutils_multiplexer_4t1.v

module zutils_multiplexer_4t1 (
    input [31:0] chooseindex,
    input wire signal0,
    input wire signal1,
    input wire signal2,
    input wire signal3,
    output reg signalout
);


  always @(*) begin
    case (chooseindex)
      0: begin
        signalout = signal0;
      end
      1: begin
        signalout = signal1;
      end
      2: begin
        signalout = signal2;
      end
      3: begin
        signalout = signal3;
      end
      default: begin
        signalout = 0;
      end
    endcase
  end
endmodule