|
|
`include "../config.v"module light_src_ctrl #( parameter REG_START_ADD = 0, parameter SYS_CLOCK_FREQ = 100000000, parameter ID = 1) ( input clk, //clock input input rst_n, //asynchronous reset input, low active
//寄存器读写接口 input [31:0] addr, input [31:0] wr_data, input wr_en, output wire [31:0] rd_data,
input [31:0] signal_in,
output wire lt_intensity_ctrl, output wire lt_en, input wire lt_error_sig_in);
/******************************************************************************* * 寄存器列表 * *******************************************************************************/
reg [31:0] reg1_source_select; reg [31:0] reg2_en_sig_ctrl_mode; //!0:触发模式 1:转发模式 reg [31:0] reg3_light_intensity_ctrl_mode; //!0:固定强度 reg [31:0] reg4_trigger_mode_pluse_num; reg [31:0] reg5_trigger_mode_pluse_interval; reg [31:0] reg6_trigger_mode_pluse_width; reg [31:0] reg7_trigger_mode_first_pluse_offset; reg [31:0] reg8_trigger_mode_output_polarity; reg [31:0] reg9_light_intensity_cnt; reg [31:0] regA_light_driver_freq_cnt; reg [31:0] regC_freq_detect_bias; reg [31:0] regD_light_src_error_state; wire [31:0] regE_in_sig_freq_detect; wire [31:0] regF_out_sig_freq_detect; wire [31:0] reg_wr_index; //!寄存器写入时相对地址
//!TTLOUT_寄存器自动赋值选择器 zutils_register_advanced #( .REG_START_ADD(REG_START_ADD) ) _register ( .clk (clk), .rst_n (rst_n), .addr (addr), .wr_data(wr_data), .wr_en (wr_en), .rd_data(rd_data),
.reg1(reg1_source_select), .reg2(reg2_en_sig_ctrl_mode), .reg3(reg3_light_intensity_ctrl_mode), .reg4(reg4_trigger_mode_pluse_num), .reg5(reg5_trigger_mode_pluse_interval), .reg6(reg6_trigger_mode_pluse_width), .reg7(reg7_trigger_mode_first_pluse_offset), .reg8(reg8_trigger_mode_output_polarity), .reg9(reg9_light_intensity_cnt), .regA(regA_light_driver_freq_cnt), .regC(regC_freq_detect_bias), .regD(regD_light_src_error_state), .regE(regE_in_sig_freq_detect), .regF(regF_out_sig_freq_detect),
.reg_wr_sig(reg_wr_sig), .reg_index (reg_wr_index) );
//!寄存器写入逻辑
localparam pluse_interval_init_val = 1 * (SYS_CLOCK_FREQ / 32'd1000_000); //1us localparam pluse_width_initval = 30 * (SYS_CLOCK_FREQ / 32'd1000_000); //1us
always @(posedge clk or negedge rst_n) begin if (!rst_n) begin reg1_source_select <= `SIG_INTERNAL_CLK; reg2_en_sig_ctrl_mode <= 0; reg3_light_intensity_ctrl_mode <= 0; reg4_trigger_mode_pluse_num <= 1; reg5_trigger_mode_pluse_interval <= pluse_interval_init_val; reg6_trigger_mode_pluse_width <= pluse_width_initval; reg7_trigger_mode_first_pluse_offset <= pluse_interval_init_val * ID + ((ID - 1) * pluse_width_initval); reg8_trigger_mode_output_polarity <= 1; reg9_light_intensity_cnt <= (SYS_CLOCK_FREQ / 30000 / 10); //100k regA_light_driver_freq_cnt <= (SYS_CLOCK_FREQ / 30000); //100k regC_freq_detect_bias <= `FREQ_DETECT_BIAS_DEFAULT; end else begin if (reg_wr_sig) begin case (reg_wr_index) 32'h1: reg1_source_select <= reg_wr_index; 32'h2: reg2_en_sig_ctrl_mode <= reg_wr_index; 32'h3: reg3_light_intensity_ctrl_mode <= reg_wr_index; 32'h4: reg4_trigger_mode_pluse_num <= reg_wr_index; 32'h5: reg5_trigger_mode_pluse_interval <= reg_wr_index; 32'h6: reg6_trigger_mode_pluse_width <= reg_wr_index; 32'h7: reg7_trigger_mode_first_pluse_offset <= reg_wr_index; 32'h8: reg8_trigger_mode_output_polarity <= reg_wr_index; 32'h9: reg9_light_intensity_cnt <= reg_wr_index; 32'hA: regA_light_driver_freq_cnt <= reg_wr_index; 32'hC: regC_freq_detect_bias <= reg_wr_index; default: begin end endcase end end end
wire signal_in_choose; //!选中的信号 wire signal_in_choose_rsing_edge; //!选中的信号 wire signal_en_output; //!EN信号输出 wire signal_lt_intensity; //!光强输出
//!信号选择器 zutils_multiplexer_32t1 signal_in_multiplexer ( .chooseindex(reg1_source_select), .signal (signal_in), .signalout (signal_in_choose) );
zutils_edge_detecter edge_detecter ( .clk (clk), .rst_n (rst_n), .in_signal (signal_in_choose), .in_signal_rising_edge(signal_in_choose_rsing_edge) );
zutils_pluse_generator_v2 pluse_generator ( .clk (clk), .rst_n(rst_n),
.pluse_width (reg6_trigger_mode_pluse_width), .pluse_delay (reg7_trigger_mode_first_pluse_offset), .trigger (signal_in_choose_rsing_edge), .output_signal(signal_en_output)
);
/******************************************************************************* * 光源亮度信号发生器 * *******************************************************************************/ zutils_pwm_generator_v2 signal_lt_intensity_generator ( .clk (clk), .rst_n(rst_n),
.pluse_width_cnt (reg9_light_intensity_cnt), .pluse_period_cnt(regA_light_driver_freq_cnt),
.output_signal(signal_lt_intensity) );
/******************************************************************************* * 异常信号捕获 * *******************************************************************************/ always @(posedge clk or negedge rst_n) begin if (!rst_n) begin regD_light_src_error_state <= 0; end else begin regD_light_src_error_state[0] <= lt_error_sig_in; end end
assign lt_intensity_ctrl = signal_lt_intensity; assign lt_en = signal_en_output;
endmodule
|
