syncbox16ch_fpga/source/src/zutils/zutils_register.v

module zutils_register16 #(
    parameter REG_START_ADD = 0,
    parameter REG0_INIT = 0,
    parameter REG1_INIT = 0,
    parameter REG2_INIT = 0,
    parameter REG3_INIT = 0,
    parameter REG4_INIT = 0,
    parameter REG5_INIT = 0,
    parameter REG6_INIT = 0,
    parameter REG7_INIT = 0,
    parameter REG8_INIT = 0,
    parameter REG9_INIT = 0,
    parameter REGA_INIT = 0,
    parameter REGB_INIT = 0,
    parameter REGC_INIT = 0,
    parameter REGD_INIT = 0,
    parameter REGE_INIT = 0,
    parameter REGF_INIT = 0

) (
    input clk,   //clock input
    input rst_n, //asynchronous reset input, low active

    //regbus interface
    input [31:0] addr,
    input [31:0] wr_data,
    input        wr_en,

    output [31:0] rd_data,  //received serial data 

    output [31:0] reg0,
    output [31:0] reg1,
    output [31:0] reg2,
    output [31:0] reg3,
    output [31:0] reg4,
    output [31:0] reg5,
    output [31:0] reg6,
    output [31:0] reg7,
    output [31:0] reg8,
    output [31:0] reg9,
    output [31:0] regA,
    output [31:0] regB,
    output [31:0] regC,
    output [31:0] regD,
    output [31:0] regE,
    output [31:0] regF
);

  parameter REG_END_ADD = REG_START_ADD + 16 - 1;  //寄存器结束地址
  reg [31:0] data[0:15] = 0;

  assign reg0 = data[0];
  assign reg1 = data[1];
  assign reg2 = data[2];
  assign reg3 = data[3];
  assign reg4 = data[4];
  assign reg5 = data[5];
  assign reg6 = data[6];
  assign reg7 = data[7];
  assign reg8 = data[8];
  assign reg9 = data[9];
  assign regA = data[10];
  assign regB = data[11];
  assign regC = data[12];
  assign regD = data[13];
  assign regE = data[14];
  assign regF = data[15];

  integer i;
  always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
      data[0]  <= REG0_INIT;
      data[1]  <= REG1_INIT;
      data[2]  <= REG2_INIT;
      data[3]  <= REG3_INIT;
      data[4]  <= REG4_INIT;
      data[5]  <= REG5_INIT;
      data[6]  <= REG6_INIT;
      data[7]  <= REG7_INIT;
      data[8]  <= REG8_INIT;
      data[9]  <= REG9_INIT;
      data[10] <= REGA_INIT;
      data[11] <= REGB_INIT;
      data[12] <= REGC_INIT;
      data[13] <= REGD_INIT;
      data[14] <= REGE_INIT;
      data[15] <= REGF_INIT;
    end else begin
      if (wr_en && addr >= REG_START_ADD && addr <= REG_END_ADD)
        data[addr-REG_START_ADD] <= wr_data;
    end
  end
  assign rd_data = (addr >= REG_START_ADD && addr <= REG_END_ADD) ? data[addr-REG_START_ADD] : 31'b0;


endmodule