syncbox16ch_fpga/source/src/timecode/timecode_basesig_generator.v

module timecode_basesig_generator #(
    parameter SYS_CLOCK_FREQ = 10000000
) (

    input clk,
    input rst_n,

    input [31:0] timecode_format,

    input wire en,
    output out_timecode_trigger_sig,
    output reg out_first_frame_sig,

    output reg [7:0] out_frame_num,
    output reg out_drop_frame
);

  localparam FPS2398Format = 0;
  localparam FPS2400Format = 1;
  localparam FPS2500Format = 2;
  localparam FPS2997Format = 3;
  localparam FPS2997DropFormat = 4;
  localparam FPS3000Format = 5;


  /*******************************************************************************
   *                                clk generator                                *
   *******************************************************************************/
  wire fps2398format_clk;
  wire fps2400format_clk;
  wire fps2500format_clk;
  wire fps2997format_clk;
  wire fps2997dropformat_clk;
  wire fps3000format_clk;

  zutils_pwm_generator_advanced #(
      .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ),
      .OUTPUT_FREQ_P00(2398)
  ) fps2398format (
      .clk(clk),
      .rst_n(rst_n),
      .ctrl_sig(en),
      .output_signal(fps2398format_clk)
  );

  zutils_pwm_generator_advanced #(
      .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ),
      .OUTPUT_FREQ_P00(2400)
  ) fps2400format (
      .clk(clk),
      .rst_n(rst_n),
      .ctrl_sig(en),
      .output_signal(fps2400format_clk)
  );

  zutils_pwm_generator_advanced #(
      .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ),
      .OUTPUT_FREQ_P00(2500)
  ) fps2500format (
      .clk(clk),
      .rst_n(rst_n),
      .ctrl_sig(en),
      .output_signal(fps2500format_clk)
  );

  zutils_pwm_generator_advanced #(
      .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ),
      .OUTPUT_FREQ_P00(2997)
  ) fps2997format (
      .clk(clk),
      .rst_n(rst_n),
      .ctrl_sig(en),
      .output_signal(fps2997format_clk)
  );

  zutils_pwm_generator_advanced #(
      .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ),
      .OUTPUT_FREQ_P00(2997)
  ) fps2997dropformat (
      .clk(clk),
      .rst_n(rst_n),
      .ctrl_sig(en),
      .output_signal(fps2997dropformat_clk)
  );

  zutils_pwm_generator_advanced #(
      .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ),
      .OUTPUT_FREQ_P00(3000)
  ) fps3000format (
      .clk(clk),
      .rst_n(rst_n),
      .ctrl_sig(en),
      .output_signal(fps3000format_clk)
  );


  zutils_multiplexer_32t1_v2 timecode_clk_output_mult (
      .chooseindex(timecode_format),
      //in
      .in0(fps2398format_clk),
      .in1(fps2400format_clk),
      .in2(fps2500format_clk),
      .in3(fps2997format_clk),
      .in4(fps2997dropformat_clk),
      .in5(fps3000format_clk),
      //out
      .out(out_timecode_sig_clk_pwm)
  );

  zutils_edge_detecter timecode_sig_clk_output_edge_detecter (
      .clk(clk),
      .rst_n(rst_n),
      .in_signal(out_timecode_sig_clk_pwm),
      .in_signal_rising_edge(out_timecode_trigger_sig)
  );


  always @(posedge clk or negedge rst_n) begin
    if (!rst_n || !en) begin
      out_first_frame_sig <= 1;
    end else begin
      if (out_first_frame_sig && out_timecode_trigger_sig) begin
        out_first_frame_sig <= 0;
      end
    end
  end

  /*******************************************************************************
   *                                  格式解析                                   *
   *******************************************************************************/

  always @(*) begin
    case (timecode_format)
      FPS2398Format: begin
        out_frame_num  <= 24;
        out_drop_frame <= 0;
      end
      FPS2400Format: begin
        out_frame_num  <= 24;
        out_drop_frame <= 0;
      end
      FPS2500Format: begin
        out_frame_num  <= 25;
        out_drop_frame <= 0;
      end
      FPS2997Format: begin
        out_frame_num  <= 30;
        out_drop_frame <= 0;
      end
      FPS2997DropFormat: begin
        out_frame_num  <= 30;
        out_drop_frame <= 0;
      end
      default begin
        out_frame_num  <= 30;
        out_drop_frame <= 0;
      end
    endcase
  end
endmodule