syncbox16ch_fpga/source/src/timecode/timecode_generator.v

module timecode_generator #(
    parameter SYS_CLOCK_FREQ = 10000000
) (
    input clk,   //clock input
    input rst_n, //asynchronous reset input, low active

    input [31:0] timecode_format,

    input timecode0_wen,
    input [31:0] timecode0,
    output [31:0] timecode0_export,
    input timecode1_wen,
    input [31:0] timecode1,
    output [31:0] timecode1_export,

    input en,

    output wire out_timecode_serial_data,
    output wire out_trigger_sig,
    output wire [31:0] out_timecode0,
    output wire [31:0] out_timecode1
);

  //



  wire [7:0] out_frame_num;
  wire out_drop_frame;

  wire frame_trigger_sig;
  wire first_frame_sig;


  timecode_basesig_generator #(
      .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ)
  ) basesig_generator (
      .clk(clk),
      .rst_n(rst_n),
      .timecode_format(timecode_format),
      .en(en),
      .out_timecode_trigger_sig(frame_trigger_sig),  //帧时钟触发信号
      .out_first_frame_sig(first_frame_sig),
      .out_frame_num(out_frame_num),
      .out_drop_frame(out_drop_frame)
  );

  reg  [63:0] timecode;
  wire [63:0] timecode_next;
  timecode_nextcode nextcode (
      .frame_mum(out_frame_num),
      .drop(out_drop_frame),
      .timecode(timecode),
      .timecode_next(timecode_next)
  );

  reg timecode_trigger_sig;
  always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
      timecode <= 0;
      timecode_trigger_sig <= 0;

    end else begin
      if (!en) begin
        if (timecode0_wen || timecode1_wen) begin
          if (timecode0_wen) begin
            timecode[31:0] <= timecode0;
          end
          if (timecode1_wen) begin
            timecode[63:32] <= timecode1;
          end
        end
      end else begin
        if (frame_trigger_sig) begin
          if (!first_frame_sig) begin
            timecode <= timecode_next;
          end
          timecode_trigger_sig <= 1;
        end else begin
          timecode_trigger_sig <= 0;
        end
      end


    end
  end

  assign timecode0_export = timecode[31:0];
  assign timecode1_export = timecode[63:32];


  wire [63:0] out_timecode;
  timecode_serialization #(
      .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ)
  ) serialization (
      .clk(clk),
      .rst_n(rst_n),
      .timecode_format(timecode_format),

      .trigger_sig(timecode_trigger_sig),
      .timecode(timecode),

      .out_timecode_serial_data(out_timecode_serial_data),
      .out_trigger_sig(out_trigger_sig),
      .out_timecode(out_timecode)
  );

  // out_timecode0
  // out_timecode1

  assign out_timecode0 = out_timecode[31:0];
  assign out_timecode1 = out_timecode[63:32];

endmodule