syncbox16ch_fpga/source/src/spi_reg_bus.v

`include "config.v"
module spi_reg_bus (
    input clk,   //clock input
    input rst_n, //asynchronous reset input, low active

    //regbus interface
    output      [31:0] addr,
    output      [31:0] wr_data,
    output             wr_en,
    //
    input  wire        spi_cs_pin,   //
    input  wire        spi_clk_pin,  //
    input  wire        spi_rx_pin,   //
    output wire        spi_tx_pin,

    input [31:0] rd_data_module_fpga_info,
    input [31:0] rd_data_module_ttlin,
    input [31:0] rd_data_module_timecode_in,
    input [31:0] rd_data_module_genlock_in,
    input [31:0] rd_data_module_internal_timecode,
    input [31:0] rd_data_module_internal_genlock,
    input [31:0] rd_data_module_internal_clock,
    input [31:0] rd_data_module_ttlout1,
    input [31:0] rd_data_module_ttlout2,
    input [31:0] rd_data_module_ttlout3,
    input [31:0] rd_data_module_ttlout4,
    input [31:0] rd_data_module_timecode_out,
    input [31:0] rd_data_module_genlock_out,
    input [31:0] rd_data_module_camera_sync_out,
    input [31:0] rd_data_module_sys_timecode,
    input [31:0] rd_data_module_sys_genlock,
    input [31:0] rd_data_module_sys_clock,
    input [31:0] rd_data_module_record_sig_generator
);

  reg [31:0] rd_data;

  spi_reg_reader spi_reg_reader_inst (
      .clk        (clk),
      .rst_n      (rst_n),
      .addr       (addr),
      .wr_data    (wr_data),
      .wr_en      (wr_en),
      .rd_data    (rd_data),
      .spi_cs_pin (spi_cs_pin),
      .spi_clk_pin(spi_clk_pin),
      .spi_rx_pin (spi_rx_pin),
      .spi_tx_pin (spi_tx_pin)
  );

  // 数据路由
  wire [31:0] addr_group;
  assign addr_group = addr & 31'hFFFF_FFF0;
  always @(*) begin
    case (addr_group)
      `REGADDOFF__FPGA_INFO:            rd_data <= rd_data_module_fpga_info;
      `REGADDOFF__TTLIN:                rd_data <= rd_data_module_ttlin;
      `REGADDOFF__TIMECODE_IN:          rd_data <= rd_data_module_timecode_in;
      `REGADDOFF__GENLOCK_IN:           rd_data <= rd_data_module_genlock_in;
      `REGADDOFF__INTERNAL_TIMECODE:    rd_data <= rd_data_module_internal_timecode;
      `REGADDOFF__INTERNAL_GENLOCK:     rd_data <= rd_data_module_internal_genlock;
      `REGADDOFF__INTERNAL_CLOCK:       rd_data <= rd_data_module_internal_clock;
      `REGADDOFF__TTLOUT1:              rd_data <= rd_data_module_ttlout1;
      `REGADDOFF__TTLOUT2:              rd_data <= rd_data_module_ttlout2;
      `REGADDOFF__TTLOUT3:              rd_data <= rd_data_module_ttlout3;
      `REGADDOFF__TTLOUT4:              rd_data <= rd_data_module_ttlout4;
      `REGADDOFF__TIMECODE_OUT:         rd_data <= rd_data_module_timecode_out;
      `REGADDOFF__GENLOCK_OUT:          rd_data <= rd_data_module_genlock_out;
      `REGADDOFF__CAMERA_SYNC_OUT:      rd_data <= rd_data_module_camera_sync_out;
      `REGADDOFF__SYS_TIMECODE:         rd_data <= rd_data_module_sys_timecode;
      `REGADDOFF__SYS_GENLOCK:          rd_data <= rd_data_module_sys_genlock;
      `REGADDOFF__SYS_CLOCK:            rd_data <= rd_data_module_sys_clock;
      `REGADDOFF__RECORD_SIG_GENERATOR: rd_data <= rd_data_module_record_sig_generator;

      default: rd_data <= 0;
    endcase
  end


endmodule