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V7

master
zhaohe 1 year ago
parent
799bb7078e
commit
14aee36022
8 changed files with 99 additions and 55 deletions
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  1. 2
      README.md
  2. 54
      camera_light_src_timing_controller_fpga.pds
  3. BIN
      release/V7/Top.sbit
  4. BIN
      release/V7/Top.sfc
  5. 2
      source/src/config.v
  6. 46
      source/src/top.v
  7. 12
      source/src/trigger_source/trigger_source_base_module.v
  8. 38
      source/src/zutils/zsimple_pluse_generator.v

2
README.md
View File

@ -5,6 +5,8 @@
```
```
V7:
1.修复PLL的BUG
V6:
1.光耦输入默认反向
2.修改内部触发默认滤波参数为0

54
camera_light_src_timing_controller_fpga.pds
View File

@ -1,5 +1,5 @@
(_flow fab_demo "2021.1-SP7"
(_comment "Generated by Fabric Compiler (version on 2021.1-SP7<build 86875>) at Mon May 6 11:31:28 2024")
(_comment "Generated by Fabric Compiler (version on 2021.1-SP7<build 86875>) at Tue May 7 10:48:58 2024")
(_version "1.0.5")
(_status "initial")
(_project
@ -19,7 +19,7 @@
(_input
(_file "source/src/top.v" + "Top:"
(_format verilog)
(_timespec "2024-05-06T11:27:37")
(_timespec "2024-05-07T10:45:38")
)
(_file "source/src/spi_reg_reader.v"
(_format verilog)
@ -187,7 +187,7 @@
)
(_file "source/src/trigger_source/trigger_source_base_module.v"
(_format verilog)
(_timespec "2024-05-06T11:27:26")
(_timespec "2024-05-07T09:51:52")
)
(_file "source/src/output/light_src_ctrl.v"
(_format verilog)
@ -207,7 +207,7 @@
)
(_file "source/src/zutils/zsimple_pluse_generator.v"
(_format verilog)
(_timespec "2024-04-23T15:03:06")
(_timespec "2024-05-07T10:36:44")
)
)
)
@ -279,17 +279,17 @@
(_db_output
(_file "compile/Top_comp.adf"
(_format adif)
(_timespec "2024-05-06T11:30:03")
(_timespec "2024-05-07T10:47:19")
)
)
(_output
(_file "compile/Top.cmr"
(_format verilog)
(_timespec "2024-05-06T11:30:01")
(_timespec "2024-05-07T10:47:16")
)
(_file "compile/cmr.db"
(_format text)
(_timespec "2024-05-06T11:30:03")
(_timespec "2024-05-07T10:47:19")
)
)
)
@ -305,21 +305,21 @@
(_db_output
(_file "synthesize/Top_syn.adf"
(_format adif)
(_timespec "2024-05-06T11:30:21")
(_timespec "2024-05-07T10:47:41")
)
)
(_output
(_file "synthesize/Top_syn.vm"
(_format structural_verilog)
(_timespec "2024-05-06T11:30:22")
(_timespec "2024-05-07T10:47:43")
)
(_file "synthesize/Top.snr"
(_format text)
(_timespec "2024-05-06T11:30:23")
(_timespec "2024-05-07T10:47:45")
)
(_file "synthesize/snr.db"
(_format text)
(_timespec "2024-05-06T11:30:23")
(_timespec "2024-05-07T10:47:45")
)
)
)
@ -340,21 +340,21 @@
(_db_output
(_file "device_map/Top_map.adf"
(_format adif)
(_timespec "2024-05-06T11:30:29")
(_timespec "2024-05-07T10:47:51")
)
)
(_output
(_file "device_map/Top_dmr.prt"
(_format text)
(_timespec "2024-05-06T11:30:27")
(_timespec "2024-05-07T10:47:48")
)
(_file "device_map/Top.dmr"
(_format text)
(_timespec "2024-05-06T11:30:29")
(_timespec "2024-05-07T10:47:51")
)
(_file "device_map/dmr.db"
(_format text)
(_timespec "2024-05-06T11:30:29")
(_timespec "2024-05-07T10:47:51")
)
)
)
@ -363,7 +363,7 @@
(_input
(_file "device_map/camera_light_src_timing_controller_fpga.pcf"
(_format pcf)
(_timespec "2024-05-06T11:30:29")
(_timespec "2024-05-07T10:47:51")
)
)
)
@ -378,33 +378,33 @@
(_db_output
(_file "place_route/Top_pnr.adf"
(_format adif)
(_timespec "2024-05-06T11:31:11")
(_timespec "2024-05-07T10:48:36")
)
)
(_output
(_file "place_route/Top.prr"
(_format text)
(_timespec "2024-05-06T11:31:11")
(_timespec "2024-05-07T10:48:37")
)
(_file "place_route/Top_prr.prt"
(_format text)
(_timespec "2024-05-06T11:31:11")
(_timespec "2024-05-07T10:48:36")
)
(_file "place_route/clock_utilization.txt"
(_format text)
(_timespec "2024-05-06T11:31:11")
(_timespec "2024-05-07T10:48:36")
)
(_file "place_route/Top_plc.adf"
(_format adif)
(_timespec "2024-05-06T11:30:40")
(_timespec "2024-05-07T10:48:06")
)
(_file "place_route/Top_pnr.netlist"
(_format text)
(_timespec "2024-05-06T11:31:11")
(_timespec "2024-05-07T10:48:37")
)
(_file "place_route/prr.db"
(_format text)
(_timespec "2024-05-06T11:31:12")
(_timespec "2024-05-07T10:48:37")
)
)
)
@ -439,19 +439,19 @@
(_output
(_file "generate_bitstream/Top.sbit"
(_format text)
(_timespec "2024-05-06T11:31:28")
(_timespec "2024-05-07T10:48:57")
)
(_file "generate_bitstream/Top.smsk"
(_format text)
(_timespec "2024-05-06T11:31:28")
(_timespec "2024-05-07T10:48:57")
)
(_file "generate_bitstream/Top.bgr"
(_format text)
(_timespec "2024-05-06T11:31:28")
(_timespec "2024-05-07T10:48:57")
)
(_file "generate_bitstream/bgr.db"
(_format text)
(_timespec "2024-05-06T11:31:28")
(_timespec "2024-05-07T10:48:58")
)
)
)

BIN
release/V7/Top.sbit
View File

BIN
release/V7/Top.sfc
View File

2
source/src/config.v
View File

@ -1,4 +1,4 @@
`define REGADDOFF__FPGA_VERSION 32'd6
`define REGADDOFF__FPGA_VERSION 32'd7
/*******************************************************************************
* 寄存器地址分配 *
*******************************************************************************/

46
source/src/top.v
View File

@ -214,7 +214,7 @@ module Top (
);
trigger_source_base_module #(
.REG_START_ADD (`REGADDOFF__INTERNAL_TRIGGER),
.REG_START_ADD(`REGADDOFF__INTERNAL_TRIGGER),
.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ),
.FREQ_DETECT_BIAS(0)
) internal_trigger_clk_trigger_source_base_module (
@ -258,7 +258,13 @@ module Top (
.out_trigger_sig_index0(sig_bus[`SIG_EXT_TRIGGER_1_I1]),
.out_trigger_sig_index1(sig_bus[`SIG_EXT_TRIGGER_1_I2]),
.out_trigger_sig_index2(sig_bus[`SIG_EXT_TRIGGER_1_I3]),
.out_trigger_sig_index3(sig_bus[`SIG_EXT_TRIGGER_1_I4])
.out_trigger_sig_index3(sig_bus[`SIG_EXT_TRIGGER_1_I4]),
.debug_sig_0(trigger_1_debug_sig_0),
.debug_sig_1(trigger_1_debug_sig_1),
.debug_sig_2(trigger_1_debug_sig_2)
);
@ -491,27 +497,25 @@ module Top (
.optocoupler_out(optocoupler_out4)
);
assign debug_bus[0] = diff_in1;
assign debug_bus[1] = optocoupler_in1;
assign debug_bus[2] = diff_in2;
assign debug_bus[3] = optocoupler_in2;
assign debug_bus[4] = diff_in3;
assign debug_bus[5] = optocoupler_in3;
assign debug_bus[6] = diff_in4;
assign debug_bus[7] = optocoupler_in4;
assign debug_bus[8] = sig_bus[`SIG_EXT_TRIGGER_1];
assign debug_bus[9] = sig_bus[`SIG_EXT_TRIGGER_2];
assign debug_bus[10] = sig_bus[`SIG_EXT_TRIGGER_3];
assign debug_bus[11] = sig_bus[`SIG_EXT_TRIGGER_4];
assign debug_bus[12] = diff_out1;
assign debug_bus[13] = diff_out2;
assign debug_bus[14] = diff_out3;
assign debug_bus[15] = diff_out4;
assign debug_bus[0] = sig_bus[`SIG_INTERNAL_CLK];
assign debug_bus[1] = sig_bus[`SIG_EXT_TRIGGER_1];
assign debug_bus[2] = sig_bus[`SIG_EXT_TRIGGER_2];
assign debug_bus[3] = sig_bus[`SIG_EXT_TRIGGER_3];
assign debug_bus[4] = sig_bus[`SIG_EXT_TRIGGER_4];
assign debug_bus[5] = lt1_en;
assign debug_bus[6] = lt2_en;
assign debug_bus[7] = lt3_en;
assign debug_bus[8] = lt4_en;
assign debug_bus[9] = optocoupler_out1;
assign debug_bus[10] = optocoupler_out2;
assign debug_bus[11] = optocoupler_out3;
assign debug_bus[12] = optocoupler_out4;
assign debug_bus[13] = lt1_intensity_ctrl;
assign debug_bus[14] = lt2_intensity_ctrl;
assign debug_bus[15] = lt3_intensity_ctrl;
// assign debug_bus[0] = sys_clk;

12
source/src/trigger_source/trigger_source_base_module.v
View File

@ -1,6 +1,6 @@
`include "../config.v"
module trigger_source_base_module #(
parameter REG_START_ADD = 0,
parameter REG_START_ADD = 0,
parameter SYS_CLOCK_FREQ = 100000000,
parameter FREQ_DETECT_BIAS = `FREQ_DETECT_BIAS_DEFAULT
) (
@ -21,7 +21,11 @@ module trigger_source_base_module #(
output reg out_trigger_sig_index0,
output reg out_trigger_sig_index1,
output reg out_trigger_sig_index2,
output reg out_trigger_sig_index3
output reg out_trigger_sig_index3,
output wire debug_sig_0,
output wire debug_sig_1,
output wire debug_sig_2
);
//
@ -213,6 +217,8 @@ module trigger_source_base_module #(
end
end
assign debug_sig_0 = sig_af_choose;
assign debug_sig_1 = sig_af_choose_af_filter;
assign debug_sig_2 = signal_out_final;
endmodule

38
source/src/zutils/zsimple_pluse_generator.v
View File

@ -14,10 +14,41 @@ module zsimple_pluse_generator (
reg [31:0] gen_pluse_cnt;
reg [31:0] cnt;
reg workflag;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
outsignal <= 0;
cnt <= 0;
_insignal_duty_cnt <= 0;
_freq_multiplication <= 0;
end else begin
if (insignal) begin
_insignal_duty_cnt <= insignal_duty_cnt;
_freq_multiplication <= freq_multiplication;
outsignal <= 1;
cnt <= 0;
gen_pluse_cnt <= 1;
end else begin
if (gen_pluse_cnt > _freq_multiplication) begin
outsignal <= 0;
end else begin
if (cnt >= _insignal_duty_cnt) begin
outsignal <= 1;
gen_pluse_cnt <= gen_pluse_cnt + 1;
end else begin
outsignal <= 0;
cnt <= cnt + _freq_multiplication + 1;
end
end
end
end
end
/*
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
workflag <= 0;
end else begin
if (insignal) begin
@ -37,6 +68,7 @@ module zsimple_pluse_generator (
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
cnt <= 0;
gen_pluse_cnt <= 0;
end else begin
if (workflag & !insignal) begin
if (cnt > _insignal_duty_cnt) begin
@ -57,14 +89,14 @@ module zsimple_pluse_generator (
if (!rst_n) begin
outsignal <= 0;
end else begin
if (cnt == _freq_multiplication + 1) begin
if (cnt == _freq_multiplication + 1+_freq_multiplication + 1) begin
outsignal <= 1;
end else begin
outsignal <= 0;
end
end
end
*/

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