diff --git a/README.md b/README.md
index b4ff7ae..b1b119a 100644
--- a/README.md
+++ b/README.md
@@ -5,6 +5,8 @@
 ```
 
 ```
+    V9:
+        1.修复PL无法2+倍频的BUG
     V7:
         1.修复PLL的BUG
     V6: 
diff --git a/camera_light_src_timing_controller_fpga.pds b/camera_light_src_timing_controller_fpga.pds
index 0455821..64a051e 100644
--- a/camera_light_src_timing_controller_fpga.pds
+++ b/camera_light_src_timing_controller_fpga.pds
@@ -1,5 +1,5 @@
 (_flow fab_demo "2021.1-SP7"
-    (_comment "Generated by Fabric Compiler (version on 2021.1-SP7<build 86875>) at Tue May  7 11:00:42 2024")
+    (_comment "Generated by Fabric Compiler (version on 2021.1-SP7<build 86875>) at Fri May 10 14:08:59 2024")
     (_version "1.0.5")
     (_status "initial")
     (_project 
@@ -19,7 +19,7 @@
             (_input
                 (_file "source/src/top.v" + "Top:"
                     (_format verilog)
-                    (_timespec "2024-05-07T10:58:09")
+                    (_timespec "2024-05-10T14:05:07")
                 )
                 (_file "source/src/spi_reg_reader.v"
                     (_format verilog)
@@ -187,7 +187,7 @@
                 )
                 (_file "source/src/trigger_source/trigger_source_base_module.v"
                     (_format verilog)
-                    (_timespec "2024-05-07T09:51:52")
+                    (_timespec "2024-05-10T11:58:19")
                 )
                 (_file "source/src/output/light_src_ctrl.v"
                     (_format verilog)
@@ -207,7 +207,7 @@
                 )
                 (_file "source/src/zutils/zsimple_pluse_generator.v"
                     (_format verilog)
-                    (_timespec "2024-05-07T10:36:44")
+                    (_timespec "2024-05-10T14:03:35")
                 )
             )
         )
@@ -279,17 +279,17 @@
             (_db_output
                 (_file "compile/Top_comp.adf"
                     (_format adif)
-                    (_timespec "2024-05-07T10:58:33")
+                    (_timespec "2024-05-10T14:07:34")
                 )
             )
             (_output
                 (_file "compile/Top.cmr"
                     (_format verilog)
-                    (_timespec "2024-05-07T10:58:30")
+                    (_timespec "2024-05-10T14:07:32")
                 )
                 (_file "compile/cmr.db"
                     (_format text)
-                    (_timespec "2024-05-07T10:58:33")
+                    (_timespec "2024-05-10T14:07:34")
                 )
             )
         )
@@ -305,21 +305,21 @@
             (_db_output
                 (_file "synthesize/Top_syn.adf"
                     (_format adif)
-                    (_timespec "2024-05-07T10:58:57")
+                    (_timespec "2024-05-10T14:07:53")
                 )
             )
             (_output
                 (_file "synthesize/Top_syn.vm"
                     (_format structural_verilog)
-                    (_timespec "2024-05-07T10:58:59")
+                    (_timespec "2024-05-10T14:07:54")
                 )
                 (_file "synthesize/Top.snr"
                     (_format text)
-                    (_timespec "2024-05-07T10:59:01")
+                    (_timespec "2024-05-10T14:07:55")
                 )
                 (_file "synthesize/snr.db"
                     (_format text)
-                    (_timespec "2024-05-07T10:59:01")
+                    (_timespec "2024-05-10T14:07:55")
                 )
             )
         )
@@ -340,21 +340,21 @@
             (_db_output
                 (_file "device_map/Top_map.adf"
                     (_format adif)
-                    (_timespec "2024-05-07T10:59:07")
+                    (_timespec "2024-05-10T14:08:02")
                 )
             )
             (_output
                 (_file "device_map/Top_dmr.prt"
                     (_format text)
-                    (_timespec "2024-05-07T10:59:04")
+                    (_timespec "2024-05-10T14:08:00")
                 )
                 (_file "device_map/Top.dmr"
                     (_format text)
-                    (_timespec "2024-05-07T10:59:07")
+                    (_timespec "2024-05-10T14:08:02")
                 )
                 (_file "device_map/dmr.db"
                     (_format text)
-                    (_timespec "2024-05-07T10:59:07")
+                    (_timespec "2024-05-10T14:08:02")
                 )
             )
         )
@@ -363,7 +363,7 @@
             (_input
                 (_file "device_map/camera_light_src_timing_controller_fpga.pcf"
                     (_format pcf)
-                    (_timespec "2024-05-07T10:59:07")
+                    (_timespec "2024-05-10T14:08:02")
                 )
             )
         )
@@ -378,33 +378,33 @@
             (_db_output
                 (_file "place_route/Top_pnr.adf"
                     (_format adif)
-                    (_timespec "2024-05-07T11:00:20")
+                    (_timespec "2024-05-10T14:08:41")
                 )
             )
             (_output
                 (_file "place_route/Top.prr"
                     (_format text)
-                    (_timespec "2024-05-07T11:00:20")
+                    (_timespec "2024-05-10T14:08:41")
                 )
                 (_file "place_route/Top_prr.prt"
                     (_format text)
-                    (_timespec "2024-05-07T11:00:19")
+                    (_timespec "2024-05-10T14:08:41")
                 )
                 (_file "place_route/clock_utilization.txt"
                     (_format text)
-                    (_timespec "2024-05-07T11:00:19")
+                    (_timespec "2024-05-10T14:08:41")
                 )
                 (_file "place_route/Top_plc.adf"
                     (_format adif)
-                    (_timespec "2024-05-07T10:59:36")
+                    (_timespec "2024-05-10T14:08:13")
                 )
                 (_file "place_route/Top_pnr.netlist"
                     (_format text)
-                    (_timespec "2024-05-07T11:00:20")
+                    (_timespec "2024-05-10T14:08:41")
                 )
                 (_file "place_route/prr.db"
                     (_format text)
-                    (_timespec "2024-05-07T11:00:20")
+                    (_timespec "2024-05-10T14:08:41")
                 )
             )
         )
@@ -439,19 +439,19 @@
             (_output
                 (_file "generate_bitstream/Top.sbit"
                     (_format text)
-                    (_timespec "2024-05-07T11:00:41")
+                    (_timespec "2024-05-10T14:08:58")
                 )
                 (_file "generate_bitstream/Top.smsk"
                     (_format text)
-                    (_timespec "2024-05-07T11:00:41")
+                    (_timespec "2024-05-10T14:08:58")
                 )
                 (_file "generate_bitstream/Top.bgr"
                     (_format text)
-                    (_timespec "2024-05-07T11:00:41")
+                    (_timespec "2024-05-10T14:08:58")
                 )
                 (_file "generate_bitstream/bgr.db"
                     (_format text)
-                    (_timespec "2024-05-07T11:00:41")
+                    (_timespec "2024-05-10T14:08:59")
                 )
             )
         )
diff --git a/release/V9/Top.sbit b/release/V9/Top.sbit
new file mode 100644
index 0000000..0e34dae
Binary files /dev/null and b/release/V9/Top.sbit differ
diff --git a/release/V9/Top.sfc b/release/V9/Top.sfc
new file mode 100644
index 0000000..d8907cd
Binary files /dev/null and b/release/V9/Top.sfc differ
diff --git a/source/src/config.v b/source/src/config.v
index 5ec87f9..b9b6db0 100644
--- a/source/src/config.v
+++ b/source/src/config.v
@@ -1,4 +1,4 @@
-`define REGADDOFF__FPGA_VERSION 32'd8
+`define REGADDOFF__FPGA_VERSION 32'd9
 /*******************************************************************************
  *                               寄存器地址分配                                *
  *******************************************************************************/
diff --git a/source/src/top.v b/source/src/top.v
index c77e368..b5c7088 100644
--- a/source/src/top.v
+++ b/source/src/top.v
@@ -251,8 +251,9 @@ module Top (
       .wr_en  (RegReaderBus_wr_en),
       .rd_data(rd_data_trigger_in1),
 
-      .in_sig_0(!optocoupler_in1),
-      .in_sig_1(diff_in1),
+      .in_sig_0       (!optocoupler_in1),
+      .in_sig_1       (diff_in1),
+      .in_sig_selected(trigger_in_selected_1),
 
       .out_trigger_sig       (sig_bus[`SIG_EXT_TRIGGER_1]),
       .out_trigger_sig_index0(sig_bus[`SIG_EXT_TRIGGER_1_I1]),
@@ -281,8 +282,9 @@ module Top (
       .wr_en  (RegReaderBus_wr_en),
       .rd_data(rd_data_trigger_in2),
 
-      .in_sig_0(!optocoupler_in2),
-      .in_sig_1(diff_in2),
+      .in_sig_0       (!optocoupler_in2),
+      .in_sig_1       (diff_in2),
+      .in_sig_selected(trigger_in_selected_2),
 
       .out_trigger_sig       (sig_bus[`SIG_EXT_TRIGGER_2]),
       .out_trigger_sig_index0(sig_bus[`SIG_EXT_TRIGGER_2_I1]),
@@ -303,8 +305,10 @@ module Top (
       .wr_en  (RegReaderBus_wr_en),
       .rd_data(rd_data_trigger_in3),
 
-      .in_sig_0(!optocoupler_in3),
-      .in_sig_1(diff_in3),
+      .in_sig_0       (!optocoupler_in3),
+      .in_sig_1       (diff_in3),
+      .in_sig_selected(trigger_in_selected_3),
+
 
       .out_trigger_sig       (sig_bus[`SIG_EXT_TRIGGER_3]),
       .out_trigger_sig_index0(sig_bus[`SIG_EXT_TRIGGER_3_I1]),
@@ -325,8 +329,9 @@ module Top (
       .wr_en  (RegReaderBus_wr_en),
       .rd_data(rd_data_trigger_in4),
 
-      .in_sig_0(!optocoupler_in4),
-      .in_sig_1(diff_in4),
+      .in_sig_0       (!optocoupler_in4),
+      .in_sig_1       (diff_in4),
+      .in_sig_selected(trigger_in_selected_4),
 
       .out_trigger_sig       (sig_bus[`SIG_EXT_TRIGGER_4]),
       .out_trigger_sig_index0(sig_bus[`SIG_EXT_TRIGGER_4_I1]),
@@ -497,22 +502,21 @@ module Top (
       .optocoupler_out(optocoupler_out4)
   );
 
-  assign debug_bus[0]  = diff_in1;
-  assign debug_bus[1]  = optocoupler_in1;
-  assign debug_bus[2]  = sig_bus[`SIG_EXT_TRIGGER_1];
 
-  assign debug_bus[3]  = diff_in2;
-  assign debug_bus[4]  = optocoupler_in2;
-  assign debug_bus[5]  = sig_bus[`SIG_EXT_TRIGGER_2];
+  assign debug_bus[0]  = trigger_in_selected_1;
+  assign debug_bus[1]  = sig_bus[`SIG_EXT_TRIGGER_1];
+  assign debug_bus[2]  = trigger_in_selected_2;
+  assign debug_bus[3]  = sig_bus[`SIG_EXT_TRIGGER_2];
+  assign debug_bus[4]  = trigger_in_selected_3;
+  assign debug_bus[5]  = sig_bus[`SIG_EXT_TRIGGER_3];
+  assign debug_bus[6]  = trigger_in_selected_4;
+  assign debug_bus[7]  = sig_bus[`SIG_EXT_TRIGGER_4];
+  assign debug_bus[8]  = lt1_intensity_ctrl;
+  assign debug_bus[9]  = lt2_intensity_ctrl;
+  assign debug_bus[10] = lt3_intensity_ctrl;
+  assign debug_bus[11] = lt4_intensity_ctrl;
 
-  assign debug_bus[6]  = diff_in3;
-  assign debug_bus[7]  = optocoupler_in3;
-  assign debug_bus[8] = sig_bus[`SIG_EXT_TRIGGER_3];
 
-  assign debug_bus[9]  = diff_in4;
-  assign debug_bus[10]  = optocoupler_in4;
-  assign debug_bus[11] = sig_bus[`SIG_EXT_TRIGGER_4];
-  
   assign debug_bus[12] = diff_out1;
   assign debug_bus[13] = diff_out2;
   assign debug_bus[14] = diff_out3;
diff --git a/source/src/trigger_source/trigger_source_base_module.v b/source/src/trigger_source/trigger_source_base_module.v
index da8853c..a791b92 100644
--- a/source/src/trigger_source/trigger_source_base_module.v
+++ b/source/src/trigger_source/trigger_source_base_module.v
@@ -16,6 +16,7 @@ module trigger_source_base_module #(
     //
     input wire in_sig_0,
     input wire in_sig_1,
+    output wire in_sig_selected,
 
     output wire out_trigger_sig,
     output reg  out_trigger_sig_index0,
@@ -123,6 +124,8 @@ module trigger_source_base_module #(
   wire sig_af_choose_af_filter_af_pll;  //!PLL后的脉冲
   reg  signal_out_final;  //!最终输出的信号
 
+  assign in_sig_selected = sig_af_choose;
+
   always @(*) begin
     if (reg1_src_slect <= 3) begin
       sig_af_choose = in_sig[reg1_src_slect];
diff --git a/source/src/zutils/zsimple_pluse_generator.v b/source/src/zutils/zsimple_pluse_generator.v
index 36fb204..8a95fef 100644
--- a/source/src/zutils/zsimple_pluse_generator.v
+++ b/source/src/zutils/zsimple_pluse_generator.v
@@ -26,7 +26,7 @@ module zsimple_pluse_generator (
         _insignal_duty_cnt   <= insignal_duty_cnt;
         _freq_multiplication <= freq_multiplication;
         outsignal            <= 1;
-        cnt                  <= 0;
+        cnt                  <= _freq_multiplication + 1;
         gen_pluse_cnt        <= 1;
       end else begin
         if (gen_pluse_cnt > _freq_multiplication) begin
@@ -35,6 +35,7 @@ module zsimple_pluse_generator (
           if (cnt >= _insignal_duty_cnt) begin
             outsignal     <= 1;
             gen_pluse_cnt <= gen_pluse_cnt + 1;
+            cnt           <= _freq_multiplication + 1;
           end else begin
             outsignal <= 0;
             cnt       <= cnt + _freq_multiplication + 1;