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syncbox16ch_fpga
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update

master
zhaohe 1 year ago
parent
a66de49e50
commit
2af77e0db1
5 changed files with 235 additions and 239 deletions
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  1. 4
      camera_light_src_timing_controller_fpga.fdc
  2. 64
      camera_light_src_timing_controller_fpga.pds
  3. 4
      pin.csv
  4. 0
      source/src/output/light_src_ctrl.v

4
camera_light_src_timing_controller_fpga.fdc
View File

@ -21,13 +21,13 @@ define_attribute {p:spi_rx_pin} {PAP_IO_LOC} {R18}
define_attribute {p:spi_rx_pin} {PAP_IO_VCCIO} {3.3} define_attribute {p:spi_rx_pin} {PAP_IO_VCCIO} {3.3}
define_attribute {p:spi_rx_pin} {PAP_IO_STANDARD} {LVTTL33} define_attribute {p:spi_rx_pin} {PAP_IO_STANDARD} {LVTTL33}
define_attribute {p:uart_tx} {PAP_IO_DIRECTION} {OUTPUT} define_attribute {p:uart_tx} {PAP_IO_DIRECTION} {OUTPUT}
define_attribute {p:uart_tx} {PAP_IO_LOC} {L18}
define_attribute {p:uart_tx} {PAP_IO_LOC} {L17}
define_attribute {p:uart_tx} {PAP_IO_VCCIO} {3.3} define_attribute {p:uart_tx} {PAP_IO_VCCIO} {3.3}
define_attribute {p:uart_tx} {PAP_IO_STANDARD} {LVCMOS33} define_attribute {p:uart_tx} {PAP_IO_STANDARD} {LVCMOS33}
define_attribute {p:uart_tx} {PAP_IO_DRIVE} {4} define_attribute {p:uart_tx} {PAP_IO_DRIVE} {4}
define_attribute {p:uart_tx} {PAP_IO_SLEW} {SLOW} define_attribute {p:uart_tx} {PAP_IO_SLEW} {SLOW}
define_attribute {p:uart_rx} {PAP_IO_DIRECTION} {INPUT} define_attribute {p:uart_rx} {PAP_IO_DIRECTION} {INPUT}
define_attribute {p:uart_rx} {PAP_IO_LOC} {L17}
define_attribute {p:uart_rx} {PAP_IO_LOC} {L18}
define_attribute {p:uart_rx} {PAP_IO_VCCIO} {3.3} define_attribute {p:uart_rx} {PAP_IO_VCCIO} {3.3}
define_attribute {p:uart_rx} {PAP_IO_STANDARD} {LVTTL33} define_attribute {p:uart_rx} {PAP_IO_STANDARD} {LVTTL33}
define_attribute {p:core_board_debug_led} {PAP_IO_DIRECTION} {OUTPUT} define_attribute {p:core_board_debug_led} {PAP_IO_DIRECTION} {OUTPUT}

64
camera_light_src_timing_controller_fpga.pds
View File

@ -1,5 +1,5 @@
(_flow fab_demo "2021.1-SP7" (_flow fab_demo "2021.1-SP7"
(_comment "Generated by Fabric Compiler (version on 2021.1-SP7<build 86875>) at Sun Mar 10 11:54:51 2024")
(_comment "Generated by Fabric Compiler (version on 2021.1-SP7<build 86875>) at Sun Mar 10 12:19:08 2024")
(_version "1.0.5") (_version "1.0.5")
(_status "initial") (_status "initial")
(_project (_project
@ -57,10 +57,6 @@
(_format verilog) (_format verilog)
(_timespec "2024-03-08T21:15:01") (_timespec "2024-03-08T21:15:01")
) )
(_file "source/src/output/ttl_output.v"
(_format verilog)
(_timespec "2024-03-08T21:15:01")
)
(_file "source/src/zutils/zutils_pwm_generator.v" (_file "source/src/zutils/zutils_pwm_generator.v"
(_format verilog) (_format verilog)
(_timespec "2024-03-08T21:15:01") (_timespec "2024-03-08T21:15:01")
@ -216,7 +212,7 @@
(_input (_input
(_file "camera_light_src_timing_controller_fpga.fdc" (_file "camera_light_src_timing_controller_fpga.fdc"
(_format fdc) (_format fdc)
(_timespec "2024-03-08T22:52:15")
(_timespec "2024-03-10T12:18:07")
) )
) )
) )
@ -263,21 +259,21 @@
) )
(_task tsk_compile (_task tsk_compile
(_command cmd_compile (_command cmd_compile
(_gci_state (_integer 3))
(_gci_state (_integer 2))
(_db_output (_db_output
(_file "compile/Top_comp.adf" (_file "compile/Top_comp.adf"
(_format adif) (_format adif)
(_timespec "2024-03-10T11:41:33")
(_timespec "2024-03-10T12:18:42")
) )
) )
(_output (_output
(_file "compile/Top.cmr" (_file "compile/Top.cmr"
(_format verilog) (_format verilog)
(_timespec "2024-03-10T11:41:33")
(_timespec "2024-03-10T12:18:42")
) )
(_file "compile/cmr.db" (_file "compile/cmr.db"
(_format text) (_format text)
(_timespec "2024-03-10T11:41:33")
(_timespec "2024-03-10T12:18:42")
) )
) )
) )
@ -287,27 +283,27 @@
) )
(_task tsk_synthesis (_task tsk_synthesis
(_command cmd_synthesize (_command cmd_synthesize
(_gci_state (_integer 3))
(_gci_state (_integer 2))
(_option ads (_switch ON)) (_option ads (_switch ON))
(_option selected_syn_tool_opt (_integer 2)) (_option selected_syn_tool_opt (_integer 2))
(_db_output (_db_output
(_file "synthesize/Top_syn.adf" (_file "synthesize/Top_syn.adf"
(_format adif) (_format adif)
(_timespec "2024-03-10T11:41:40")
(_timespec "2024-03-10T12:18:49")
) )
) )
(_output (_output
(_file "synthesize/Top_syn.vm" (_file "synthesize/Top_syn.vm"
(_format structural_verilog) (_format structural_verilog)
(_timespec "2024-03-10T11:41:40")
(_timespec "2024-03-10T12:18:49")
) )
(_file "synthesize/Top.snr" (_file "synthesize/Top.snr"
(_format text) (_format text)
(_timespec "2024-03-10T11:41:40")
(_timespec "2024-03-10T12:18:49")
) )
(_file "synthesize/snr.db" (_file "synthesize/snr.db"
(_format text) (_format text)
(_timespec "2024-03-10T11:41:40")
(_timespec "2024-03-10T12:18:49")
) )
) )
) )
@ -324,25 +320,25 @@
) )
(_task tsk_devmap (_task tsk_devmap
(_command cmd_devmap (_command cmd_devmap
(_gci_state (_integer 3))
(_gci_state (_integer 2))
(_db_output (_db_output
(_file "device_map/Top_map.adf" (_file "device_map/Top_map.adf"
(_format adif) (_format adif)
(_timespec "2024-03-10T11:41:43")
(_timespec "2024-03-10T12:18:52")
) )
) )
(_output (_output
(_file "device_map/Top_dmr.prt" (_file "device_map/Top_dmr.prt"
(_format text) (_format text)
(_timespec "2024-03-10T11:41:42")
(_timespec "2024-03-10T12:18:52")
) )
(_file "device_map/Top.dmr" (_file "device_map/Top.dmr"
(_format text) (_format text)
(_timespec "2024-03-10T11:41:43")
(_timespec "2024-03-10T12:18:52")
) )
(_file "device_map/dmr.db" (_file "device_map/dmr.db"
(_format text) (_format text)
(_timespec "2024-03-10T11:41:43")
(_timespec "2024-03-10T12:18:52")
) )
) )
) )
@ -351,7 +347,7 @@
(_input (_input
(_file "device_map/camera_light_src_timing_controller_fpga.pcf" (_file "device_map/camera_light_src_timing_controller_fpga.pcf"
(_format pcf) (_format pcf)
(_timespec "2024-03-10T11:41:43")
(_timespec "2024-03-10T12:18:52")
) )
) )
) )
@ -361,38 +357,38 @@
) )
(_task tsk_pnr (_task tsk_pnr
(_command cmd_pnr (_command cmd_pnr
(_gci_state (_integer 3))
(_gci_state (_integer 2))
(_option mode (_string "fast")) (_option mode (_string "fast"))
(_db_output (_db_output
(_file "place_route/Top_pnr.adf" (_file "place_route/Top_pnr.adf"
(_format adif) (_format adif)
(_timespec "2024-03-10T11:41:51")
(_timespec "2024-03-10T12:19:00")
) )
) )
(_output (_output
(_file "place_route/Top.prr" (_file "place_route/Top.prr"
(_format text) (_format text)
(_timespec "2024-03-10T11:41:51")
(_timespec "2024-03-10T12:19:00")
) )
(_file "place_route/Top_prr.prt" (_file "place_route/Top_prr.prt"
(_format text) (_format text)
(_timespec "2024-03-10T11:41:50")
(_timespec "2024-03-10T12:19:00")
) )
(_file "place_route/clock_utilization.txt" (_file "place_route/clock_utilization.txt"
(_format text) (_format text)
(_timespec "2024-03-10T11:41:50")
(_timespec "2024-03-10T12:19:00")
) )
(_file "place_route/Top_plc.adf" (_file "place_route/Top_plc.adf"
(_format adif) (_format adif)
(_timespec "2024-03-10T11:41:47")
(_timespec "2024-03-10T12:18:57")
) )
(_file "place_route/Top_pnr.netlist" (_file "place_route/Top_pnr.netlist"
(_format text) (_format text)
(_timespec "2024-03-10T11:41:51")
(_timespec "2024-03-10T12:19:00")
) )
(_file "place_route/prr.db" (_file "place_route/prr.db"
(_format text) (_format text)
(_timespec "2024-03-10T11:41:51")
(_timespec "2024-03-10T12:19:00")
) )
) )
) )
@ -423,23 +419,23 @@
) )
(_task tsk_gen_bitstream (_task tsk_gen_bitstream
(_command cmd_gen_bitstream (_command cmd_gen_bitstream
(_gci_state (_integer 3))
(_gci_state (_integer 2))
(_output (_output
(_file "generate_bitstream/Top.sbit" (_file "generate_bitstream/Top.sbit"
(_format text) (_format text)
(_timespec "2024-03-10T11:41:58")
(_timespec "2024-03-10T12:19:08")
) )
(_file "generate_bitstream/Top.smsk" (_file "generate_bitstream/Top.smsk"
(_format text) (_format text)
(_timespec "2024-03-10T11:41:58")
(_timespec "2024-03-10T12:19:08")
) )
(_file "generate_bitstream/Top.bgr" (_file "generate_bitstream/Top.bgr"
(_format text) (_format text)
(_timespec "2024-03-10T11:41:58")
(_timespec "2024-03-10T12:19:08")
) )
(_file "generate_bitstream/bgr.db" (_file "generate_bitstream/bgr.db"
(_format text) (_format text)
(_timespec "2024-03-10T11:41:59")
(_timespec "2024-03-10T12:19:08")
) )
) )
) )

4
pin.csv
View File

@ -4,8 +4,8 @@ P17,spi_cs_pin ,INPUT
L12,spi_clk_pin,INPUT L12,spi_clk_pin,INPUT
R17,spi_tx_pin,OUTPUT R17,spi_tx_pin,OUTPUT
R18,spi_rx_pin,INPUT R18,spi_rx_pin,INPUT
L18,uart_tx,OUTPUT
L17,uart_rx,INPUT
L17,uart_tx,OUTPUT
L18,uart_rx,INPUT
T11,core_board_debug_led,OUTPUT T11,core_board_debug_led,OUTPUT
M16,id[0],INPUT M16,id[0],INPUT
L16,id[1],INPUT L16,id[1],INPUT

0
source/src/output/ttl_output.v → source/src/output/light_src_ctrl.v
View File

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