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syncbox16ch_fpga
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zhaohe 1 year ago
parent
6e6d9efdb9
commit
2fd941e3fc
7 changed files with 130 additions and 194 deletions
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  1. 118
      camera_light_src_timing_controller_fpga.pds
  2. BIN
      cfg_verify_result.sbit
  3. 4
      source/src/config.v
  4. 42
      source/src/output/light_src_ctrl.v
  5. 21
      source/src/output/ttl_output_ctrl.v
  6. 129
      source/src/top.v
  7. 10
      source/src/trigger_source/internal_trigger_clk.v

118
camera_light_src_timing_controller_fpga.pds
View File

@ -1,5 +1,5 @@
(_flow fab_demo "2021.1-SP7"
(_comment "Generated by Fabric Compiler (version on 2021.1-SP7<build 86875>) at Sun Mar 10 23:34:39 2024")
(_comment "Generated by Fabric Compiler (version on 2021.1-SP7<build 86875>) at Mon Mar 11 15:28:46 2024")
(_version "1.0.5")
(_status "initial")
(_project
@ -19,7 +19,7 @@
(_input
(_file "source/src/top.v" + "Top:"
(_format verilog)
(_timespec "2024-03-10T23:27:42")
(_timespec "2024-03-11T14:22:56")
)
(_file "source/src/spi_reg_reader.v"
(_format verilog)
@ -183,7 +183,7 @@
)
(_file "source/src/trigger_source/internal_trigger_clk.v"
(_format verilog)
(_timespec "2024-03-10T19:03:17")
(_timespec "2024-03-11T00:09:16")
)
(_file "source/src/zutils/zutils_trigger_sig_gen.v"
(_format verilog)
@ -195,11 +195,11 @@
)
(_file "source/src/output/light_src_ctrl.v"
(_format verilog)
(_timespec "2024-03-10T23:34:38")
(_timespec "2024-03-11T09:38:33")
)
(_file "source/src/output/ttl_output_ctrl.v"
(_format verilog)
(_timespec "2024-03-10T22:41:52")
(_timespec "2024-03-11T15:28:29")
)
(_file "source/src/zutils/zutils_pluse_generator_v2.v"
(_format verilog)
@ -275,21 +275,21 @@
)
(_task tsk_compile
(_command cmd_compile
(_gci_state (_integer 3))
(_gci_state (_integer 2))
(_db_output
(_file "compile/Top_comp.adf"
(_format adif)
(_timespec "2024-03-10T23:27:55")
(_timespec "2024-03-11T15:28:45")
)
)
(_output
(_file "compile/Top.cmr"
(_format verilog)
(_timespec "2024-03-10T23:27:53")
(_timespec "2024-03-11T15:28:43")
)
(_file "compile/cmr.db"
(_format text)
(_timespec "2024-03-10T23:27:55")
(_timespec "2024-03-11T15:28:45")
)
)
)
@ -299,29 +299,9 @@
)
(_task tsk_synthesis
(_command cmd_synthesize
(_gci_state (_integer 3))
(_gci_state (_integer 0))
(_option ads (_switch ON))
(_option selected_syn_tool_opt (_integer 2))
(_db_output
(_file "synthesize/Top_syn.adf"
(_format adif)
(_timespec "2024-03-10T23:28:09")
)
)
(_output
(_file "synthesize/Top_syn.vm"
(_format structural_verilog)
(_timespec "2024-03-10T23:28:10")
)
(_file "synthesize/Top.snr"
(_format text)
(_timespec "2024-03-10T23:28:10")
)
(_file "synthesize/snr.db"
(_format text)
(_timespec "2024-03-10T23:28:10")
)
)
)
(_widget wgt_tech_view
(_attribute _click_to_run (_switch ON))
@ -336,34 +316,14 @@
)
(_task tsk_devmap
(_command cmd_devmap
(_gci_state (_integer 3))
(_db_output
(_file "device_map/Top_map.adf"
(_format adif)
(_timespec "2024-03-10T23:28:14")
)
)
(_output
(_file "device_map/Top_dmr.prt"
(_format text)
(_timespec "2024-03-10T23:28:13")
)
(_file "device_map/Top.dmr"
(_format text)
(_timespec "2024-03-10T23:28:14")
)
(_file "device_map/dmr.db"
(_format text)
(_timespec "2024-03-10T23:28:14")
)
)
(_gci_state (_integer 0))
)
(_widget wgt_edit_placement_cons
(_attribute _click_to_run (_switch ON))
(_input
(_file "device_map/camera_light_src_timing_controller_fpga.pcf"
(_format pcf)
(_timespec "2024-03-10T23:28:14")
(_timespec "2024-03-11T14:25:50")
)
)
)
@ -373,40 +333,8 @@
)
(_task tsk_pnr
(_command cmd_pnr
(_gci_state (_integer 3))
(_gci_state (_integer 0))
(_option mode (_string "fast"))
(_db_output
(_file "place_route/Top_pnr.adf"
(_format adif)
(_timespec "2024-03-10T23:28:45")
)
)
(_output
(_file "place_route/Top.prr"
(_format text)
(_timespec "2024-03-10T23:28:45")
)
(_file "place_route/Top_prr.prt"
(_format text)
(_timespec "2024-03-10T23:28:44")
)
(_file "place_route/clock_utilization.txt"
(_format text)
(_timespec "2024-03-10T23:28:44")
)
(_file "place_route/Top_plc.adf"
(_format adif)
(_timespec "2024-03-10T23:28:21")
)
(_file "place_route/Top_pnr.netlist"
(_format text)
(_timespec "2024-03-10T23:28:45")
)
(_file "place_route/prr.db"
(_format text)
(_timespec "2024-03-10T23:28:46")
)
)
)
(_widget wgt_power_calculator
(_attribute _click_to_run (_switch ON))
@ -435,25 +363,7 @@
)
(_task tsk_gen_bitstream
(_command cmd_gen_bitstream
(_gci_state (_integer 3))
(_output
(_file "generate_bitstream/Top.sbit"
(_format text)
(_timespec "2024-03-10T23:29:07")
)
(_file "generate_bitstream/Top.smsk"
(_format text)
(_timespec "2024-03-10T23:29:07")
)
(_file "generate_bitstream/Top.bgr"
(_format text)
(_timespec "2024-03-10T23:29:07")
)
(_file "generate_bitstream/bgr.db"
(_format text)
(_timespec "2024-03-10T23:29:08")
)
)
(_gci_state (_integer 0))
)
)
)

BIN
cfg_verify_result.sbit
View File

4
source/src/config.v
View File

@ -1,4 +1,4 @@
`define REGADDOFF__FPGA_VERSION 32'd1
`define REGADDOFF__FPGA_VERSION 32'd2
/*******************************************************************************
* 寄存器地址分配 *
*******************************************************************************/
@ -25,7 +25,7 @@
/*******************************************************************************
* 部分寄存器初始化数值 *
*******************************************************************************/
`define FREQ_DETECT_BIAS_DEFAULT 32'd10
`define FREQ_DETECT_BIAS_DEFAULT 32'd100
`define FREQ_TTL_INPUT_FILTER 32'd10
/*******************************************************************************

42
source/src/output/light_src_ctrl.v
View File

@ -93,17 +93,17 @@ module light_src_ctrl #(
end else begin
if (reg_wr_sig) begin
case (reg_wr_index)
32'h1: reg1_source_select <= reg_wr_index;
32'h2: reg2_en_sig_ctrl_mode <= reg_wr_index;
32'h3: reg3_light_intensity_ctrl_mode <= reg_wr_index;
32'h4: reg4_trigger_mode_pluse_num <= reg_wr_index;
32'h5: reg5_trigger_mode_pluse_interval <= reg_wr_index;
32'h6: reg6_trigger_mode_pluse_width <= reg_wr_index;
32'h7: reg7_trigger_mode_first_pluse_offset <= reg_wr_index;
32'h8: reg8_trigger_mode_output_polarity <= reg_wr_index;
32'h9: reg9_light_intensity_cnt <= reg_wr_index;
32'hA: regA_light_driver_freq_cnt <= reg_wr_index;
32'hC: regC_freq_detect_bias <= reg_wr_index;
32'h1: reg1_source_select <= wr_data;
32'h2: reg2_en_sig_ctrl_mode <= wr_data;
32'h3: reg3_light_intensity_ctrl_mode <= wr_data;
32'h4: reg4_trigger_mode_pluse_num <= wr_data;
32'h5: reg5_trigger_mode_pluse_interval <= wr_data;
32'h6: reg6_trigger_mode_pluse_width <= wr_data;
32'h7: reg7_trigger_mode_first_pluse_offset <= wr_data;
32'h8: reg8_trigger_mode_output_polarity <= wr_data;
32'h9: reg9_light_intensity_cnt <= wr_data;
32'hA: regA_light_driver_freq_cnt <= wr_data;
32'hC: regC_freq_detect_bias <= wr_data;
default: begin
end
endcase
@ -143,6 +143,7 @@ module light_src_ctrl #(
);
/*******************************************************************************
* 光源亮度信号发生器 *
*******************************************************************************/
@ -167,6 +168,25 @@ module light_src_ctrl #(
end
end
zutils_freq_detector_v2 freq_detector1 (
.clk (clk),
.rst_n (rst_n),
.freq_detect_bias(regC_freq_detect_bias),
.pluse_input (signal_in_choose),
.pluse_width_cnt (regE_in_sig_freq_detect)
);
zutils_freq_detector_v2 freq_detector2 (
.clk (clk),
.rst_n (rst_n),
.freq_detect_bias(regC_freq_detect_bias),
.pluse_input (signal_en_output),
.pluse_width_cnt (regF_out_sig_freq_detect)
);
assign lt_intensity_ctrl = signal_lt_intensity;
assign lt_en = signal_en_output;

21
source/src/output/ttl_output_ctrl.v
View File

@ -29,6 +29,7 @@ module ttl_output_ctrl #(
reg [31:0] reg2_lt_en_bind; //!绑定的光源信号
reg [31:0] reg3_lt_en_offset; //!快门信号与曝光信号偏移
reg [31:0] reg4_in_sig_select; //!转发模式下信号选择器
reg [31:0] reg5_bind_mode_output_polarity_reversal; //!转发模式下信号选择器
wire [31:0] reg_wr_index;
//!TTLOUT_寄存器自动赋值选择器
@ -54,17 +55,19 @@ module ttl_output_ctrl #(
//!寄存器写入逻辑
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
reg1_output_ctrl_mode <= `SIG_PROCESS_MODE__BIND_MODE;
reg2_lt_en_bind <= 32'hffff_ffff;
reg3_lt_en_offset <= (SYS_CLOCK_FREQ / 32'd1000_000); //1us
reg1_output_ctrl_mode <= `SIG_PROCESS_MODE__BIND_MODE;
reg2_lt_en_bind <= 32'hffff_ffff;
reg3_lt_en_offset <= (SYS_CLOCK_FREQ / 32'd1000_000); //1us
reg4_in_sig_select <= 0;
reg5_bind_mode_output_polarity_reversal <= 0;
end else begin
if (reg_wr_sig) begin
case (reg_wr_index)
32'h1: reg1_output_ctrl_mode <= reg_wr_index;
32'h2: reg2_lt_en_bind <= reg_wr_index;
32'h3: reg3_lt_en_offset <= reg_wr_index;
32'h4: reg4_in_sig_select <= reg_wr_index;
32'h1: reg1_output_ctrl_mode <= wr_data;
32'h2: reg2_lt_en_bind <= wr_data;
32'h3: reg3_lt_en_offset <= wr_data;
32'h4: reg4_in_sig_select <= wr_data;
32'h5: reg5_bind_mode_output_polarity_reversal <= wr_data;
default: begin
end
endcase
@ -125,7 +128,7 @@ module ttl_output_ctrl #(
always @(*) begin
case (reg1_output_ctrl_mode)
`SIG_PROCESS_MODE__BIND_MODE: output_sig <= output_sig_0 & trigger_sig;
`SIG_PROCESS_MODE__BIND_MODE: output_sig <= (output_sig_0 & trigger_sig) ^ (reg5_bind_mode_output_polarity_reversal);
`SIG_PROCESS_MODE__TRANSPARENT_MODE: output_sig <= signal_in_choose;
default: begin
output_sig <= 0;

129
source/src/top.v
View File

@ -101,8 +101,9 @@ module Top (
);
localparam SYS_CLOCK_FREQ = 100000000;
assign sys_clk = sys_clk_100m;
// assign sys_rst_n = ex_rst_n & pll_lock;
assign sys_rst_n = pll_lock;
assign sys_rst_n = stm32_input_bus[0] & pll_lock;
// assign sys_rst_n = pll_lock;
wire [31:0] rd_data_fpga_info;
wire [31:0] rd_data_internal_clk;
@ -258,7 +259,7 @@ module Top (
trigger_source_base_module #(
.REG_START_ADD (`REGADDOFF__TRIGGER_IN1),
.REG_START_ADD (`REGADDOFF__TRIGGER_IN2),
.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ)
) trigger_in2 (
.clk (sys_clk),
@ -279,49 +280,49 @@ module Top (
.out_trigger_sig_index3(sig_bus[`SIG_EXT_TRIGGER_2_I4])
);
trigger_source_base_module #(
.REG_START_ADD (`REGADDOFF__TRIGGER_IN1),
.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ)
) trigger_in3 (
.clk (sys_clk),
.rst_n(sys_rst_n),
.addr (RegReaderBus_addr),
.wr_data(RegReaderBus_wr_data),
.wr_en (RegReaderBus_wr_en),
.rd_data(rd_data_trigger_in3),
.in_sig_0(optocoupler_in3),
.in_sig_1(diff_in3),
.out_trigger_sig (sig_bus[`SIG_EXT_TRIGGER_3]),
.out_trigger_sig_index0(sig_bus[`SIG_EXT_TRIGGER_3_I1]),
.out_trigger_sig_index1(sig_bus[`SIG_EXT_TRIGGER_3_I2]),
.out_trigger_sig_index2(sig_bus[`SIG_EXT_TRIGGER_3_I3]),
.out_trigger_sig_index3(sig_bus[`SIG_EXT_TRIGGER_3_I4])
);
trigger_source_base_module #(
.REG_START_ADD (`REGADDOFF__TRIGGER_IN1),
.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ)
) trigger_in4 (
.clk (sys_clk),
.rst_n(sys_rst_n),
.addr (RegReaderBus_addr),
.wr_data(RegReaderBus_wr_data),
.wr_en (RegReaderBus_wr_en),
.rd_data(rd_data_trigger_in4),
.in_sig_0(optocoupler_in4),
.in_sig_1(diff_in4),
.out_trigger_sig (sig_bus[`SIG_EXT_TRIGGER_4]),
.out_trigger_sig_index0(sig_bus[`SIG_EXT_TRIGGER_4_I1]),
.out_trigger_sig_index1(sig_bus[`SIG_EXT_TRIGGER_4_I2]),
.out_trigger_sig_index2(sig_bus[`SIG_EXT_TRIGGER_4_I3]),
.out_trigger_sig_index3(sig_bus[`SIG_EXT_TRIGGER_4_I4])
);
trigger_source_base_module #(
.REG_START_ADD (`REGADDOFF__TRIGGER_IN3),
.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ)
) trigger_in3 (
.clk (sys_clk),
.rst_n(sys_rst_n),
.addr (RegReaderBus_addr),
.wr_data(RegReaderBus_wr_data),
.wr_en (RegReaderBus_wr_en),
.rd_data(rd_data_trigger_in3),
.in_sig_0(optocoupler_in3),
.in_sig_1(diff_in3),
.out_trigger_sig (sig_bus[`SIG_EXT_TRIGGER_3]),
.out_trigger_sig_index0(sig_bus[`SIG_EXT_TRIGGER_3_I1]),
.out_trigger_sig_index1(sig_bus[`SIG_EXT_TRIGGER_3_I2]),
.out_trigger_sig_index2(sig_bus[`SIG_EXT_TRIGGER_3_I3]),
.out_trigger_sig_index3(sig_bus[`SIG_EXT_TRIGGER_3_I4])
);
trigger_source_base_module #(
.REG_START_ADD (`REGADDOFF__TRIGGER_IN4),
.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ)
) trigger_in4 (
.clk (sys_clk),
.rst_n(sys_rst_n),
.addr (RegReaderBus_addr),
.wr_data(RegReaderBus_wr_data),
.wr_en (RegReaderBus_wr_en),
.rd_data(rd_data_trigger_in4),
.in_sig_0(optocoupler_in4),
.in_sig_1(diff_in4),
.out_trigger_sig (sig_bus[`SIG_EXT_TRIGGER_4]),
.out_trigger_sig_index0(sig_bus[`SIG_EXT_TRIGGER_4_I1]),
.out_trigger_sig_index1(sig_bus[`SIG_EXT_TRIGGER_4_I2]),
.out_trigger_sig_index2(sig_bus[`SIG_EXT_TRIGGER_4_I3]),
.out_trigger_sig_index3(sig_bus[`SIG_EXT_TRIGGER_4_I4])
);
// ttl_output_ctrl
@ -366,7 +367,7 @@ module Top (
);
light_src_ctrl #(
.REG_START_ADD(`REGADDOFF__LIGHT_CTROL_MODULE1),
.REG_START_ADD(`REGADDOFF__LIGHT_CTROL_MODULE2),
.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ),
.ID(2)
) light_src_ctrl_2 (
@ -406,7 +407,7 @@ module Top (
);
light_src_ctrl #(
.REG_START_ADD(`REGADDOFF__LIGHT_CTROL_MODULE1),
.REG_START_ADD(`REGADDOFF__LIGHT_CTROL_MODULE3),
.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ),
.ID(3)
) light_src_ctrl_3 (
@ -446,7 +447,7 @@ module Top (
);
light_src_ctrl #(
.REG_START_ADD(`REGADDOFF__LIGHT_CTROL_MODULE1),
.REG_START_ADD(`REGADDOFF__LIGHT_CTROL_MODULE4),
.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ),
.ID(4)
) light_src_ctrl_4 (
@ -486,23 +487,25 @@ module Top (
);
assign debug_bus[0] = internal_trigger_clk_ins_output_sig;
assign debug_bus[1] = sig_bus[`SIG_INTERNAL_CLK];
assign debug_bus[2] = sig_bus[`SIG_INTERNAL_CLK_I1];
assign debug_bus[3] = sig_bus[`SIG_INTERNAL_CLK_I2];
assign debug_bus[4] = sig_bus[`SIG_INTERNAL_CLK_I3];
assign debug_bus[5] = sig_bus[`SIG_INTERNAL_CLK_I4];
assign debug_bus[6] = lt1_intensity_ctrl;
assign debug_bus[7] = lt1_en;
assign debug_bus[8] = lt1_error_sig_in;
assign debug_bus[0] = sig_bus[`SIG_INTERNAL_CLK];
assign debug_bus[1] = sig_bus[`SIG_EXT_TRIGGER_1];
assign debug_bus[2] = sig_bus[`SIG_EXT_TRIGGER_2];
assign debug_bus[3] = sig_bus[`SIG_EXT_TRIGGER_3];
assign debug_bus[4] = sig_bus[`SIG_EXT_TRIGGER_4];
assign debug_bus[5] = lt1_en;
assign debug_bus[6] = lt2_en;
assign debug_bus[7] = lt3_en;
assign debug_bus[8] = lt4_en;
assign debug_bus[9] = optocoupler_out1;
assign debug_bus[10] = diff_out1;
assign debug_bus[10] = optocoupler_out2;
assign debug_bus[11] = optocoupler_out3;
assign debug_bus[12] = optocoupler_out4;
assign debug_bus[11] = lt1_en;
assign debug_bus[12] = lt2_en;
assign debug_bus[13] = lt3_en;
assign debug_bus[14] = lt4_en;
assign debug_bus[13] = lt1_intensity_ctrl;
assign debug_bus[14] = lt2_intensity_ctrl;
assign debug_bus[15] = lt3_intensity_ctrl;

10
source/src/trigger_source/internal_trigger_clk.v
View File

@ -48,13 +48,13 @@ module internal_trigger_clk #(
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
reg1_ctrl <= 0;
reg2_cfg_freq_cnt <= SYS_CLOCK_FREQ/10; //输出频率10hz
reg2_cfg_freq_cnt <= SYS_CLOCK_FREQ / 10; //输出频率10hz
reg3_cfg_pluse_cnt <= 32'd0; //
end else begin
if (reg_wr_sig) begin
case (reg_wr_index)
32'h2: reg2_cfg_freq_cnt <= reg_wr_index;
32'h3: reg3_cfg_pluse_cnt <= reg_wr_index;
32'h2: reg2_cfg_freq_cnt <= wr_data;
32'h3: reg3_cfg_pluse_cnt <= wr_data;
default: begin
end
endcase
@ -63,8 +63,8 @@ module internal_trigger_clk #(
end
always @(*) begin
start_sig <= (reg_wr_index == 1) & reg_wr_sig & (reg_wr_index == 1);
stop_sig <= (reg_wr_index == 1) & reg_wr_sig & (reg_wr_index == 0);
start_sig <= (reg_wr_index == 1) & reg_wr_sig & (wr_data == 1);
stop_sig <= (reg_wr_index == 1) & reg_wr_sig & (wr_data == 0);
end

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