diff --git a/README.md b/README.md index 47fb170..5bce2bb 100644 --- a/README.md +++ b/README.md @@ -1,4 +1,8 @@ ``` +https://iflytop1.feishu.cn/docx/Fk3CdIRNZoal1XxCGgjc9q1Dn1f +``` + +``` 核心板引脚分配: define_attribute {p:rst_n} {PAP_IO_DIRECTION} {INPUT} diff --git a/led_test.pds b/led_test.pds index 7f4f5f9..0f16148 100644 --- a/led_test.pds +++ b/led_test.pds @@ -1,5 +1,5 @@ (_flow fab_demo "2021.1-SP7" - (_comment "Generated by Fabric Compiler (version on 2021.1-SP7) at Thu Feb 29 22:19:25 2024") + (_comment "Generated by Fabric Compiler (version on 2021.1-SP7) at Sat Mar 2 18:19:24 2024") (_version "1.0.5") (_status "initial") (_project @@ -19,7 +19,7 @@ (_input (_file "source/src/top.v" + "Top:" (_format verilog) - (_timespec "2024-02-29T22:16:53") + (_timespec "2024-03-02T17:50:26") ) (_file "source/src/spi_reg_reader.v" (_format verilog) @@ -59,16 +59,12 @@ ) (_file "source/src/output/ttl_output.v" (_format verilog) - (_timespec "2024-02-27T20:28:55") + (_timespec "2024-03-02T18:19:22") ) (_file "source/src/zutils/zutils_pwm_generator.v" (_format verilog) (_timespec "2024-02-27T20:28:55") ) - (_file "source/src/rd_data_router.v" - (_format verilog) - (_timespec "2024-02-28T11:36:12") - ) (_file "source/src/zutils/zutils_reset_sig_gen.v" (_format verilog) (_timespec "2024-02-27T20:28:55") @@ -133,11 +129,11 @@ (_format verilog) (_timespec "2024-02-27T20:28:55") ) - (_file "source/src/timecode_output.v" + (_file "source/src/output/timecode_output.v" (_format verilog) (_timespec "2024-02-27T20:28:55") ) - (_file "source/src/camera_sync_signal_output.v" + (_file "source/src/input/timecode_input.v" (_format verilog) (_timespec "2024-02-27T20:28:55") ) @@ -149,18 +145,14 @@ (_format verilog) (_timespec "2024-02-27T20:28:55") ) - (_file "source/src/timecode_input.v" + (_file "source/src/input/ttl_input.v" (_format verilog) - (_timespec "2024-02-27T20:28:55") + (_timespec "2024-03-02T17:48:39") ) (_file "source/src/zutils/ztuils_sig_devide.v" (_format verilog) (_timespec "2024-02-27T20:28:55") ) - (_file "source/src/ttl_input.v" - (_format verilog) - (_timespec "2024-02-29T22:19:16") - ) (_file "source/src/zutils/zutils_signal_filter_advance.v" (_format verilog) (_timespec "2024-02-27T20:28:55") @@ -171,7 +163,11 @@ ) (_file "source/src/zutils/zutils_freq_detector.v" (_format verilog) - (_timespec "2024-02-29T22:02:42") + (_timespec "2024-03-02T17:47:04") + ) + (_file "source/src/zutils/zsimple_pll.v" + (_format verilog) + (_timespec "2024-03-02T16:28:23") ) ) ) @@ -239,21 +235,21 @@ ) (_task tsk_compile (_command cmd_compile - (_gci_state (_integer 2)) + (_gci_state (_integer 3)) (_db_output (_file "compile/Top_comp.adf" (_format adif) - (_timespec "2024-02-29T22:19:20") + (_timespec "2024-03-02T18:16:20") ) ) (_output (_file "compile/Top.cmr" (_format verilog) - (_timespec "2024-02-29T22:19:19") + (_timespec "2024-03-02T18:16:19") ) (_file "compile/cmr.db" (_format text) - (_timespec "2024-02-29T22:19:20") + (_timespec "2024-03-02T18:16:20") ) ) ) @@ -263,27 +259,27 @@ ) (_task tsk_synthesis (_command cmd_synthesize - (_gci_state (_integer 2)) + (_gci_state (_integer 3)) (_option ads (_switch ON)) (_option selected_syn_tool_opt (_integer 2)) (_db_output (_file "synthesize/Top_syn.adf" (_format adif) - (_timespec "2024-02-29T22:19:25") + (_timespec "2024-03-02T18:16:47") ) ) (_output (_file "synthesize/Top_syn.vm" (_format structural_verilog) - (_timespec "2024-02-29T22:19:25") + (_timespec "2024-03-02T18:16:49") ) (_file "synthesize/Top.snr" (_format text) - (_timespec "2024-02-29T22:19:25") + (_timespec "2024-03-02T18:16:51") ) (_file "synthesize/snr.db" (_format text) - (_timespec "2024-02-29T22:19:25") + (_timespec "2024-03-02T18:16:52") ) ) ) @@ -300,14 +296,34 @@ ) (_task tsk_devmap (_command cmd_devmap - (_gci_state (_integer 0)) + (_gci_state (_integer 3)) + (_db_output + (_file "device_map/Top_map.adf" + (_format adif) + (_timespec "2024-03-02T18:16:55") + ) + ) + (_output + (_file "device_map/Top_dmr.prt" + (_format text) + (_timespec "2024-03-02T18:16:54") + ) + (_file "device_map/Top.dmr" + (_format text) + (_timespec "2024-03-02T18:16:55") + ) + (_file "device_map/dmr.db" + (_format text) + (_timespec "2024-03-02T18:16:55") + ) + ) ) (_widget wgt_edit_placement_cons (_attribute _click_to_run (_switch ON)) (_input (_file "device_map/led_test.pcf" (_format pcf) - (_timespec "2024-02-27T20:30:08") + (_timespec "2024-03-02T18:16:55") ) ) ) @@ -317,8 +333,40 @@ ) (_task tsk_pnr (_command cmd_pnr - (_gci_state (_integer 0)) + (_gci_state (_integer 3)) (_option mode (_string "fast")) + (_db_output + (_file "place_route/Top_pnr.adf" + (_format adif) + (_timespec "2024-03-02T18:17:42") + ) + ) + (_output + (_file "place_route/Top.prr" + (_format text) + (_timespec "2024-03-02T18:17:42") + ) + (_file "place_route/Top_prr.prt" + (_format text) + (_timespec "2024-03-02T18:17:41") + ) + (_file "place_route/clock_utilization.txt" + (_format text) + (_timespec "2024-03-02T18:17:41") + ) + (_file "place_route/Top_plc.adf" + (_format adif) + (_timespec "2024-03-02T18:17:09") + ) + (_file "place_route/Top_pnr.netlist" + (_format text) + (_timespec "2024-03-02T18:17:42") + ) + (_file "place_route/prr.db" + (_format text) + (_timespec "2024-03-02T18:17:43") + ) + ) ) (_widget wgt_power_calculator (_attribute _click_to_run (_switch ON)) @@ -329,6 +377,7 @@ (_command cmd_report_post_pnr_timing (_gci_state (_integer 0)) (_attribute _auto_exe_lock (_switch OFF)) + (_attribute _auto_exe (_switch OFF)) ) (_widget wgt_arch_browser (_attribute _click_to_run (_switch ON)) @@ -346,7 +395,25 @@ ) (_task tsk_gen_bitstream (_command cmd_gen_bitstream - (_gci_state (_integer 0)) + (_gci_state (_integer 3)) + (_output + (_file "generate_bitstream/Top.sbit" + (_format text) + (_timespec "2024-03-02T18:18:14") + ) + (_file "generate_bitstream/Top.smsk" + (_format text) + (_timespec "2024-03-02T18:18:14") + ) + (_file "generate_bitstream/Top.bgr" + (_format text) + (_timespec "2024-03-02T18:18:14") + ) + (_file "generate_bitstream/bgr.db" + (_format text) + (_timespec "2024-03-02T18:18:16") + ) + ) ) ) ) diff --git a/source/src/debuger.v b/source/src/debuger.v deleted file mode 100644 index 9bfc4f1..0000000 --- a/source/src/debuger.v +++ /dev/null @@ -1,29 +0,0 @@ -/* - * Hacky baud rate generator to divide a 50MHz clock into a 115200 baud - * rx/tx pair where the rx clcken oversamples by 16x. - */ -module rd_data_router ( - input [31:0] addr, - - input [31:0] stm32_rd_data, - input [31:0] fpga_test_rd_data, - input [31:0] xsync_internal_sig_generator_rd_data, - input [31:0] ttlin1_rd_data, - input [31:0] ttlin2_rd_data, - input [31:0] ttlin3_rd_data, - input [31:0] ttlin4_rd_data, - input [31:0] timecode_in_rd_data, - input [31:0] genlock_in_rd_data, - input [31:0] ttlout1_rd_data, - input [31:0] ttlout2_rd_data, - input [31:0] ttlout3_rd_data, - input [31:0] ttlout4_rd_data, - input [31:0] timecode_out_rd_data, - input [31:0] genlock_out_rd_data, - input [31:0] camera_sync_out_rd_data, - input [31:0] debuger_rd_data, - - output reg [31:0] rd_data_out -); - -endmodule \ No newline at end of file diff --git a/source/src/input/src_genlock.v b/source/src/input/src_genlock.v deleted file mode 100644 index e69de29..0000000 diff --git a/source/src/input/src_timecode.v b/source/src/input/src_timecode.v deleted file mode 100644 index 8ef0be2..0000000 --- a/source/src/input/src_timecode.v +++ /dev/null @@ -1,208 +0,0 @@ -// module src_timecode_parser #( -// parameter REG_START_ADD = 0 -// ) ( -// input clk, //clock input -// input rst_n, //asynchronous reset input, low active - -// //regbus interface -// output reg [31:0] addr, -// input [31:0] wr_data, -// input wr_en, - -// inout wire [31:0] rd_data, //received serial data -// // 输入 -// input timecode_signal_in, -// //输出 -// output wire timecode_signal_orgin_output, //ttl原始数据 -// output wire timecode_freq_trigger_signal -// ); - -// /******************************************************************************* -// * 寄存器读写 * -// *******************************************************************************/ - -// // -// // @功能: -// // 1. 采样TIMECODE信号 -// // 2. 转发TIMECODE信号 -// // 3. TIMECODE信号成功解析 -// // 4. TIMECODE采样计数 -// // -// // @寄存器列表: -// // 地址 读写 默认 描述 -// // 0x00 wr 0x0 timecode bit周期 -// // 0x01 r 0x0 flag bit[0]:timecode_ready_flag -// // 0x02 r 0x0 timecode [31:0] -// // 0x03 r 0x0 timecode [63:32] -// // 0x04 r 0x0 timecode_ready_signal_pluse_width //识别到一帧timecode信号后，输出一个脉冲信号，用于同步其他模块 - -// parameter REG_TIMECODE_BIT_PERIOD_ADD = REG_START_ADD + 0; //timecode bit周期寄存器地址 - - -// parameter ADD_NUM = 5; //寄存器数量 -// parameter REG_END_ADD = REG_START_ADD + ADD_NUM - 1; //寄存器结束地址 -// reg [31:0] register[REG_START_ADD:REG_END_ADD]; -// integer i; -// always @(posedge clk or negedge rst_n) begin -// if (!rst_n) begin -// for (i = 0; i < ADD_NUM; i = i + 1) begin -// register[i] <= 0; -// end -// end else begin -// if (wr_en && addr >= REG_START_ADD && addr <= REG_END_ADD) register[addr] <= wr_data; -// end -// end -// assign rd_data = (addr >= REG_START_ADD && addr <= REG_END_ADD) ? register[addr] : 31'bz; - - - -// // 416us 500us 520us -// // 边沿触发--> 采样偏移同步 -// // - -// // 416us采用 160byte 采样到同步 -// // 电平变化修正采样计数 - -// // -// // 配置: -// // 1. 制式 -// // 2. - -// // 边沿信号捕获 - - -// reg [160-1:0] tc_bit_2x; //timecode 每1/2bit -// reg [79:0] tc_bit; //timecode 每1bit -// reg sample_signal; //采样信号 -// reg [31:0] sample_time_cnt; //采样计数 -// wire sample_time_calibrate_signal; //采样信号修正器 -// reg time_code_signal_edge; //timecode原始信号的边沿信号，即timecode上升沿或者下降沿时，置1 -// assign timecode_signal_in_a = timecode_signal_in; // -// reg timecode_signal_in_b; // -// reg tc_sync_signal_edge; // timecode捕获到同步信号时，置1，此时可以解析timecode信号，并将其存放到寄存中 - - -// /******************************************************************************* -// * timecode边沿信号捕获 * -// *******************************************************************************/ -// always @(posedge clk or negedge rst_n) begin -// if (!rst_n) begin -// timecode_signal_in_b <= 0; -// end else begin -// timecode_signal_in_b <= timecode_signal_in_a; -// end -// end - -// always @(posedge clk or negedge rst_n) begin -// if (!rst_n) begin -// time_code_signal_edge <= 0; -// end else begin -// if (timecode_signal_in_a != timecode_signal_in_b) begin -// time_code_signal_edge <= 1; -// end else begin -// time_code_signal_edge <= 0; -// end -// end -// end - -// assign sample_time_calibrate_signal = time_code_signal_edge; - - -// /******************************************************************************* -// * BIT信号映射 * -// *******************************************************************************/ -// // -// // 采样点 采样点 采样点 采样点 -// // + + + + -// // ___------------_______-------- -// // 0 1 -// // timecode的每个bit要通过两个点进行判断，所以需要2x的采样率 -// // -// always @(*) begin -// for (i = 0; i < 79; i = i + 1) begin -// tc_bit[i] = !tc_bit_2x[i*2] & tc_bit_2x[i*2+1]; -// end -// end - -// /******************************************************************************* -// * 采样信号生成器 * -// *******************************************************************************/ -// // -// // 1. 当捕获到timecode原始信号的边沿时，校准采样信号计数器 -// // 2. 当采样信号计数器到达采样点时，输出采样信号 -// // 3. 当采样信号计数器到达2倍采样点时，重置采样信号计数器 -// // -// assign timecode_sample_cnt_reset_signal = ( -// sample_time_calibrate_signal|| -// sample_time_cnt >= (register[REG_TIMECODE_BIT_PERIOD_ADD] << 1) -// ); -// always @(posedge clk or negedge rst_n) begin -// if (!rst_n) begin -// sample_time_cnt <= 0; -// sample_signal <= 0; -// end else begin -// if (timecode_sample_cnt_reset_signal) begin -// sample_time_cnt <= 0; -// sample_signal <= 0; -// end else if (sample_time_cnt == register[REG_TIMECODE_BIT_PERIOD_ADD]) begin -// sample_time_cnt <= sample_time_cnt + 1; -// sample_signal <= 1; -// end else begin -// sample_time_cnt <= sample_time_cnt + 1; -// sample_signal <= 0; -// end -// end -// end - -// // -// // 根据sample_signal捕获timecode信号 -// // -// always @(posedge clk or negedge rst_n) begin -// if (!rst_n) begin -// tc_bit_2x <= 0; -// end else begin -// if (sample_signal) begin -// tc_bit_2x <= {tc_bit_2x[158:0], timecode_signal_in}; -// end else begin -// tc_bit_2x <= tc_bit_2x; -// end -// end -// end - -// /******************************************************************************* -// * tc_sync_signal_edge * -// *******************************************************************************/ -// // ___------------_______-------- -// // 0 1 -// // -// // 捕获timecode同步信号 -// // -// // 同步信号 -// // 0011_1111_11111_1101 -// // 1111_0101__0101_0101__0101_0101__0101_1101 -// // -// reg [31:0] sync_code_pattern = 32'b1111_0101__0101_0101__0101_0101__0101_1101; -// assign tc_sync_signal = (tc_bit == sync_code_pattern); -// reg tc_sync_signal_b; -// always @(posedge clk or negedge rst_n) begin -// if (!rst_n) begin -// tc_sync_signal_b <= 0; -// end else begin -// tc_sync_signal_b <= tc_sync_signal; - -// if (tc_sync_signal & !tc_sync_signal_b) begin -// tc_sync_signal_edge <= 1; -// end else begin -// tc_sync_signal_edge <= 0; -// end -// end -// end - - - - -// assign timecode_freq_trigger_signal = tc_sync_signal_edge; - - - -// endmodule diff --git a/source/src/input/src_ttl_parser.v b/source/src/input/src_ttl_parser.v deleted file mode 100644 index b7b9a5b..0000000 --- a/source/src/input/src_ttl_parser.v +++ /dev/null @@ -1,131 +0,0 @@ -// module src_ttl_parser #( -// parameter REG_START_ADD = 0 -// ) ( -// input clk, //clock input -// input rst_n, //asynchronous reset input, low active - -// //regbus interface -// output reg [31:0] addr, -// input [31:0] wr_data, -// input wr_en, - -// inout wire [31:0] rd_data, //received serial data -// // 输入 -// input ttlin, -// //输出 -// output wire ttl_output //ttl原始数据 -// ); -// // -// // @功能: -// // 1. 计算ttl频率 -// // 2. 转发ttl信号 -// // 3. 分频倍频 -// // -// // @寄存器列表: -// // 地址 读写 默认 描述 -// // 0x00 r 0x0 function 0:原始信号输出 1:频率信号源 -// // 0x01 r 0x0 freq //一个周期的计数，单位为 1/50M s -// // 0x02 wr 0x0 pll_mul //暂不支持 -// // 0x03 wr 0x0 pll_div -// // 0x04 wr 0x0 [0]:信号源是上升沿触发，还是下降沿触发 -// // - - -// reg ttl_origin_output; //ttl原始信号输出 -// reg ttl_after_process_output; //ttl处理后信号输出 - - -// /******************************************************************************* -// * 寄存器读写 * -// *******************************************************************************/ - -// parameter ADD_NUM = 5; //寄存器数量 -// parameter REG_END_ADD = REG_START_ADD + ADD_NUM - 1; //寄存器结束地址 -// reg [31:0] register[REG_START_ADD:REG_END_ADD]; -// integer i; -// always @(posedge clk or negedge rst_n) begin -// if (!rst_n) begin -// for (i = 0; i < ADD_NUM; i = i + 1) begin -// register[i] <= 0; -// end -// end else begin -// if (wr_en && addr >= REG_START_ADD && addr <= REG_END_ADD) register[addr] <= wr_data; -// end -// end -// assign rd_data = (addr >= REG_START_ADD && addr <= REG_END_ADD) ? register[addr] : 31'bz; - -// parameter REG_FUNC_ADD = REG_START_ADD + 0; -// parameter REG_FREQ_ADD = REG_START_ADD + 1; -// parameter REG_PLL_MUL_ADD = REG_START_ADD + 2; -// parameter REG_PLL_DIV_ADD = REG_START_ADD + 3; -// parameter REG_TTL_EDGE_ADD = REG_START_ADD + 4; - -// /******************************************************************************* -// * ttl输出路径选择 * -// *******************************************************************************/ - -// assign ttl_output = (register[REG_FUNC_ADD] == 0) ? ttl_origin_output : ttl_after_process_output; - -// /******************************************************************************* -// * 原始信号输出 * -// *******************************************************************************/ -// always @(posedge clk or negedge rst_n) begin -// if (!rst_n) begin -// ttl_origin_output <= 0; -// end else begin -// ttl_origin_output <= ttlin; -// end -// end - -// /******************************************************************************* -// * ttl_in_last信号捕获 * -// *******************************************************************************/ -// reg ttl_in_last; -// always @(posedge clk or negedge rst_n) begin -// if (!rst_n) begin -// ttl_in_last <= 0; -// end else begin -// ttl_in_last <= ttlin; -// end -// end - - -// /******************************************************************************* -// * 频率探测 * -// *******************************************************************************/ -// reg [31:0] ttl_freq_cnt; -// always @(posedge clk or negedge rst_n) begin -// if (!rst_n) begin -// ttl_freq_cnt <= 0; -// end else begin -// if (ttlin && !ttl_in_last) begin -// register[REG_FREQ_ADD] <= ttl_freq_cnt; -// ttl_freq_cnt <= 0; -// end -// if (ttl_freq_cnt != 32'hffff_ffff_ffff_ffff) begin -// ttl_freq_cnt <= ttl_freq_cnt + 1; -// end -// end -// end - -// /******************************************************************************* -// * 分频 * -// *******************************************************************************/ -// reg [31:0] ttl_in_cnt; -// always @(posedge clk or negedge rst_n) begin -// if (!rst_n) begin -// ttl_in_cnt <= 0; -// end else begin -// if (ttlin && !ttl_in_last) begin -// if (ttl_in_cnt <= register[REG_PLL_MUL_ADD]) begin -// ttl_in_cnt <= ttl_in_cnt + 1; -// end else begin -// ttl_in_cnt <= 0; -// ttl_after_process_output <= 1; -// end -// end else begin -// ttl_after_process_output <= 0; -// end -// end -// end -// endmodule diff --git a/source/src/timecode_input.v b/source/src/input/timecode_input.v similarity index 100% rename from source/src/timecode_input.v rename to source/src/input/timecode_input.v diff --git a/source/src/ttl_input.v b/source/src/input/ttl_input.v similarity index 83% rename from source/src/ttl_input.v rename to source/src/input/ttl_input.v index 792cec7..87e0b17 100644 --- a/source/src/ttl_input.v +++ b/source/src/input/ttl_input.v @@ -35,7 +35,7 @@ module ttl_input #( output sig_ttlin4 //! 输出信号4 ); - reg [31:0] r0_ttlin_en; // !信号源选择 0:off,1:bnc,2:headphone + reg [31:0] r0_ttlin_en; // !信号源使能控制寄存器 wire [31:0] r1_ttlin1_freq_detector; // !频率探测 wire [31:0] r2_ttlin2_freq_detector; // !频率探测 wire [31:0] r3_ttlin3_freq_detector; // !频率探测 @@ -146,31 +146,35 @@ module ttl_input #( - zutils_freq_detector freq_detector1 ( - .clk(clk), - .rst_n(rst_n), - .pluse_input(ttlin1_sig_af_filter), - .pluse_width_cnt(r1_ttlin1_freq_detector) - ); - - zutils_freq_detector freq_detector2 ( - .clk(clk), - .rst_n(rst_n), - .pluse_input(ttlin2_sig_af_filter), - .pluse_width_cnt(r2_ttlin2_freq_detector) - ); - zutils_freq_detector freq_detector3 ( - .clk(clk), - .rst_n(rst_n), - .pluse_input(ttlin3_sig_af_filter), - .pluse_width_cnt(r3_ttlin3_freq_detector) - ); - zutils_freq_detector freq_detector4 ( - .clk(clk), - .rst_n(rst_n), - .pluse_input(ttlin4_sig_af_filter), - .pluse_width_cnt(r4_ttlin4_freq_detector) - ); + zutils_freq_detector + freq_detector1 ( + .clk(clk), + .rst_n(rst_n), + .pluse_input(ttlin1_sig_af_filter), + .pluse_width_cnt(r1_ttlin1_freq_detector) + ); + + zutils_freq_detector + freq_detector2 ( + .clk(clk), + .rst_n(rst_n), + .pluse_input(ttlin2_sig_af_filter), + .pluse_width_cnt(r2_ttlin2_freq_detector) + ); + zutils_freq_detector + freq_detector3 ( + .clk(clk), + .rst_n(rst_n), + .pluse_input(ttlin3_sig_af_filter), + .pluse_width_cnt(r3_ttlin3_freq_detector) + ); + zutils_freq_detector + freq_detector4 ( + .clk(clk), + .rst_n(rst_n), + .pluse_input(ttlin4_sig_af_filter), + .pluse_width_cnt(r4_ttlin4_freq_detector) + ); assign sig_ttlin1 = ttlin1_sig_af_filter; diff --git a/source/src/camera_sync_signal_output.v b/source/src/output/camera_sync_signal_output.v similarity index 100% rename from source/src/camera_sync_signal_output.v rename to source/src/output/camera_sync_signal_output.v diff --git a/source/src/timecode_output.v b/source/src/output/timecode_output.v similarity index 100% rename from source/src/timecode_output.v rename to source/src/output/timecode_output.v diff --git a/source/src/output/ttl_output.v b/source/src/output/ttl_output.v index 8e50f68..7046115 100644 --- a/source/src/output/ttl_output.v +++ b/source/src/output/ttl_output.v @@ -1,20 +1,13 @@ -// -// @功能: -// 1. 功能:同步输出,脉冲输出 -// 2. 输出脉冲 -// 3. 输出脉冲时长可调 -// 4. 输出极性可调 -// module ttl_output #( parameter REG_START_ADD = 0, parameter SYS_CLOCK_FREQ = 10000000, // parameter TEST = 0, parameter ID = 1 -) ( + ) ( input clk, //clock input input rst_n, //asynchronous reset input, low active - //寄存器读写接口 + //寄存器读写接口 input [31:0] addr, input [31:0] wr_data, input wr_en, @@ -24,142 +17,191 @@ module ttl_output #( output ttloutput, //ttl输出信号 output ttloutput_state_led //ttl输出状态信号 -); + ); + + // 编写注意事项 + // 1. 修改配置寄存器时候，部分计数需要清空 + /******************************************************************************* * 寄存器列表 * *******************************************************************************/ - // - // 输入信号选择器 - // 0: 信号0 - // 1: 信号1 - // ... - // x: 信号x - - wire [31:0] reg_input_signal_select; - // - // 输出信号选择器 - // [0] - // 0:输出0 - // 1:输出1 - // 2:测试信号输出 - // 3:原始信号 - // 4:原始信号翻转输出 - // 5:脉冲输出 - // 6:脉冲信号翻转输出 - localparam REG1_INIT = 0; - wire [31:0] reg_output_signal_select; - - // - // 配置寄存器 - // [0] 脉冲输入时候触发信号 0:上升沿 1:下降沿触发 - // - wire [31:0] reg_config; - assign pluse_input_trigger_signal = reg_config[0]; - // - // 脉冲模式-有效电平长度: - // 0~0xffffffff - // - wire [31:0] reg_pulse_mode_valid_len; // 脉冲模式-有效电平长度: 0~0xffffffff - // - // 脉冲模式-触发延时: - // 0~0xffffffff - // - wire [31:0] reg_pulse_mode_trigger_delay; // 脉冲模式-触发延时: 0~0xffffffff - - - zutils_register16 #( - .REG_START_ADD(REG_START_ADD), - .REG1_INIT(REG1_INIT) - ) _register ( - .clk(clk), - .rst_n(rst_n), - .addr(addr), - .wr_data(wr_data), - .wr_en(wr_en), - .rd_data(rd_data), - .reg0(reg_input_signal_select), - .reg1(reg_output_signal_select), - .reg2(reg_config), - .reg3(reg_pulse_mode_valid_len), - .reg4(reg_pulse_mode_trigger_delay) - ); + //!信号处理模式 0:固定输出低电平，1:固定输出高电平，2:分频倍频模式，3:转发模式，4:测试模式 + reg [31:0] reg_signal_process_mode; + //!TTLOUT_信号选择器 + reg [31:0] reg_input_signal_select; + //!TTLOUT_分频器 + reg [31:0] reg_input_freq_division; + //!TTLOUT_频率倍增器 + reg [31:0] reg_input_freq_multiplication; + //!TTLOUT_极性控制寄存器 + reg [31:0] reg_input_polarity_ctrl; + //!TTLOUT_触发信号边沿类型 + reg [31:0] reg_input_trigger_edge_select; + //!输入信号频率探测 read only + reg [31:0] reg_sig_in_freq_detect; + //!输出信号频率探测 read only + reg [31:0] reg_sig_out_freq_detect; + + + //!寄存器写入时相对地址 + wire [31:0] reg_wr_index; + + + wire signal_in_choose; //!原始信号 + wire signal_in_multiplication;//!倍频后的信号 + wire signal_in_polarity_ctrl;//!极性翻转后的信号 + + + //!TTLOUT_寄存器自动赋值选择器 + zutils_register_advanced #( + .REG_START_ADD(REG_START_ADD) + ) _register ( + .clk(clk), + .rst_n(rst_n), + .addr(addr), + .wr_data(wr_data), + .wr_en(wr_en), + .rd_data(rd_data), + .reg0(reg_signal_process_mode), + .reg1(reg_input_signal_select), + .reg2(reg_input_freq_division), + .reg3(reg_input_freq_multiplication), + .reg4(reg_input_polarity_ctrl), + .reg5(reg_sig_in_freq_detect), + .reg6(reg_sig_out_freq_detect), + .reg7(reg_input_trigger_edge_select), + .reg_wr_sig(reg_wr_sig), + .reg_index(reg_wr_index) + ); + + //!寄存器写入逻辑 + always @(posedge clk or negedge rst_n) begin + if (!rst_n) begin + reg_signal_process_mode<=0; + reg_input_signal_select<=0; + reg_input_freq_division<=0; + reg_input_freq_multiplication<=0; + reg_input_polarity_ctrl<=0; + reg_input_trigger_edge_select<=1; + // reg_sig_in_freq_detect<=0; + // reg_sig_out_freq_detect<=0; + end + else begin + if (reg_wr_sig) begin + case (reg_wr_index) + 0: + reg_signal_process_mode <= wr_data; + 1: + reg_input_signal_select <= wr_data; + 2: + reg_input_freq_division <= wr_data; + 3: + reg_input_freq_multiplication <= wr_data; + 4: + reg_input_polarity_ctrl <= wr_data; + // 5: + // reg_sig_in_freq_detect <= wr_data; + // 6: + // reg_sig_out_freq_detect <= wr_data; + default: begin + end + endcase + end + end + end + + assign signal_in_choose = signal_in[2]; + + zsimple_pll _simple_pll ( + .clk(clk), + .rst_n(rst_n), + .insignal(signal_in_choose), + .trigger_eage_type(reg_input_trigger_edge_select[0]), + .freq_division(32'd2), + .freq_multiplication(32'd3), + .cfg_change(reg_wr_sig), + .outsignal(signal_in_multiplication) + ); + + assign ttloutput_state_led = 1; + assign ttloutput = signal_in_multiplication; + /******************************************************************************* * 内部信号 * *******************************************************************************/ - //脉冲输出 - wire pluse_output; - // 输入信号上升沿事件 - wire in_signal_rising_edge; - // 输入信号下降沿事件 - wire in_signal_falling_edge; - // 输入信号上升沿或下降沿事件 - wire in_signal_edge; - // 输出的脉冲触发信号的触发信号 - wire signal_src_trigger; - - assign signal_src_trigger = (pluse_input_trigger_signal==0) ? (in_signal_rising_edge) : (in_signal_falling_edge); - - wire signal_in_choose; - zutils_multiplexer_32t1 _signal_select ( - .chooseindex(reg_input_signal_select), - .signal(signal_in), - .signalout(signal_in_choose) - ); - - - // 边沿检测 - zutils_edge_detecter _signal_in ( - .clk(clk), - .rst_n(rst_n), - .in_signal(signal_in_choose), - .in_signal_rising_edge(in_signal_rising_edge), - .in_signal_falling_edge(in_signal_falling_edge), - .in_signal_edge(in_signal_edge) - ); - - // 短脉冲，触发生成，长脉冲 - zutils_pluse_generator _pluse_generator ( - .clk(clk), - .rst_n(rst_n), - .pluse_width(reg_pulse_mode_valid_len), - .pluse_delay(reg_pulse_mode_trigger_delay), - .trigger(signal_src_trigger), - .output_signal(ttl_after_process_output) - ); - - zutils_pwm_generator #( - .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ), - .OUTPUT_FREQ(1000 * ID) - ) _test_signal_generator ( - .clk(clk), - .rst_n(rst_n), - .output_signal(test_signal_output) - ); - - - - wire [15:0] signal_output_select_in; - assign signal_output_select_in[0] = 1'b0; - assign signal_output_select_in[1] = 1'b1; - assign signal_output_select_in[2] = test_signal_output; - assign signal_output_select_in[3] = signal_in_choose; - assign signal_output_select_in[4] = !signal_in_choose; - assign signal_output_select_in[5] = ttl_after_process_output; - assign signal_output_select_in[6] = !ttl_after_process_output; - assign signal_output_select_in[7] = 1'b0; - assign signal_output_select_in[15:8] = 8'b0; - - zutils_multiplexer_16t1 _signal_output_select ( - .chooseindex(reg_output_signal_select), - .signal(signal_output_select_in), - - .signalout(ttloutput) - ); - // assign ttloutput_state_led = !ttloutput; - assign ttloutput_state_led = 1; + // //脉冲输出 + // wire pluse_output; + // // 输入信号上升沿事件 + // wire in_signal_rising_edge; + // // 输入信号下降沿事件 + // wire in_signal_falling_edge; + // // 输入信号上升沿或下降沿事件 + // wire in_signal_edge; + // // 输出的脉冲触发信号的触发信号 + // wire signal_src_trigger; + + // assign signal_src_trigger = (pluse_input_trigger_signal==0) ? (in_signal_rising_edge) : (in_signal_falling_edge); + + // wire signal_in_choose; + // zutils_multiplexer_32t1 _signal_select ( + // .chooseindex(reg_input_signal_select), + // .signal(signal_in), + // .signalout(signal_in_choose) + // ); + + + // // 边沿检测 + // zutils_edge_detecter _signal_in ( + // .clk(clk), + // .rst_n(rst_n), + // .in_signal(signal_in_choose), + // .in_signal_rising_edge(in_signal_rising_edge), + // .in_signal_falling_edge(in_signal_falling_edge), + // .in_signal_edge(in_signal_edge) + // ); + + // // 短脉冲，触发生成，长脉冲 + // zutils_pluse_generator _pluse_generator ( + // .clk(clk), + // .rst_n(rst_n), + // .pluse_width(reg_pulse_mode_valid_len), + // .pluse_delay(reg_pulse_mode_trigger_delay), + // .trigger(signal_src_trigger), + // .output_signal(ttl_after_process_output) + // ); + + // zutils_pwm_generator #( + // .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ), + // .OUTPUT_FREQ(1000 * ID) + // ) _test_signal_generator ( + // .clk(clk), + // .rst_n(rst_n), + // .output_signal(test_signal_output) + // ); + + + + // wire [15:0] signal_output_select_in; + // assign signal_output_select_in[0] = 1'b0; + // assign signal_output_select_in[1] = 1'b1; + // assign signal_output_select_in[2] = test_signal_output; + // assign signal_output_select_in[3] = signal_in_choose; + // assign signal_output_select_in[4] = !signal_in_choose; + // assign signal_output_select_in[5] = ttl_after_process_output; + // assign signal_output_select_in[6] = !ttl_after_process_output; + // assign signal_output_select_in[7] = 1'b0; + // assign signal_output_select_in[15:8] = 8'b0; + + // zutils_multiplexer_16t1 _signal_output_select ( + // .chooseindex(reg_output_signal_select), + // .signal(signal_output_select_in), + + // .signalout(ttloutput) + // ); + // // assign ttloutput_state_led = !ttloutput; endmodule diff --git a/source/src/rd_data_router.v b/source/src/rd_data_router.v deleted file mode 100644 index 60f37b6..0000000 --- a/source/src/rd_data_router.v +++ /dev/null @@ -1,95 +0,0 @@ -/* - * Hacky baud rate generator to divide a 50MHz clock into a 115200 baud - * rx/tx pair where the rx clcken oversamples by 16x. - */ -module rd_data_router #( - parameter REG_ADD_OFF_STM32 = 0, - parameter REG_ADD_OFF_FPGA_TEST = 0, - parameter REG_ADD_OFF_XSYNC_INTERNAL_SIG_GENERATOR = 0, - parameter REG_ADD_OFF_TTLIN1 = 0, - parameter REG_ADD_OFF_TTLIN2 = 0, - parameter REG_ADD_OFF_TTLIN3 = 0, - parameter REG_ADD_OFF_TTLIN4 = 0, - parameter REG_ADD_OFF_TIMECODE_IN = 0, - parameter REG_ADD_OFF_GENLOCK_IN = 0, - parameter REG_ADD_OFF_TTLOUT1 = 0, - parameter REG_ADD_OFF_TTLOUT2 = 0, - parameter REG_ADD_OFF_TTLOUT3 = 0, - parameter REG_ADD_OFF_TTLOUT4 = 0, - parameter REG_ADD_OFF_TIMECODE_OUT = 0, - parameter REG_ADD_OFF_GENLOCK_OUT = 0, - parameter REG_ADD_OFF_CAMERA_SYNC_OUT = 0, - parameter REG_ADD_OFF_DEBUGER = 0 - - ) ( - input [31:0] addr, - - input [31:0] stm32_rd_data, - input [31:0] fpga_test_rd_data, - input [31:0] xsync_internal_sig_generator_rd_data, - input [31:0] ttlin1_rd_data, - input [31:0] ttlin2_rd_data, - input [31:0] ttlin3_rd_data, - input [31:0] ttlin4_rd_data, - input [31:0] timecode_in_rd_data, - input [31:0] genlock_in_rd_data, - input [31:0] ttlout1_rd_data, - input [31:0] ttlout2_rd_data, - input [31:0] ttlout3_rd_data, - input [31:0] ttlout4_rd_data, - input [31:0] timecode_out_rd_data, - input [31:0] genlock_out_rd_data, - input [31:0] camera_sync_out_rd_data, - input [31:0] debuger_rd_data, - - output reg [31:0] rd_data_out - ); - - // initial rd_data_out = 0; - // wire [31:0] addr_8 = addr >> 8; - wire [31:0] addr_group; - assign addr_group = addr & 31'hFFFF_FFF0; - - always @(*) - begin - case (addr_group) - REG_ADD_OFF_STM32: - rd_data_out = stm32_rd_data; - REG_ADD_OFF_FPGA_TEST: - rd_data_out = fpga_test_rd_data; - REG_ADD_OFF_XSYNC_INTERNAL_SIG_GENERATOR: - rd_data_out = xsync_internal_sig_generator_rd_data; - REG_ADD_OFF_TTLIN1: - rd_data_out = ttlin1_rd_data; - REG_ADD_OFF_TTLIN2: - rd_data_out = ttlin2_rd_data; - REG_ADD_OFF_TTLIN3: - rd_data_out = ttlin3_rd_data; - REG_ADD_OFF_TTLIN4: - rd_data_out = ttlin4_rd_data; - REG_ADD_OFF_TIMECODE_IN: - rd_data_out = timecode_in_rd_data; - REG_ADD_OFF_GENLOCK_IN: - rd_data_out = genlock_in_rd_data; - REG_ADD_OFF_TTLOUT1: - rd_data_out = ttlout1_rd_data; - REG_ADD_OFF_TTLOUT2: - rd_data_out = ttlout2_rd_data; - REG_ADD_OFF_TTLOUT3: - rd_data_out = ttlout3_rd_data; - REG_ADD_OFF_TTLOUT4: - rd_data_out = ttlout4_rd_data; - REG_ADD_OFF_TIMECODE_OUT: - rd_data_out = timecode_out_rd_data; - REG_ADD_OFF_GENLOCK_OUT: - rd_data_out = genlock_out_rd_data; - REG_ADD_OFF_CAMERA_SYNC_OUT: - rd_data_out = camera_sync_out_rd_data; - REG_ADD_OFF_DEBUGER: - rd_data_out = debuger_rd_data; - default: - rd_data_out = 0; - endcase - end - -endmodule diff --git a/source/src/top.v b/source/src/top.v index 28b2873..a03b4fb 100644 --- a/source/src/top.v +++ b/source/src/top.v @@ -8,7 +8,6 @@ module Top ( input genlock_in_fsync, output genlock_in_state_led, - output [9:0] genlock_out_dac, output genlock_out_dac_clk, output genlock_out_dac_state_led, @@ -79,14 +78,21 @@ module Top ( localparam REGADDOFF__TTLIN = 16'h0100; localparam REGADDOFF__TIMECODE_IN = 16'h0120; localparam REGADDOFF__GENLOCK_IN = 16'h0130; - localparam REGADDOFF__INTERNAL_TIMECODE = 16'h0200; //!内部时间码 - localparam REGADDOFF__INTERNAL_GENLOCK = 16'h0210; //!内部同步信号 - localparam REGADDOFF__INTERNAL_CLOCK = 16'h0220; //!内部时钟 - + localparam REGADDOFF__INTERNAL_TIMECODE = 16'h0200; + localparam REGADDOFF__INTERNAL_GENLOCK = 16'h0210; + localparam REGADDOFF__INTERNAL_CLOCK = 16'h0220; + localparam REGADDOFF__TTLOUT1 = 16'h0200; + localparam REGADDOFF__TTLOUT2 = 16'h0210; + localparam REGADDOFF__TTLOUT3 = 16'h0220; + localparam REGADDOFF__TTLOUT4 = 16'h0230; + localparam REGADDOFF__TIMECODE_OUT = 16'h0240; + localparam REGADDOFF__GENLOCK_OUT = 16'h0250; + localparam REGADDOFF__CAMERA_SYNC_OUT = 16'h0260; localparam SYS_CLOCK_FREQ = 10000000; + wire sys_clk; //! 系统时钟 wire sys_rst_n; //! 系统复位 @@ -97,21 +103,60 @@ module Top ( reg [31:0] RegReaderBus_rd_data; //!寄存器读写-读数据总线 //模块寄存器读总线 - wire [31:0] rd_data_module_fpga_info; //! - wire [31:0] rd_data_module_ttlin; //! - wire [31:0] rd_data_module_timecode_in; //! - wire [31:0] rd_data_module_genlock_in; //! - wire [31:0] rd_data_module_internal_timecode; //! - wire [31:0] rd_data_module_internal_genlock; //! - wire [31:0] rd_data_module_internal_clock; //! - - - wire sig_ttlin1_module_ext; - wire sig_ttlin2_module_ext; - wire sig_ttlin3_module_ext; - wire sig_ttlin4_module_ext; - - + wire [31:0] rd_data_module_fpga_info; //! 模块寄存器数据总线读数据 + wire [31:0] rd_data_module_ttlin; //! 模块寄存器数据总线读数据 + wire [31:0] rd_data_module_timecode_in; //! 模块寄存器数据总线读数据 + wire [31:0] rd_data_module_genlock_in; //! 模块寄存器数据总线读数据 + wire [31:0] rd_data_module_internal_timecode; //! 模块寄存器数据总线读数据 + wire [31:0] rd_data_module_internal_genlock; //! 模块寄存器数据总线读数据 + wire [31:0] rd_data_module_internal_clock; //! 模块寄存器数据总线读数据 + wire [31:0] rd_data_module_ttlout1;//! 模块寄存器数据总线读数据 + wire [31:0] rd_data_module_ttlout2;//! 模块寄存器数据总线读数据 + wire [31:0] rd_data_module_ttlout3;//! 模块寄存器数据总线读数据 + wire [31:0] rd_data_module_ttlout4;//! 模块寄存器数据总线读数据 + wire [31:0] rd_data_module_timecode_out;//! 模块寄存器数据总线读数据 + wire [31:0] rd_data_module_genlock_out;//! 模块寄存器数据总线读数据 + wire [31:0] rd_data_module_camera_sync_out;//! 模块寄存器数据总线读数据 + + //内部信号 + wire signal_logic0; //! 逻辑0 + wire signal_logic1; //! 逻辑1 + wire signal_ttlin1; //! TTL输入1 + wire signal_ttlin2; //! TTL输入2 + wire signal_ttlin3; //! TTL输入3 + wire signal_ttlin4; //! TTL输入4 + wire signal_ext_genlock_freq; //! 外部GENLOCK频率信号 + wire signal_ext_timecode_freq; //! 外部时间码频率信号 + wire signal_internal_timecode_freq;//! 内部时间码频率信号 + wire signal_internal_genlock_freq;//! 内部GENLOCK频率信号 + wire signal_internal_freq_sig;//! 内部频率信号 + wire signal_sys_clk_output;//! 系统时钟输出 + wire signal_sys_genlock_output;//! 系统GENLOCK输出 + wire signal_sys_timecode_freq_output;//! 系统时间码频率输出 + wire signal_business_record_sig; //! 业务摄影状态信号 + wire signal_business_record_exposure_sig;//! 业务摄影拍照曝光信号 + + wire [31:0] sig_src; // 系统内部信号总线 + + assign sig_src[0] = signal_logic0; + assign sig_src[1] = signal_logic1; + assign sig_src[2] = signal_ttlin1; + assign sig_src[3] = signal_ttlin2; + assign sig_src[4] = signal_ttlin3; + assign sig_src[5] = signal_ttlin4; + assign sig_src[6] = signal_ext_genlock_freq; + assign sig_src[7] = signal_ext_timecode_freq; + assign sig_src[8] = signal_internal_timecode_freq; + assign sig_src[9] = signal_internal_genlock_freq; + assign sig_src[10] = signal_internal_freq_sig; + assign sig_src[11] = signal_sys_clk_output; + assign sig_src[12] = signal_sys_genlock_output; + assign sig_src[13] = signal_sys_timecode_freq_output; + assign sig_src[14] = signal_business_record_sig; + assign sig_src[15] = signal_business_record_exposure_sig; + + assign signal_logic0 = 1'b0; + assign signal_logic1 = 1'b1; //系统时钟源 SPLL spll ( .clkin1 (ex_clk), @@ -138,6 +183,7 @@ module Top ( ); // 数据路由 + wire [31:0] addr_group; assign addr_group = RegReaderBus_addr & 31'hFFFF_FFF0; always @(*) begin case (addr_group) @@ -155,17 +201,58 @@ module Top ( RegReaderBus_rd_data <= rd_data_module_internal_genlock; REGADDOFF__INTERNAL_CLOCK: RegReaderBus_rd_data <= rd_data_module_internal_clock; + REGADDOFF__TTLOUT1: + RegReaderBus_rd_data <= rd_data_module_ttlout1; + REGADDOFF__TTLOUT2: + RegReaderBus_rd_data <= rd_data_module_ttlout2; + REGADDOFF__TTLOUT3: + RegReaderBus_rd_data <= rd_data_module_ttlout3; + REGADDOFF__TTLOUT4: + RegReaderBus_rd_data <= rd_data_module_ttlout4; + REGADDOFF__TIMECODE_OUT: + RegReaderBus_rd_data <= rd_data_module_timecode_out; + REGADDOFF__GENLOCK_OUT: + RegReaderBus_rd_data <= rd_data_module_genlock_out; + REGADDOFF__CAMERA_SYNC_OUT: + RegReaderBus_rd_data <= rd_data_module_camera_sync_out; default: - RegReaderBus_rd_data = 0; + RegReaderBus_rd_data <= 0; endcase end - + /******************************************************************************* + * FPGA_INFO * + *******************************************************************************/ + zutils_register16 #( + .REG_START_ADD(REGADDOFF__FPGA_INFO), + .REG0_INIT(1), + .REG1_INIT(2), + .REG2_INIT(3), + .REG3_INIT(4), + .REG4_INIT(5), + .REG5_INIT(6), + .REG6_INIT(7), + .REG7_INIT(8), + .REG8_INIT(9), + .REG9_INIT(10), + .REGA_INIT(11), + .REGB_INIT(12), + .REGC_INIT(13), + .REGD_INIT(14), + .REGE_INIT(15), + .REGF_INIT(16) + ) test_reg ( + .clk(sys_clk), + .rst_n(sys_rst_n), + .addr(RegReaderBus_addr), + .wr_data(RegReaderBus_wr_data), + .wr_en(RegReaderBus_wr_en), + .rd_data(rd_data_module_fpga_info) + ); /******************************************************************************* * TTL输入模块 * *******************************************************************************/ - ttl_input #( .REG_START_ADD (REGADDOFF__TTLIN), @@ -191,13 +278,110 @@ module Top ( .ttlin4_state_led(sync_ttl_in4_state_led), //原始信号 - .sig_ttlin1(ISIG_ttlin1_module_ext), - .sig_ttlin2(ISIG_ttlin2_module_ext), - .sig_ttlin3(ISIG_ttlin3_module_ext), - .sig_ttlin4(ISIG_ttlin4_module_ext) + .sig_ttlin1(signal_ttlin1), + .sig_ttlin2(signal_ttlin2), + .sig_ttlin3(signal_ttlin3), + .sig_ttlin4(signal_ttlin4) ); - + /******************************************************************************* + * TTL_OUTPUT * + *******************************************************************************/ + + + + + ttl_output #( + .REG_START_ADD(REGADDOFF__TTLOUT1), + .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ), + .ID(1) + ) ttl_output_1 ( + .clk (sys_clk), + .rst_n(sys_rst_n), + + .addr(RegReaderBus_addr), + .wr_data(RegReaderBus_wr_data), + .wr_en(RegReaderBus_wr_en), + .rd_data(rd_data_module_ttlout1), + + .signal_in(sig_src), + + .ttloutput(sync_ttl_out1), + .ttloutput_state_led(sync_ttl_out1_state_led) + ); + + ttl_output #( + .REG_START_ADD(REGADDOFF__TTLOUT2), + .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ), + .ID(2) + ) ttl_output_2 ( + .clk (sys_clk), + .rst_n(sys_rst_n), + + .addr(RegReaderBus_addr), + .wr_data(RegReaderBus_wr_data), + .wr_en(RegReaderBus_wr_en), + .rd_data(rd_data_module_ttlout2), + + .signal_in(sig_src), + + .ttloutput(sync_ttl_out2), + .ttloutput_state_led(sync_ttl_out2_state_led) + ); + ttl_output #( + .REG_START_ADD(REGADDOFF__TTLOUT3), + .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ), + .ID(3) + ) ttl_output_3 ( + .clk (sys_clk), + .rst_n(sys_rst_n), + + .addr(RegReaderBus_addr), + .wr_data(RegReaderBus_wr_data), + .wr_en(RegReaderBus_wr_en), + .rd_data(rd_data_module_ttlout3), + + .signal_in(sig_src), + + .ttloutput(sync_ttl_out3), + .ttloutput_state_led(sync_ttl_out3_state_led) + ); + + ttl_output #( + .REG_START_ADD(REGADDOFF__TTLOUT4), + .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ), + .ID(4) + ) ttl_output_4 ( + .clk (sys_clk), + .rst_n(sys_rst_n), + + .addr(RegReaderBus_addr), + .wr_data(RegReaderBus_wr_data), + .wr_en(RegReaderBus_wr_en), + .rd_data(rd_data_module_ttlout4), + + .signal_in(sig_src), + + .ttloutput(sync_ttl_out4), + .ttloutput_state_led(sync_ttl_out4_state_led) + ); + + + assign debug_signal_output[0] = sys_clk; + assign debug_signal_output[1] = sync_ttl_in1; + assign debug_signal_output[2] = sync_ttl_in2; + assign debug_signal_output[3] = sync_ttl_in3; + assign debug_signal_output[4] = sync_ttl_in4; + assign debug_signal_output[5] = sync_ttl_out1; + assign debug_signal_output[6] = sync_ttl_out2; + assign debug_signal_output[7] = sync_ttl_out3; + assign debug_signal_output[8] = sync_ttl_out4; + assign debug_signal_output[9] = genlock_in_fsync; + assign debug_signal_output[10] = timecode_headphone_in; + assign debug_signal_output[11] = timecode_bnc_in; + assign debug_signal_output[12] = timecode_out_headphone; + assign debug_signal_output[13] = timecode_out_bnc; + assign debug_signal_output[15] = 0; endmodule diff --git a/source/src/zutils/zsimple_pll.v b/source/src/zutils/zsimple_pll.v new file mode 100644 index 0000000..27ca809 --- /dev/null +++ b/source/src/zutils/zsimple_pll.v @@ -0,0 +1,164 @@ +module zsimple_pll ( + input clk, //!clock input + input rst_n, //!asynchronous reset input, low active + + input insignal, //!输入信号 + input trigger_eage_type, + input wire [31:0] freq_division, + input wire [31:0] freq_multiplication, + input wire cfg_change, + output wire outsignal + ); + + // + // + //insignal + // -----> + // insignal_trigger_sig + // -------> + // insignal_division + // --------> + // insignal_multiplication + + + + wire insignal_rising_edge; //! 输入信号上升沿 + wire insignal_falling_edge; //! 输入信号下降沿 + wire insignal_trigger_sig; //! 触发信号 + wire module_reset; //! 模块内部复位信号 + + reg insignal_division; //! 输入信号分频后的信号 + reg insignal_multiplication;//! 输入信号倍频后的信号 + + + zutils_edge_detecter edge_detecter ( + .clk(clk), + .rst_n(rst_n), + .in_signal(insignal), + .in_signal_rising_edge(insignal_rising_edge), + .in_signal_falling_edge(insignal_falling_edge) + ); + + + assign insignal_trigger_sig = trigger_eage_type ? insignal_rising_edge : insignal_falling_edge; + assign module_reset = !rst_n || cfg_change; + + // 分频 + reg [31:0] insignal_division_cnt; + always @(posedge clk or posedge module_reset) begin + if (module_reset) begin + insignal_division_cnt <= 0; + insignal_division <= 0; + end + else begin + if(insignal_trigger_sig) begin + if(insignal_division_cnt >= freq_division) begin + insignal_division_cnt <= 0; + insignal_division <= 1; + end + else begin + insignal_division_cnt <= insignal_division_cnt + 1; + end + end + else begin + insignal_division <= 0; + end + end + end + + // 倍频 + // + // 触发计数 + // 更新计数 + // + // + + // 计数器 + reg [31:0] freq_cnt_cache; + reg [31:0] freq_cnt; + always @(posedge clk or posedge module_reset) begin + if (module_reset) begin + freq_cnt <= 0; + freq_cnt_cache <= 32'hffff_ffff; + end + else begin + if (insignal_division) begin + if(freq_cnt == 0) begin + freq_cnt_cache <= 32'hffff_ffff; + end + else begin + freq_cnt_cache <= freq_cnt; + end + freq_cnt <= 0; + end + else begin + freq_cnt <= freq_cnt + 1; + if(freq_cnt >= 32'hffff_ffff) begin + freq_cnt_cache <= 32'hffff_ffff; + freq_cnt <= 0; + end + end + end + end + + + reg [31:0] multiplication_state; + reg [31:0] multiplication_cnt; + reg [31:0] append_pluse_cnt; + + always @(posedge clk or posedge module_reset) begin + if (module_reset) begin + multiplication_cnt <= 0; + insignal_multiplication <= 0; + append_pluse_cnt <= 0; + multiplication_state <= 0; + end + else begin + case (multiplication_state) + 0 : begin // !默认状态 + if(insignal_division) begin + + //触发一次脉冲 + insignal_multiplication <= 1; + + if(freq_multiplication >= 1 && freq_cnt_cache != 32'hffff_ffff) begin + // 进入额外脉冲状态 + multiplication_state <= 1; + append_pluse_cnt <= 0; + multiplication_cnt <= 0; + end + end + else begin + insignal_multiplication <= 0; + end + end + 1 : begin + + if(append_pluse_cnt < freq_multiplication && freq_cnt_cache != 32'hffff_ffff && freq_multiplication > 0) begin + + if(multiplication_cnt < freq_cnt_cache) begin + multiplication_cnt <= multiplication_cnt + freq_multiplication + 1; + insignal_multiplication <= 0; + end + else begin + insignal_multiplication <= 1; + multiplication_cnt <= 0; + append_pluse_cnt <= append_pluse_cnt + 1; + end + + end + else begin + multiplication_state <= 0; + insignal_multiplication <= 0; + end + + end + default: begin + multiplication_state <= 0; + end + endcase + end + end + + assign outsignal = insignal_multiplication; +endmodule diff --git a/source/src/zutils/zutils_freq_detector.v b/source/src/zutils/zutils_freq_detector.v index 76e120a..4652d5e 100644 --- a/source/src/zutils/zutils_freq_detector.v +++ b/source/src/zutils/zutils_freq_detector.v @@ -4,7 +4,8 @@ // 2. 频率探测 // 3. 输出灯光控制 // -module zutils_freq_detector ( +module zutils_freq_detector + ( input clk, //! 时钟输入 input rst_n, //! 复位输入 @@ -46,8 +47,9 @@ module zutils_freq_detector ( end end - // 计数器 + + // 计数器 reg [31:0] pluse_width_cnt_reg; //!脉冲宽度计数 always @(posedge clk or negedge rst_n) begin @@ -62,6 +64,10 @@ module zutils_freq_detector ( end else begin pluse_width_cnt_reg <= pluse_width_cnt_reg + 1; + if(pluse_width_cnt_reg >= 32'd11000000) begin //TODO:支持可配置 + pluse_width_cnt <= 32'hffff_ffff; + pluse_width_cnt_reg <= 0; + end end end end