From 4777fcba6e321f3e0b29841d031597ef546461ac Mon Sep 17 00:00:00 2001 From: zhaohe Date: Sun, 10 Mar 2024 19:15:21 +0800 Subject: [PATCH] v0 --- camera_light_src_timing_controller_fpga.pds | 172 +++----- ipcore/SPLL/.last_generated | 2 +- ipcore/SPLL/SPLL.idf | 490 +++++++++++---------- ipcore/SPLL/SPLL.v | 6 +- ipcore/SPLL/SPLL_tb.v | 1 + ipcore/SPLL/SPLL_tmpl.v | 3 +- ipcore/SPLL/SPLL_tmpl.vhdl | 6 +- ipcore/SPLL/generate.log | 4 +- source/bak/internal_timecode_generator.v | 2 +- source/src/business/record_sig_generator.v | 2 +- source/src/config.v | 65 +-- source/src/internal/internal_clock_generator.v | 2 +- source/src/internal/internal_genlock_generator.v | 2 +- source/src/internal/internal_timecode_generator.v | 2 +- source/src/output/light_src_ctrl.v | 18 +- source/src/output/ttl_output_ctrl.v | 47 +- source/src/spi_reg_bus.v | 17 +- source/src/timecode/timecode_basesig_generator.v | 2 +- source/src/timecode/timecode_decoder.v | 2 +- source/src/timecode/timecode_generator.v | 2 +- .../src/timecode/timecode_sample_sig_generator.v | 2 +- source/src/timecode/timecode_serialization.v | 2 +- source/src/top.v | 96 +++- source/src/trigger_source/internal_trigger_clk.v | 4 +- .../trigger_source/trigger_source_base_module.v | 3 +- source/src/xsync_internal_generator.v | 2 +- source/src/zutils/zutils_debug_pwm_generator.v | 2 +- source/src/zutils/zutils_genlock_clk_generator.v | 2 +- source/src/zutils/zutils_muti_debug_signal_gen.v | 2 +- source/src/zutils/zutils_pluse_generator.v | 2 +- source/src/zutils/zutils_pwm_generator.v | 2 +- source/src/zutils/zutils_pwm_generator_advanced.v | 2 +- .../zutils/zutils_smpte_timecode_clk_generator.v | 2 +- source/src/zutils/zutils_timecode_convert.v | 2 +- .../src/zutils/zutils_timecode_serial_data_gen.v | 2 +- source/test/test_timecode_generator.v | 2 +- 36 files changed, 499 insertions(+), 477 deletions(-) diff --git a/camera_light_src_timing_controller_fpga.pds b/camera_light_src_timing_controller_fpga.pds index ee5d141..95f690d 100644 --- a/camera_light_src_timing_controller_fpga.pds +++ b/camera_light_src_timing_controller_fpga.pds @@ -1,5 +1,5 @@ (_flow fab_demo "2021.1-SP7" - (_comment "Generated by Fabric Compiler (version on 2021.1-SP7) at Sun Mar 10 18:02:35 2024") + (_comment "Generated by Fabric Compiler (version on 2021.1-SP7) at Sun Mar 10 19:15:07 2024") (_version "1.0.5") (_status "initial") (_project @@ -19,7 +19,7 @@ (_input (_file "source/src/top.v" + "Top:" (_format verilog) - (_timespec "2024-03-10T17:58:53") + (_timespec "2024-03-10T18:51:24") ) (_file "source/src/spi_reg_reader.v" (_format verilog) @@ -27,7 +27,7 @@ ) (_file "source/src/zutils/zutils_pluse_generator.v" (_format verilog) - (_timespec "2024-03-10T13:59:39") + (_timespec "2024-03-10T18:52:01") ) (_file "source/src/zutils/zutils_edge_detecter.v" (_format verilog) @@ -59,7 +59,7 @@ ) (_file "source/src/zutils/zutils_pwm_generator.v" (_format verilog) - (_timespec "2024-03-08T21:15:01") + (_timespec "2024-03-10T18:52:01") ) (_file "source/src/zutils/zutils_reset_sig_gen.v" (_format verilog) @@ -75,15 +75,15 @@ ) (_file "source/src/zutils/zutils_muti_debug_signal_gen.v" (_format verilog) - (_timespec "2024-03-08T21:15:01") + (_timespec "2024-03-10T18:52:01") ) (_file "source/src/xsync_internal_generator.v" (_format verilog) - (_timespec "2024-03-08T21:15:01") + (_timespec "2024-03-10T18:52:01") ) (_file "source/src/zutils/zutils_pwm_generator_advanced.v" (_format verilog) - (_timespec "2024-03-08T21:15:01") + (_timespec "2024-03-10T18:52:01") ) (_file "source/src/zutils/zutils_register_advanced.v" (_format verilog) @@ -91,7 +91,7 @@ ) (_file "source/src/zutils/zutils_genlock_clk_generator.v" (_format verilog) - (_timespec "2024-03-08T21:15:01") + (_timespec "2024-03-10T18:52:01") ) (_file "source/src/zutils/zutils_multiplexer_32t1_v2.v" (_format verilog) @@ -103,7 +103,7 @@ ) (_file "source/src/zutils/zutils_smpte_timecode_clk_generator.v" (_format verilog) - (_timespec "2024-03-08T21:15:01") + (_timespec "2024-03-10T18:52:01") ) (_file "source/src/timecode/timecode_nextcode.v" (_format verilog) @@ -111,23 +111,23 @@ ) (_file "source/src/timecode/timecode_basesig_generator.v" (_format verilog) - (_timespec "2024-03-08T21:15:01") + (_timespec "2024-03-10T18:52:01") ) (_file "source/src/timecode/timecode_serialization.v" (_format verilog) - (_timespec "2024-03-08T21:15:01") + (_timespec "2024-03-10T18:52:01") ) (_file "source/src/timecode/timecode_generator.v" (_format verilog) - (_timespec "2024-03-08T21:15:01") + (_timespec "2024-03-10T18:52:01") ) (_file "source/src/timecode/timecode_decoder.v" (_format verilog) - (_timespec "2024-03-08T21:15:01") + (_timespec "2024-03-10T18:52:01") ) (_file "source/src/timecode/timecode_sample_sig_generator.v" (_format verilog) - (_timespec "2024-03-08T21:15:01") + (_timespec "2024-03-10T18:52:01") ) (_file "source/src/zutils/ztuils_sig_devide.v" (_format verilog) @@ -159,31 +159,31 @@ ) (_file "source/src/spi_reg_bus.v" (_format verilog) - (_timespec "2024-03-10T17:19:50") + (_timespec "2024-03-10T18:37:55") ) (_file "source/src/internal/internal_timecode_generator.v" (_format verilog) - (_timespec "2024-03-08T21:15:01") + (_timespec "2024-03-10T18:52:01") ) (_file "source/src/internal/internal_clock_generator.v" (_format verilog) - (_timespec "2024-03-10T16:40:22") + (_timespec "2024-03-10T18:52:01") ) (_file "source/src/internal/internal_genlock_generator.v" (_format verilog) - (_timespec "2024-03-08T21:15:01") + (_timespec "2024-03-10T18:52:01") ) (_file "source/src/business/record_sig_generator.v" (_format verilog) - (_timespec "2024-03-08T21:15:01") + (_timespec "2024-03-10T18:52:01") ) (_file "source/src/zutils/zutils_debug_pwm_generator.v" (_format verilog) - (_timespec "2024-03-10T11:13:27") + (_timespec "2024-03-10T18:52:01") ) (_file "source/src/trigger_source/internal_trigger_clk.v" (_format verilog) - (_timespec "2024-03-10T17:37:47") + (_timespec "2024-03-10T19:03:17") ) (_file "source/src/zutils/zutils_trigger_sig_gen.v" (_format verilog) @@ -191,16 +191,32 @@ ) (_file "source/src/trigger_source/trigger_source_base_module.v" (_format verilog) - (_timespec "2024-03-10T18:02:05") + (_timespec "2024-03-10T18:52:01") + ) + (_file "source/src/output/light_src_ctrl.v" + (_format verilog) + (_timespec "2024-03-10T19:06:04") + ) + (_file "source/src/output/ttl_output_ctrl.v" + (_format verilog) + (_timespec "2024-03-10T19:14:59") + ) + (_file "source/src/zutils/zutils_pluse_generator_v2.v" + (_format verilog) + (_timespec "2024-03-10T14:04:31") + ) + (_file "source/src/zutils/zutils_pwm_generator_v2.v" + (_format verilog) + (_timespec "2024-03-10T13:37:24") ) ) ) (_widget wgt_my_ips_src (_input (_ip "ipcore/SPLL/SPLL.idf" - (_timespec "2024-03-08T21:15:01") + (_timespec "2024-03-10T18:50:53") (_ip_source_item "ipcore/SPLL/SPLL.v" - (_timespec "2024-03-08T21:15:01") + (_timespec "2024-03-10T18:50:53") ) ) (_ip "ipcore/genlock_sig_gen_pll/genlock_sig_gen_pll.idf" @@ -248,7 +264,7 @@ ) (_file "source/test/test_timecode_generator.v" (_format verilog) - (_timespec "2024-03-08T21:15:01") + (_timespec "2024-03-10T18:52:01") ) (_file "source/test/test_timecode_decoder.v" + "test_timecode_decoder:" (_format verilog) @@ -263,17 +279,17 @@ (_db_output (_file "compile/Top_comp.adf" (_format adif) - (_timespec "2024-03-10T18:02:11") + (_timespec "2024-03-10T19:15:06") ) ) (_output (_file "compile/Top.cmr" (_format verilog) - (_timespec "2024-03-10T18:02:11") + (_timespec "2024-03-10T19:15:05") ) (_file "compile/cmr.db" (_format text) - (_timespec "2024-03-10T18:02:11") + (_timespec "2024-03-10T19:15:06") ) ) ) @@ -283,29 +299,9 @@ ) (_task tsk_synthesis (_command cmd_synthesize - (_gci_state (_integer 2)) + (_gci_state (_integer 0)) (_option ads (_switch ON)) (_option selected_syn_tool_opt (_integer 2)) - (_db_output - (_file "synthesize/Top_syn.adf" - (_format adif) - (_timespec "2024-03-10T18:02:16") - ) - ) - (_output - (_file "synthesize/Top_syn.vm" - (_format structural_verilog) - (_timespec "2024-03-10T18:02:16") - ) - (_file "synthesize/Top.snr" - (_format text) - (_timespec "2024-03-10T18:02:17") - ) - (_file "synthesize/snr.db" - (_format text) - (_timespec "2024-03-10T18:02:17") - ) - ) ) (_widget wgt_tech_view (_attribute _click_to_run (_switch ON)) @@ -320,34 +316,14 @@ ) (_task tsk_devmap (_command cmd_devmap - (_gci_state (_integer 2)) - (_db_output - (_file "device_map/Top_map.adf" - (_format adif) - (_timespec "2024-03-10T18:02:19") - ) - ) - (_output - (_file "device_map/Top_dmr.prt" - (_format text) - (_timespec "2024-03-10T18:02:19") - ) - (_file "device_map/Top.dmr" - (_format text) - (_timespec "2024-03-10T18:02:19") - ) - (_file "device_map/dmr.db" - (_format text) - (_timespec "2024-03-10T18:02:20") - ) - ) + (_gci_state (_integer 0)) ) (_widget wgt_edit_placement_cons (_attribute _click_to_run (_switch ON)) (_input (_file "device_map/camera_light_src_timing_controller_fpga.pcf" (_format pcf) - (_timespec "2024-03-10T18:02:19") + (_timespec "2024-03-10T19:13:18") ) ) ) @@ -357,40 +333,8 @@ ) (_task tsk_pnr (_command cmd_pnr - (_gci_state (_integer 2)) + (_gci_state (_integer 0)) (_option mode (_string "fast")) - (_db_output - (_file "place_route/Top_pnr.adf" - (_format adif) - (_timespec "2024-03-10T18:02:28") - ) - ) - (_output - (_file "place_route/Top.prr" - (_format text) - (_timespec "2024-03-10T18:02:28") - ) - (_file "place_route/Top_prr.prt" - (_format text) - (_timespec "2024-03-10T18:02:28") - ) - (_file "place_route/clock_utilization.txt" - (_format text) - (_timespec "2024-03-10T18:02:28") - ) - (_file "place_route/Top_plc.adf" - (_format adif) - (_timespec "2024-03-10T18:02:24") - ) - (_file "place_route/Top_pnr.netlist" - (_format text) - (_timespec "2024-03-10T18:02:28") - ) - (_file "place_route/prr.db" - (_format text) - (_timespec "2024-03-10T18:02:29") - ) - ) ) (_widget wgt_power_calculator (_attribute _click_to_run (_switch ON)) @@ -419,25 +363,7 @@ ) (_task tsk_gen_bitstream (_command cmd_gen_bitstream - (_gci_state (_integer 2)) - (_output - (_file "generate_bitstream/Top.sbit" - (_format text) - (_timespec "2024-03-10T18:02:35") - ) - (_file "generate_bitstream/Top.smsk" - (_format text) - (_timespec "2024-03-10T18:02:35") - ) - (_file "generate_bitstream/Top.bgr" - (_format text) - (_timespec "2024-03-10T18:02:35") - ) - (_file "generate_bitstream/bgr.db" - (_format text) - (_timespec "2024-03-10T18:02:35") - ) - ) + (_gci_state (_integer 0)) ) ) ) diff --git a/ipcore/SPLL/.last_generated b/ipcore/SPLL/.last_generated index 8ec0a2e..a4edacb 100644 --- a/ipcore/SPLL/.last_generated +++ b/ipcore/SPLL/.last_generated @@ -1,2 +1,2 @@ -2024-01-11 09:39 +2024-03-10 18:50 rev_1 \ No newline at end of file diff --git a/ipcore/SPLL/SPLL.idf b/ipcore/SPLL/SPLL.idf index e584f38..e0d9529 100644 --- a/ipcore/SPLL/SPLL.idf +++ b/ipcore/SPLL/SPLL.idf @@ -15,211 +15,245 @@ - RST_ENABLE_basicPage + DYNAMIC_CLKIN_EN_advancedPage false - CLKOUT0_REQ_PHASE_basicPage - 0.0000 - 4 + DYNAMIC_DUTY2_EN_advancedPage + false - RSTODIV_ENABLE_advancedPage - false + STATIC_DUTY4_basicPage + 16 - STATIC_RATIOF_basicPage + STATIC_DUTY0_basicPage 24 - CLKOUT3_REQ_FREQ_basicPage - 50.0000 - 4 + STATIC_RATIO3_advancedPage + 16 - CLKOUT4_REQ_PHASE_basicPage - 0.0000 - 4 + STATIC_RATIOF_basicPage + 24 - CLKOUT1_REQ_DUTY_basicPage + CLKIN_BYPASS_EN_advancedPage + false + + + CLKOUT2_REQ_DUTY_basicPage 50.0000 4 - FEEDBACK_DELAY_ENABLE_advancedPage + DEVICE_PGL35 false - DYNAMIC_RATIO0_EN_advancedPage + CLKSWITCH_FLAG_ENABLE_advancedPage false - DYNAMIC_CLKIN_EN_basicPage + CLK_CAS3_EN_advancedPage false - CLKOUT0_EN_basicPage - true - - - DYNAMIC_PHASE0_EN_advancedPage - false + STATIC_PHASE1_basicPage + 16 - STATIC_RATIO2_advancedPage - 16 + CLKOUT4_REQ_DUTY_basicPage + 50.0000 + 4 - CLKOUT3_EN_basicPage + DYNAMIC_RATIOF_EN_advancedPage false - LOOP_MAPPING_EN_advancedPage + FBMODE_basicPage false - STATIC_PHASE3_basicPage + STATIC_PHASE1_advancedPage 16 - STATIC_DUTY0_basicPage - 24 - - - STATIC_RATIOM_advancedPage - 1 + STATIC_RATIO1_advancedPage + 16 - CLKOUT2_EN_basicPage + CLKOUT1_EN_basicPage true - STATIC_DUTY0_advancedPage - 16 - - - PFDEN_EN_advancedPage + CLKIN_SEL_EN_ENABLE_advancedPage false - FBDIV_SEL_basicPage - 0 + DYNAMIC_PHASE4_EN_advancedPage + false - CLKOUT4_REQ_FREQ_basicPage - 50.0000 + CLKOUT1_REQ_PHASE_basicPage + 0.0000 4 - CLKOUT4_GATE_EN_advancedPage + VCODIV2_ENABLE_advancedPage false - CLKIN_SEL_ENABLE_advancedPage + PFDEN_EN_advancedPage false - CLKOUT5_EN_advancedPage + FBMODE_advancedPage false - CLK_CAS4_EN_advancedPage + STATIC_DUTY1_basicPage + 60 + + + CLKOUT5_GATE_EN_advancedPage false - CLKOUT5_SEL_advancedPage - 0 + CLKOUT0_REQ_FREQ_basicPage + 25.0000 + 4 + + + STATIC_PHASE4_basicPage + 16 STATIC_DUTYF_basicPage 24 - STATIC_RATIO3_advancedPage + STATIC_RATIOF_advancedPage 16 - DYNAMIC_PHASE1_EN_advancedPage + CLKOUT0_EXT_GATE_EN_advancedPage false - STATIC_DUTY1_advancedPage + CLKOUT3_GATE_EN_basicPage + false + + + DEVICE_PGL22 + true + + + CLKOUT2_GATE_EN_basicPage + false + + + STATIC_DUTY2_advancedPage 16 - CLKOUT2_REQ_PHASE_basicPage + CLKOUT0_REQ_PHASE_basicPage 0.0000 4 - CLKOUT4_EN_advancedPage - false + STATIC_RATIO0_basicPage + 24 - CLKOUT3_GATE_EN_advancedPage + DYNAMIC_DUTY0_EN_advancedPage false - FBMODE_advancedPage + CLKOUT0_EXT_EN_advancedPage false - CLKIN_BYPASS_EN_basicPage + DYNAMIC_RATIO3_EN_advancedPage false - DYNAMIC_RATIO4_EN_advancedPage + DYNAMIC_PHASE_EN_advancedPage false - CLKSWITCH_FLAG_ENABLE_advancedPage + DYNAMIC_RATIO2_EN_advancedPage false - PLL_PWD_ENABLE_advancedPage + CLK_CAS4_EN_advancedPage false - MODE + STATIC_RATIO4_advancedPage + 16 + + + CLKOUT0_EN_advancedPage + true + + + STATIC_DUTY0_advancedPage + 16 + + + STATIC_RATIOI_basicPage + 2 + + + MODE_CFG + 0 + + + DYNAMIC_RATIO4_EN_advancedPage false - STATIC_RATIO4_advancedPage + STATIC_PHASE4_advancedPage 16 - DYNAMIC_RATIO2_EN_advancedPage + CLK_CAS1_EN_basicPage false - CLKOUT1_REQ_PHASE_basicPage - 0.0000 + CLKOUT2_EN_basicPage + true + + + CLKOUT1_REQ_FREQ_basicPage + 10.0000 4 - CLK_CAS2_EN_basicPage + PLL_PWD_ENABLE_basicPage false - CLKOUT3_EN_advancedPage - false + STATIC_RATIO2_basicPage + 120 - STATIC_PHASE4_advancedPage - 16 + STATIC_RATIO1_basicPage + 60 - CLKIN_FREQ_basicPage - 50.0000 - 4 + STATIC_RATIO4_basicPage + 16 - STATIC_RATIO0_basicPage - 24 + STATIC_PHASE0_basicPage + 16 - CLK_CAS4_EN_basicPage + CLKIN_BYPASS_EN_basicPage false @@ -228,19 +262,15 @@ 4 - PLL_PWD_ENABLE_basicPage - false - - - CLKOUT0_GATE_EN_basicPage + CLKOUT2_GATE_EN_advancedPage false - CLKOUT4_EN_basicPage + CLKOUT0_EXT_GATE_EN_basicPage false - SHOW_SETTING_EN_basicPage + LOOP_MAPPING_EN_advancedPage false @@ -249,254 +279,240 @@ 4 - CLKOUT2_GATE_EN_advancedPage - false - - - STATIC_RATIO2_basicPage - 120 + CLKIN_FREQ_basicPage + 50.0000 + 4 - DYNAMIC_PHASE2_EN_advancedPage + CLKOUT0_GATE_EN_advancedPage false - CLKOUT1_REQ_FREQ_basicPage - 10.0000 - 4 + CLKOUT4_EN_advancedPage + false - CLKIN_BYPASS_EN_advancedPage + RST_ENABLE_basicPage false - STATIC_RATIOM_basicPage - 1 + SHOW_SETTING_EN_basicPage + false - CLKOUT1_GATE_EN_basicPage + DYNAMIC_DUTY4_EN_advancedPage false - CLKIN_SEL_ENABLE_basicPage + FEEDBACK_DELAY_ENABLE_basicPage false - CLKOUT1_GATE_EN_advancedPage + DYNAMIC_RATIO1_EN_advancedPage false - DYNAMIC_PHASE_EN_advancedPage + DYNAMIC_RATIOI_EN_advancedPage false - DYNAMIC_LOOP_EN_advancedPage + DYNAMIC_CLKIN_EN_basicPage false - CLKOUT3_GATE_EN_basicPage + CLK_CAS1_EN_advancedPage false - STATIC_DUTY3_basicPage + STATIC_PHASE3_basicPage 16 - FEEDBACK_DELAY_VALUE_advancedPage - 0.000 - 3 + CLKSWITCH_FLAG_ENABLE_basicPage + false - CLKOUT0_REQ_FREQ_basicPage - 25.0000 - 4 + STATIC_DUTY2_basicPage + 120 CLKOUT4_GATE_EN_basicPage false - STATIC_RATIO4_basicPage - 16 + CLKOUT0_EXT_EN_basicPage + false - CLKOUT0_EXT_GATE_EN_basicPage - false + CLKOUT3_EN_basicPage + true - CLKOUT0_EXT_EN_advancedPage + DYNAMIC_PHASE0_EN_advancedPage false - CLKOUT2_REQ_DUTY_basicPage + CLKOUT1_REQ_DUTY_basicPage 50.0000 4 - CLKOUT2_GATE_EN_basicPage + CLKIN_SEL_ENABLE_basicPage false - RST_ENABLE_advancedPage - false + FBDIV_SEL_advancedPage + 0 - CLKOUT2_EN_advancedPage - false + STATIC_PHASE2_advancedPage + 16 - FBMODE_basicPage + DYNAMIC_PHASE2_EN_advancedPage false - STATIC_DUTY3_advancedPage - 16 - - - STATIC_DUTY2_advancedPage - 16 + STATIC_RATIOM_advancedPage + 1 - STATIC_RATIOI_advancedPage - 2 + CLK_CAS4_EN_basicPage + false - FBDIV_SEL_advancedPage - 0 + DYNAMIC_LOOP_EN_advancedPage + false - DYNAMIC_PHASE3_EN_advancedPage + CLKIN_SEL_ENABLE_advancedPage false - CLKIN_SEL_EN_ENABLE_basicPage + CLK_CAS2_EN_basicPage false - CLKOUT4_REQ_DUTY_basicPage - 50.0000 - 4 + FBDIV_SEL_basicPage + 0 - FEEDBACK_DELAY_VALUE_basicPage + FEEDBACK_DELAY_VALUE_advancedPage 0.000 3 - STATIC_PHASE1_advancedPage - 16 + STATIC_RATIOM_basicPage + 1 DYNAMIC_DUTY1_EN_advancedPage false - CLKSWITCH_FLAG_ENABLE_basicPage - false + STATIC_PHASE2_basicPage + 16 - DYNAMIC_RATIOM_EN_advancedPage + DYNAMIC_PHASE3_EN_advancedPage false - DEVICE_PGL22 - true + CLKOUT5_SEL_advancedPage + 0 - STATIC_PHASE2_basicPage - 16 + CLK_CAS3_EN_basicPage + false - FEEDBACK_DELAY_ENABLE_basicPage - false + BANDWIDTH_basicPage + OPTIMIZED - STATIC_DUTY4_basicPage + STATIC_RATIO2_advancedPage 16 - DYNAMIC_RATIOI_EN_advancedPage + RST_ENABLE_advancedPage false - CLK_CAS2_EN_advancedPage + CLKOUT4_GATE_EN_advancedPage false - VCODIV2_ENABLE_advancedPage + DYNAMIC_RATIOM_EN_advancedPage false - CLKOUT0_EXT_EN_basicPage + CLKOUT0_GATE_EN_basicPage false - MODE_CFG - 0 - - - BANDWIDTH_advancedPage - OPTIMIZED + CLKOUT4_EN_basicPage + false STATIC_RATIO3_basicPage - 16 + 6 - STATIC_PHASE0_advancedPage - 16 + FB_MODE_basicPage + 0 - STATIC_PHASE1_basicPage - 16 + CLKOUT1_GATE_EN_advancedPage + false - DYNAMIC_CLKIN_EN_advancedPage + CLKOUT1_GATE_EN_basicPage false - DEVICE_PGL35 + CLKOUT3_REQ_FREQ_basicPage + 100.0000 + 4 + + + CLKIN_SEL_EN_ENABLE_basicPage false - STATIC_RATIO1_advancedPage + STATIC_PHASE3_advancedPage 16 - CLKOUT0_EXT_GATE_EN_advancedPage + PLL_PWD_ENABLE_advancedPage false - CLKOUT0_REQ_DUTY_basicPage - 50.0000 - 4 - - - DYNAMIC_DUTY2_EN_advancedPage + DYNAMIC_RATIO0_EN_advancedPage false - STATIC_DUTY4_advancedPage - 16 + CLKOUT0_REQ_DUTY_basicPage + 50.0000 + 4 - STATIC_RATIO0_advancedPage + STATIC_DUTY3_advancedPage 16 - FB_MODE_advancedPage - 0 + CLK_CAS2_EN_advancedPage + false - STATIC_RATIOF_advancedPage - 16 + CLKOUT1_EN_advancedPage + false - STATIC_RATIOI_basicPage - 2 + BANDWIDTH_advancedPage + OPTIMIZED - DYNAMIC_PHASE4_EN_advancedPage + RSTODIV_ENABLE_advancedPage false @@ -505,113 +521,97 @@ 4 - DYNAMIC_RATIO1_EN_advancedPage + DEVICE_PGL12 false - STATIC_DUTY2_basicPage - 120 - - - STATIC_PHASE3_advancedPage - 16 - - - STATIC_PHASE2_advancedPage - 16 - - - DYNAMIC_RATIO3_EN_advancedPage + CLKOUT3_EN_advancedPage false - DYNAMIC_DUTY3_EN_advancedPage + CLKOUT5_EN_advancedPage false - BANDWIDTH_basicPage - OPTIMIZED - - - STATIC_PHASE0_basicPage - 16 - - - STATIC_RATIO1_basicPage - 60 + CLKOUT2_REQ_PHASE_basicPage + 0.0000 + 4 - DYNAMIC_RATIOF_EN_advancedPage - false + STATIC_DUTY3_basicPage + 6 - CLKOUT5_GATE_EN_advancedPage + FEEDBACK_DELAY_ENABLE_advancedPage false - FB_MODE_basicPage - 0 + CLKOUT4_REQ_FREQ_basicPage + 50.0000 + 4 - CLK_CAS1_EN_advancedPage + CLKOUT2_EN_advancedPage false - CLKOUT0_EN_advancedPage - true + CLKOUT3_REQ_PHASE_basicPage + 0.0000 + 4 - CLKOUT1_EN_advancedPage - false + STATIC_RATIO0_advancedPage + 16 - CLK_CAS1_EN_basicPage + MODE false - CLKOUT1_EN_basicPage - true + CLKOUT4_REQ_PHASE_basicPage + 0.0000 + 4 - DYNAMIC_DUTY4_EN_advancedPage - false + STATIC_DUTY4_advancedPage + 16 - CLKOUT3_REQ_PHASE_basicPage - 0.0000 - 4 + CLKOUT0_EN_basicPage + true - DYNAMIC_DUTY0_EN_advancedPage - false + FEEDBACK_DELAY_VALUE_basicPage + 0.000 + 3 - CLKOUT0_GATE_EN_advancedPage + CLKOUT3_GATE_EN_advancedPage false - DEVICE_PGL12 - false + FB_MODE_advancedPage + 0 - CLK_CAS3_EN_basicPage - false + STATIC_RATIOI_advancedPage + 2 - CLK_CAS3_EN_advancedPage - false + STATIC_DUTY1_advancedPage + 16 - CLKIN_SEL_EN_ENABLE_advancedPage + DYNAMIC_DUTY3_EN_advancedPage false - STATIC_PHASE4_basicPage + STATIC_PHASE0_advancedPage 16 - STATIC_DUTY1_basicPage - 60 + DYNAMIC_PHASE1_EN_advancedPage + false @@ -645,6 +645,12 @@ output right + + clkout3 + clkout3 + output + right + diff --git a/ipcore/SPLL/SPLL.v b/ipcore/SPLL/SPLL.v index c71a4d2..e73351a 100644 --- a/ipcore/SPLL/SPLL.v +++ b/ipcore/SPLL/SPLL.v @@ -22,6 +22,7 @@ module SPLL ( clkout0, clkout1, clkout2, + clkout3, pll_lock ); @@ -31,13 +32,13 @@ module SPLL ( localparam integer STATIC_RATIO0 = 24; localparam integer STATIC_RATIO1 = 60; localparam integer STATIC_RATIO2 = 120; - localparam integer STATIC_RATIO3 = 16; + localparam integer STATIC_RATIO3 = 6; localparam integer STATIC_RATIO4 = 16; localparam integer STATIC_RATIOF = 24; localparam integer STATIC_DUTY0 = 24; localparam integer STATIC_DUTY1 = 60; localparam integer STATIC_DUTY2 = 120; - localparam integer STATIC_DUTY3 = 16; + localparam integer STATIC_DUTY3 = 6; localparam integer STATIC_DUTY4 = 16; localparam integer STATIC_DUTYF = 24; localparam integer STATIC_PHASE0 = 16; @@ -103,6 +104,7 @@ module SPLL ( output clkout0; output clkout1; output clkout2; + output clkout3; output pll_lock; diff --git a/ipcore/SPLL/SPLL_tb.v b/ipcore/SPLL/SPLL_tb.v index 60dd5fe..5fb7f90 100644 --- a/ipcore/SPLL/SPLL_tb.v +++ b/ipcore/SPLL/SPLL_tb.v @@ -178,6 +178,7 @@ SPLL U_SPLL ( .clkout0(clkout0), .clkout1(clkout1), .clkout2(clkout2), + .clkout3(clkout3), .clkin1(clkin1), diff --git a/ipcore/SPLL/SPLL_tmpl.v b/ipcore/SPLL/SPLL_tmpl.v index 0d0a436..615a35d 100644 --- a/ipcore/SPLL/SPLL_tmpl.v +++ b/ipcore/SPLL/SPLL_tmpl.v @@ -11,5 +11,6 @@ SPLL the_instance_name ( .pll_lock(pll_lock), // output .clkout0(clkout0), // output .clkout1(clkout1), // output - .clkout2(clkout2) // output + .clkout2(clkout2), // output + .clkout3(clkout3) // output ); diff --git a/ipcore/SPLL/SPLL_tmpl.vhdl b/ipcore/SPLL/SPLL_tmpl.vhdl index c75c06f..8b100be 100644 --- a/ipcore/SPLL/SPLL_tmpl.vhdl +++ b/ipcore/SPLL/SPLL_tmpl.vhdl @@ -12,7 +12,8 @@ COMPONENT SPLL pll_lock : OUT STD_LOGIC; clkout0 : OUT STD_LOGIC; clkout1 : OUT STD_LOGIC; - clkout2 : OUT STD_LOGIC + clkout2 : OUT STD_LOGIC; + clkout3 : OUT STD_LOGIC ); END COMPONENT; @@ -23,5 +24,6 @@ the_instance_name : SPLL pll_lock => pll_lock, clkout0 => clkout0, clkout1 => clkout1, - clkout2 => clkout2 + clkout2 => clkout2, + clkout3 => clkout3 ); diff --git a/ipcore/SPLL/generate.log b/ipcore/SPLL/generate.log index 7504850..97b0200 100644 --- a/ipcore/SPLL/generate.log +++ b/ipcore/SPLL/generate.log @@ -1,7 +1,7 @@ IP Generator (Version 2021.1-SP7 build 86875) Check out license ... -Start generating at 2024-01-11 09:39 -Instance: SPLL (D:\workspace\fpga_demo\camera_light_src_timing_controller_fpga\ipcore\SPLL\SPLL.idf) +Start generating at 2024-03-10 18:50 +Instance: SPLL (D:\workspace\p_camera_light_source_timing_controller\camera_light_src_timing_controller_fpga\ipcore\SPLL\SPLL.idf) IP: PLL (1.5) Part: Logos-PGL22G-MBG324--6 Create directory 'rtl' ... diff --git a/source/bak/internal_timecode_generator.v b/source/bak/internal_timecode_generator.v index e57956e..bf5cbf1 100644 --- a/source/bak/internal_timecode_generator.v +++ b/source/bak/internal_timecode_generator.v @@ -1,6 +1,6 @@ // module internal_timecode_generator #( -// parameter SYS_CLOCK_FREQ = 10000000 +// parameter SYS_CLOCK_FREQ = 100000000 // ) ( // input clk, //clock input // input rst_n, //asynchronous reset input, low active diff --git a/source/src/business/record_sig_generator.v b/source/src/business/record_sig_generator.v index 825b35c..58d0fbe 100644 --- a/source/src/business/record_sig_generator.v +++ b/source/src/business/record_sig_generator.v @@ -1,6 +1,6 @@ module record_sig_generator #( parameter REG_START_ADD = 0, - parameter SYS_CLOCK_FREQ = 10000000, + parameter SYS_CLOCK_FREQ = 100000000, parameter TEST = 0 ) ( input clk, diff --git a/source/src/config.v b/source/src/config.v index 9408efb..076c9b6 100644 --- a/source/src/config.v +++ b/source/src/config.v @@ -6,20 +6,21 @@ `define REGADDOFF__INTERNAL_CLK 16'h1020 `define REGADDOFF__INTERNAL_TRIGGER 16'h1040 -`define REGADDOFF__TRIGGER_IN0 16'h2000 -`define REGADDOFF__TRIGGER_IN1 16'h2020 -`define REGADDOFF__TRIGGER_IN2 16'h2040 -`define REGADDOFF__TRIGGER_IN3 16'h2060 +`define REGADDOFF__TRIGGER_IN1 16'h2000 +`define REGADDOFF__TRIGGER_IN2 16'h2020 +`define REGADDOFF__TRIGGER_IN3 16'h2040 +`define REGADDOFF__TRIGGER_IN4 16'h2060 -`define REGADDOFF__LIGHT_CTROL_MODULE0 16'h3000 -`define REGADDOFF__LIGHT_CTROL_MODULE1 16'h3020 -`define REGADDOFF__LIGHT_CTROL_MODULE2 16'h3040 -`define REGADDOFF__LIGHT_CTROL_MODULE3 16'h3060 -`define REGADDOFF__TTL_OUTPUT_MODULE0 16'h4000 -`define REGADDOFF__TTL_OUTPUT_MODULE1 16'h4020 -`define REGADDOFF__TTL_OUTPUT_MODULE2 16'h4040 -`define REGADDOFF__TTL_OUTPUT_MODULE3 16'h4060 +`define REGADDOFF__LIGHT_CTROL_MODULE1 16'h3000 +`define REGADDOFF__LIGHT_CTROL_MODULE2 16'h3020 +`define REGADDOFF__LIGHT_CTROL_MODULE3 16'h3040 +`define REGADDOFF__LIGHT_CTROL_MODULE4 16'h3060 + +`define REGADDOFF__TTL_OUTPUT_MODULE1 16'h4000 +`define REGADDOFF__TTL_OUTPUT_MODULE2 16'h4020 +`define REGADDOFF__TTL_OUTPUT_MODULE3 16'h4040 +`define REGADDOFF__TTL_OUTPUT_MODULE4 16'h4060 /******************************************************************************* * 部分寄存器初始化数值 * @@ -34,33 +35,33 @@ `define SIG_LOGIC1 32'd1 `define SIG_INTERNAL_CLK 32'd2 -`define SIG_INTERNAL_CLK_I0 32'd3 -`define SIG_INTERNAL_CLK_I1 32'd4 -`define SIG_INTERNAL_CLK_I2 32'd5 -`define SIG_INTERNAL_CLK_I3 32'd6 +`define SIG_INTERNAL_CLK_I1 32'd3 +`define SIG_INTERNAL_CLK_I2 32'd4 +`define SIG_INTERNAL_CLK_I3 32'd5 +`define SIG_INTERNAL_CLK_I4 32'd6 `define SIG_EXT_TRIGGER_1 32'd7 -`define SIG_EXT_TRIGGER_1_I0 32'd8 -`define SIG_EXT_TRIGGER_1_I1 32'd9 -`define SIG_EXT_TRIGGER_1_I2 32'd10 -`define SIG_EXT_TRIGGER_1_I3 32'd11 +`define SIG_EXT_TRIGGER_1_I1 32'd8 +`define SIG_EXT_TRIGGER_1_I2 32'd9 +`define SIG_EXT_TRIGGER_1_I3 32'd10 +`define SIG_EXT_TRIGGER_1_I4 32'd11 `define SIG_EXT_TRIGGER_2 32'd12 -`define SIG_EXT_TRIGGER_2_I0 32'd13 -`define SIG_EXT_TRIGGER_2_I1 32'd14 -`define SIG_EXT_TRIGGER_2_I2 32'd15 -`define SIG_EXT_TRIGGER_2_I3 32'd16 +`define SIG_EXT_TRIGGER_2_I1 32'd13 +`define SIG_EXT_TRIGGER_2_I2 32'd14 +`define SIG_EXT_TRIGGER_2_I3 32'd15 +`define SIG_EXT_TRIGGER_2_I4 32'd16 `define SIG_EXT_TRIGGER_3 32'd17 -`define SIG_EXT_TRIGGER_3_I0 32'd18 -`define SIG_EXT_TRIGGER_3_I1 32'd19 -`define SIG_EXT_TRIGGER_3_I2 32'd20 -`define SIG_EXT_TRIGGER_3_I3 32'd21 +`define SIG_EXT_TRIGGER_3_I1 32'd18 +`define SIG_EXT_TRIGGER_3_I2 32'd19 +`define SIG_EXT_TRIGGER_3_I3 32'd20 +`define SIG_EXT_TRIGGER_3_I4 32'd21 `define SIG_EXT_TRIGGER_4 32'd22 -`define SIG_EXT_TRIGGER_4_I0 32'd23 -`define SIG_EXT_TRIGGER_4_I1 32'd24 -`define SIG_EXT_TRIGGER_4_I2 32'd25 -`define SIG_EXT_TRIGGER_4_I3 32'd26 +`define SIG_EXT_TRIGGER_4_I1 32'd23 +`define SIG_EXT_TRIGGER_4_I2 32'd24 +`define SIG_EXT_TRIGGER_4_I3 32'd25 +`define SIG_EXT_TRIGGER_4_I4 32'd26 diff --git a/source/src/internal/internal_clock_generator.v b/source/src/internal/internal_clock_generator.v index bae3a0b..faf7cf6 100644 --- a/source/src/internal/internal_clock_generator.v +++ b/source/src/internal/internal_clock_generator.v @@ -1,7 +1,7 @@ `include "../config.v" module internal_clock_generator #( parameter REG_START_ADD = 0, - parameter SYS_CLOCK_FREQ = 10000000 + parameter SYS_CLOCK_FREQ = 100000000 ) ( input clk, //! 时钟输入 diff --git a/source/src/internal/internal_genlock_generator.v b/source/src/internal/internal_genlock_generator.v index 898c4ac..dbd9443 100644 --- a/source/src/internal/internal_genlock_generator.v +++ b/source/src/internal/internal_genlock_generator.v @@ -1,7 +1,7 @@ `include "../config.v" module internal_genlock_generator #( parameter REG_START_ADD = 0, - parameter SYS_CLOCK_FREQ = 10000000 + parameter SYS_CLOCK_FREQ = 100000000 ) ( input clk, //! 时钟输入 diff --git a/source/src/internal/internal_timecode_generator.v b/source/src/internal/internal_timecode_generator.v index 73a8e12..f6527f2 100644 --- a/source/src/internal/internal_timecode_generator.v +++ b/source/src/internal/internal_timecode_generator.v @@ -1,6 +1,6 @@ module internal_timecode_generator #( parameter REG_START_ADD = 0, - parameter SYS_CLOCK_FREQ = 10000000, + parameter SYS_CLOCK_FREQ = 100000000, parameter ID = 1 ) ( input clk, //clock input diff --git a/source/src/output/light_src_ctrl.v b/source/src/output/light_src_ctrl.v index 8e2b833..16a3307 100644 --- a/source/src/output/light_src_ctrl.v +++ b/source/src/output/light_src_ctrl.v @@ -1,7 +1,7 @@ `include "../config.v" module light_src_ctrl #( parameter REG_START_ADD = 0, - parameter SYS_CLOCK_FREQ = 10000000, + parameter SYS_CLOCK_FREQ = 100000000, parameter ID = 1 ) ( input clk, //clock input @@ -73,18 +73,22 @@ module light_src_ctrl #( ); //!寄存器写入逻辑 + + localparam pluse_interval_init_val = 1 * (SYS_CLOCK_FREQ / 1000000); //1us + localparam pluse_width_initval = 30 * (SYS_CLOCK_FREQ / 1000000); //1us + always @(posedge clk or negedge rst_n) begin if (!rst_n) begin - reg1_source_select <= 0; + reg1_source_select <= `SIG_INTERNAL_CLK; reg2_en_sig_ctrl_mode <= 0; reg3_light_intensity_ctrl_mode <= 0; reg4_trigger_mode_pluse_num <= 1; - reg5_trigger_mode_pluse_interval <= 10; - reg6_trigger_mode_pluse_width <= 300; - reg7_trigger_mode_first_pluse_offset <= 10 * ID + ((ID - 1) * 300); + reg5_trigger_mode_pluse_interval <= pluse_interval_init_val; + reg6_trigger_mode_pluse_width <= pluse_width_initval; + reg7_trigger_mode_first_pluse_offset <= pluse_interval_init_val * ID + ((ID - 1) * pluse_width_initval); reg8_trigger_mode_output_polarity <= 1; - reg9_light_intensity_cnt <= 32'd500; - regA_light_driver_freq_cnt <= (32'd500 * 2); + reg9_light_intensity_cnt <= (SYS_CLOCK_FREQ / 100000 / 2); //100k + regA_light_driver_freq_cnt <= (SYS_CLOCK_FREQ / 100000); //100k regC_freq_detect_bias <= `FREQ_DETECT_BIAS_DEFAULT; end else begin if (reg_wr_sig) begin diff --git a/source/src/output/ttl_output_ctrl.v b/source/src/output/ttl_output_ctrl.v index 03753c7..c581c77 100644 --- a/source/src/output/ttl_output_ctrl.v +++ b/source/src/output/ttl_output_ctrl.v @@ -1,7 +1,7 @@ `include "../config.v" module ttl_output_ctrl #( parameter REG_START_ADD = 0, - parameter SYS_CLOCK_FREQ = 10000000, + parameter SYS_CLOCK_FREQ = 32'd100_000_000, parameter ID = 1 ) ( input clk, //clock input @@ -14,7 +14,8 @@ module ttl_output_ctrl #( output wire [31:0] rd_data, - input wire [3:0] lt_en_sig, + input wire [ 3:0] lt_en_sig, + input wire [31:0] sys_internal_sig_bus, output wire diff_out, output wire optocoupler_out @@ -24,10 +25,11 @@ module ttl_output_ctrl #( * 寄存器列表 * *******************************************************************************/ - reg [31:0] reg1_output_ctrl_mode; //!0:绑定模式 - reg [31:0] reg2_lt_en_bind; //!绑定的光源信号 - reg [31:0] reg3_lt_en_offset; //!快门信号与曝光信号偏移 - + reg [31:0] reg1_output_ctrl_mode; //!0:绑定模式 + reg [31:0] reg2_lt_en_bind; //!绑定的光源信号 + reg [31:0] reg3_lt_en_offset; //!快门信号与曝光信号偏移 + reg [31:0] reg4_in_sig_select; //!转发模式下信号选择器 + wire [31:0] reg_wr_index; //!TTLOUT_寄存器自动赋值选择器 zutils_register_advanced #( @@ -43,6 +45,7 @@ module ttl_output_ctrl #( .reg1(reg1_output_ctrl_mode), .reg2(reg2_lt_en_bind), .reg3(reg3_lt_en_offset), + .reg4(reg4_in_sig_select), .reg_wr_sig(reg_wr_sig), .reg_index (reg_wr_index) @@ -53,7 +56,7 @@ module ttl_output_ctrl #( if (!rst_n) begin reg1_output_ctrl_mode <= 0; reg2_lt_en_bind <= 32'hffff_ffff; - reg3_lt_en_offset <= 32'd10; //10us + reg3_lt_en_offset <= (SYS_CLOCK_FREQ / 32'd1000_000); //1us end else begin if (reg_wr_sig) begin @@ -61,6 +64,7 @@ module ttl_output_ctrl #( 32'h1: reg1_output_ctrl_mode <= reg_wr_index; 32'h2: reg2_lt_en_bind <= reg_wr_index; 32'h3: reg3_lt_en_offset <= reg_wr_index; + 32'h4: reg4_in_sig_select <= reg_wr_index; default: begin end endcase @@ -68,17 +72,17 @@ module ttl_output_ctrl #( end end - reg trigger_sig; //! 触发信号 - reg [31:0] cnt; //! 计数器 - reg output_sig_0; //!延后的触发信号 - wire output_sig; //!最终输出的信号 - reg [31:0] lt_en_offset_offset; //!延后偏移缓存 + reg trigger_sig; //! 触发信号 + reg [31:0] cnt; //! 计数器 + reg output_sig_0; //!延后的触发信号 + reg output_sig; //!最终输出的信号 + reg [31:0] lt_en_offset_offset; //!延后偏移缓存 always @(posedge clk or negedge rst_n) begin if (!rst_n) begin trigger_sig <= 0; end else begin - trigger_sig = (lt_en_sig[0] & reg2_lt_en_bind[0]) // + trigger_sig <= (lt_en_sig[0] & reg2_lt_en_bind[0]) // | (lt_en_sig[1] & reg2_lt_en_bind[1]) // | (lt_en_sig[2] & reg2_lt_en_bind[2]) // | (lt_en_sig[3] & reg2_lt_en_bind[3]); @@ -113,7 +117,22 @@ module ttl_output_ctrl #( end end - assign output_sig = output_sig_0 & trigger_sig; + zutils_multiplexer_32t1 signal_in_multiplexer ( + .chooseindex(reg4_in_sig_select), + .signal (sys_internal_sig_bus), + .signalout (signal_in_choose) + ); + + always @(*) begin + case (reg1_output_ctrl_mode) + 0: output_sig <= output_sig_0 & trigger_sig; + 1: output_sig <= signal_in_choose; + default: begin + output_sig <= 0; + end + endcase + end + assign diff_out = output_sig; assign optocoupler_out = output_sig; diff --git a/source/src/spi_reg_bus.v b/source/src/spi_reg_bus.v index e043a46..8d3a92f 100644 --- a/source/src/spi_reg_bus.v +++ b/source/src/spi_reg_bus.v @@ -17,20 +17,20 @@ module spi_reg_bus ( input [31:0] rd_data_internal_trigger, input [31:0] rd_data_internal_clk, - input [31:0] rd_data_trigger_in0, input [31:0] rd_data_trigger_in1, input [31:0] rd_data_trigger_in2, input [31:0] rd_data_trigger_in3, + input [31:0] rd_data_trigger_in4, - input [31:0] rd_data_light_ctrol_module0, input [31:0] rd_data_light_ctrol_module1, input [31:0] rd_data_light_ctrol_module2, input [31:0] rd_data_light_ctrol_module3, + input [31:0] rd_data_light_ctrol_module4, - input [31:0] rd_data_ttl_output_module0, input [31:0] rd_data_ttl_output_module1, input [31:0] rd_data_ttl_output_module2, - input [31:0] rd_data_ttl_output_module3 + input [31:0] rd_data_ttl_output_module3, + input [31:0] rd_data_ttl_output_module4 ); reg [31:0] rd_data; spi_reg_reader spi_reg_reader_inst ( @@ -56,20 +56,23 @@ module spi_reg_bus ( `REGADDOFF__INTERNAL_TRIGGER: rd_data <= rd_data_internal_trigger; `REGADDOFF__INTERNAL_CLK: rd_data <= rd_data_internal_clk; - `REGADDOFF__TRIGGER_IN0: rd_data <= rd_data_trigger_in0; `REGADDOFF__TRIGGER_IN1: rd_data <= rd_data_trigger_in1; `REGADDOFF__TRIGGER_IN2: rd_data <= rd_data_trigger_in2; `REGADDOFF__TRIGGER_IN3: rd_data <= rd_data_trigger_in3; + `REGADDOFF__TRIGGER_IN4: rd_data <= rd_data_trigger_in4; + - `REGADDOFF__LIGHT_CTROL_MODULE0: rd_data <= rd_data_light_ctrol_module0; `REGADDOFF__LIGHT_CTROL_MODULE1: rd_data <= rd_data_light_ctrol_module1; `REGADDOFF__LIGHT_CTROL_MODULE2: rd_data <= rd_data_light_ctrol_module2; `REGADDOFF__LIGHT_CTROL_MODULE3: rd_data <= rd_data_light_ctrol_module3; + `REGADDOFF__LIGHT_CTROL_MODULE4: rd_data <= rd_data_light_ctrol_module4; + - `REGADDOFF__TTL_OUTPUT_MODULE0: rd_data <= rd_data_ttl_output_module0; `REGADDOFF__TTL_OUTPUT_MODULE1: rd_data <= rd_data_ttl_output_module1; `REGADDOFF__TTL_OUTPUT_MODULE2: rd_data <= rd_data_ttl_output_module2; `REGADDOFF__TTL_OUTPUT_MODULE3: rd_data <= rd_data_ttl_output_module3; + `REGADDOFF__TTL_OUTPUT_MODULE4: rd_data <= rd_data_ttl_output_module4; + default: rd_data <= 0; endcase diff --git a/source/src/timecode/timecode_basesig_generator.v b/source/src/timecode/timecode_basesig_generator.v index 9737183..ed279a4 100644 --- a/source/src/timecode/timecode_basesig_generator.v +++ b/source/src/timecode/timecode_basesig_generator.v @@ -1,6 +1,6 @@ module timecode_basesig_generator #( - parameter SYS_CLOCK_FREQ = 10000000 + parameter SYS_CLOCK_FREQ = 100000000 ) ( input clk, diff --git a/source/src/timecode/timecode_decoder.v b/source/src/timecode/timecode_decoder.v index 68d98e6..986afc6 100644 --- a/source/src/timecode/timecode_decoder.v +++ b/source/src/timecode/timecode_decoder.v @@ -1,5 +1,5 @@ module timecode_decoder #( - parameter SYS_CLOCK_FREQ = 10000000 + parameter SYS_CLOCK_FREQ = 100000000 ) ( input clk, //clock input input rst_n, //asynchronous reset input, low active diff --git a/source/src/timecode/timecode_generator.v b/source/src/timecode/timecode_generator.v index c79de9f..f3caf30 100644 --- a/source/src/timecode/timecode_generator.v +++ b/source/src/timecode/timecode_generator.v @@ -1,6 +1,6 @@ module timecode_generator #( - parameter SYS_CLOCK_FREQ = 10000000 + parameter SYS_CLOCK_FREQ = 100000000 ) ( input clk, //clock input input rst_n, //asynchronous reset input, low active diff --git a/source/src/timecode/timecode_sample_sig_generator.v b/source/src/timecode/timecode_sample_sig_generator.v index 63050b8..c37c6bd 100644 --- a/source/src/timecode/timecode_sample_sig_generator.v +++ b/source/src/timecode/timecode_sample_sig_generator.v @@ -1,5 +1,5 @@ module timecode_sample_sig_generator #( - parameter SYS_CLOCK_FREQ = 10000000, + parameter SYS_CLOCK_FREQ = 100000000, parameter SAMPLE_RATE = 8547 ) ( input clk, //clock input diff --git a/source/src/timecode/timecode_serialization.v b/source/src/timecode/timecode_serialization.v index a748e57..92136fb 100644 --- a/source/src/timecode/timecode_serialization.v +++ b/source/src/timecode/timecode_serialization.v @@ -1,6 +1,6 @@ module timecode_serialization #( - parameter SYS_CLOCK_FREQ = 10000000 + parameter SYS_CLOCK_FREQ = 100000000 ) ( input clk, input rst_n, diff --git a/source/src/top.v b/source/src/top.v index 0237563..1dc73a8 100644 --- a/source/src/top.v +++ b/source/src/top.v @@ -79,8 +79,6 @@ module Top ( ); - localparam SYS_CLOCK_FREQ = 10000000; - wire sys_clk; //! 系统时钟 wire sys_rst_n; //! 系统复位 @@ -98,24 +96,26 @@ module Top ( .pll_lock(pll_lock), .clkout0 (sys_clk_25m), .clkout1 (sys_clk_10m), - .clkout2 (sys_clk_5m) + .clkout2 (sys_clk_5m), + .clkout3 (sys_clk_100m) ); - assign sys_clk = sys_clk_10m; + localparam SYS_CLOCK_FREQ = 100000000; + assign sys_clk = sys_clk_100m; // assign sys_rst_n = ex_rst_n & pll_lock; assign sys_rst_n = pll_lock; wire [31:0] rd_data_fpga_info; wire [31:0] rd_data_internal_clk; wire [31:0] rd_data_internal_trigger; - wire [31:0] rd_data_trigger_in0; + wire [31:0] rd_data_trigger_in4; wire [31:0] rd_data_trigger_in1; wire [31:0] rd_data_trigger_in2; wire [31:0] rd_data_trigger_in3; - wire [31:0] rd_data_light_ctrol_module0; + wire [31:0] rd_data_light_ctrol_module4; wire [31:0] rd_data_light_ctrol_module1; wire [31:0] rd_data_light_ctrol_module2; wire [31:0] rd_data_light_ctrol_module3; - wire [31:0] rd_data_ttl_output_module0; + wire [31:0] rd_data_ttl_output_module4; wire [31:0] rd_data_ttl_output_module1; wire [31:0] rd_data_ttl_output_module2; wire [31:0] rd_data_ttl_output_module3; @@ -134,15 +134,15 @@ module Top ( .rd_data_fpga_info (rd_data_fpga_info), .rd_data_internal_clk (rd_data_internal_clk), .rd_data_internal_trigger (rd_data_internal_trigger), - .rd_data_trigger_in0 (rd_data_trigger_in0), + .rd_data_trigger_in4 (rd_data_trigger_in4), .rd_data_trigger_in1 (rd_data_trigger_in1), .rd_data_trigger_in2 (rd_data_trigger_in2), .rd_data_trigger_in3 (rd_data_trigger_in3), - .rd_data_light_ctrol_module0(rd_data_light_ctrol_module0), + .rd_data_light_ctrol_module4(rd_data_light_ctrol_module4), .rd_data_light_ctrol_module1(rd_data_light_ctrol_module1), .rd_data_light_ctrol_module2(rd_data_light_ctrol_module2), .rd_data_light_ctrol_module3(rd_data_light_ctrol_module3), - .rd_data_ttl_output_module0 (rd_data_ttl_output_module0), + .rd_data_ttl_output_module4 (rd_data_ttl_output_module4), .rd_data_ttl_output_module1 (rd_data_ttl_output_module1), .rd_data_ttl_output_module2 (rd_data_ttl_output_module2), .rd_data_ttl_output_module3 (rd_data_ttl_output_module3) @@ -182,6 +182,12 @@ module Top ( assign sig_bus[`SIG_LOGIC0] = 0; assign sig_bus[`SIG_LOGIC1] = 1; + wire [3:0] lt_en_sig_bus; + assign lt_en_sig_bus[0] = lt1_en; + assign lt_en_sig_bus[1] = lt2_en; + assign lt_en_sig_bus[2] = lt3_en; + assign lt_en_sig_bus[3] = lt4_en; + /******************************************************************************* * INTERNAL_CLK * @@ -218,19 +224,69 @@ module Top ( .in_sig_1(internal_trigger_clk_ins_output_sig), .out_trigger_sig (sig_bus[`SIG_INTERNAL_CLK]), - .out_trigger_sig_index0(sig_bus[`SIG_INTERNAL_CLK_I0]), - .out_trigger_sig_index1(sig_bus[`SIG_INTERNAL_CLK_I1]), - .out_trigger_sig_index2(sig_bus[`SIG_INTERNAL_CLK_I2]), - .out_trigger_sig_index3(sig_bus[`SIG_INTERNAL_CLK_I3]) + .out_trigger_sig_index0(sig_bus[`SIG_INTERNAL_CLK_I1]), + .out_trigger_sig_index1(sig_bus[`SIG_INTERNAL_CLK_I2]), + .out_trigger_sig_index2(sig_bus[`SIG_INTERNAL_CLK_I3]), + .out_trigger_sig_index3(sig_bus[`SIG_INTERNAL_CLK_I4]) + ); + + // ttl_output_ctrl + + light_src_ctrl #( + .REG_START_ADD(`REGADDOFF__LIGHT_CTROL_MODULE1), + .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ), + .ID(1) + ) light_src_ctrl_1 ( + .clk (sys_clk), + .rst_n(sys_rst_n), + + .addr (RegReaderBus_addr), + .wr_data(RegReaderBus_wr_data), + .wr_en (RegReaderBus_wr_en), + .rd_data(rd_data_light_ctrol_module4), + + .signal_in(sig_bus), + + .lt_intensity_ctrl(lt1_intensity_ctrl), + .lt_en (lt1_en), + .lt_error_sig_in (lt1_error_sig_in) + ); + + + ttl_output_ctrl #( + .REG_START_ADD (`REGADDOFF__TTL_OUTPUT_MODULE1), + .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ) + ) ttl_output_ctrl_1 ( + .clk (sys_clk), + .rst_n(sys_rst_n), + + .addr (RegReaderBus_addr), + .wr_data(RegReaderBus_wr_data), + .wr_en (RegReaderBus_wr_en), + .rd_data(rd_data_ttl_output_module4), + + .sys_internal_sig_bus(sig_bus), + .lt_en_sig (lt_en_sig_bus), + + .diff_out (diff_out1), + .optocoupler_out(optocoupler_out1) ); - assign debug_bus[0] = internal_trigger_clk_ins_output_sig; - assign debug_bus[1] = sig_bus[`SIG_INTERNAL_CLK]; - assign debug_bus[2] = sig_bus[`SIG_INTERNAL_CLK_I0]; - assign debug_bus[3] = sig_bus[`SIG_INTERNAL_CLK_I1]; - assign debug_bus[4] = sig_bus[`SIG_INTERNAL_CLK_I2]; - assign debug_bus[5] = sig_bus[`SIG_INTERNAL_CLK_I3]; + assign debug_bus[0] = internal_trigger_clk_ins_output_sig; + assign debug_bus[1] = sig_bus[`SIG_INTERNAL_CLK]; + assign debug_bus[2] = sig_bus[`SIG_INTERNAL_CLK_I1]; + assign debug_bus[3] = sig_bus[`SIG_INTERNAL_CLK_I2]; + assign debug_bus[4] = sig_bus[`SIG_INTERNAL_CLK_I3]; + assign debug_bus[5] = sig_bus[`SIG_INTERNAL_CLK_I4]; + + assign debug_bus[6] = lt1_intensity_ctrl; + assign debug_bus[7] = lt1_en; + assign debug_bus[8] = lt1_error_sig_in; + assign debug_bus[9] = optocoupler_out1; + assign debug_bus[10] = diff_out1; + + // assign debug_bus[0] = sys_clk; // assign optocoupler_out1 = diff_in1; // assign optocoupler_out2 = diff_in2; diff --git a/source/src/trigger_source/internal_trigger_clk.v b/source/src/trigger_source/internal_trigger_clk.v index 6f067ec..3ee3931 100644 --- a/source/src/trigger_source/internal_trigger_clk.v +++ b/source/src/trigger_source/internal_trigger_clk.v @@ -1,7 +1,7 @@ `include "../config.v" module internal_trigger_clk #( parameter REG_START_ADD = 0, - parameter SYS_CLOCK_FREQ = 10000000 + parameter SYS_CLOCK_FREQ = 100000000 ) ( input clk, //! 时钟输入 @@ -48,7 +48,7 @@ module internal_trigger_clk #( always @(posedge clk or negedge rst_n) begin if (!rst_n) begin reg1_ctrl <= 0; - reg2_cfg_freq_cnt <= 32'd1000; //输出频率10khz + reg2_cfg_freq_cnt <= SYS_CLOCK_FREQ/10; //输出频率10hz reg3_cfg_pluse_cnt <= 32'd0; // end else begin if (reg_wr_sig) begin diff --git a/source/src/trigger_source/trigger_source_base_module.v b/source/src/trigger_source/trigger_source_base_module.v index d3df421..4514677 100644 --- a/source/src/trigger_source/trigger_source_base_module.v +++ b/source/src/trigger_source/trigger_source_base_module.v @@ -1,7 +1,7 @@ `include "../config.v" module trigger_source_base_module #( parameter REG_START_ADD = 0, - parameter SYS_CLOCK_FREQ = 10000000 + parameter SYS_CLOCK_FREQ = 100000000 ) ( input clk, //! 时钟输入 @@ -173,6 +173,7 @@ module trigger_source_base_module #( assign out_trigger_sig = signal_out_final; + zutils_edge_detecter cs_edge_detecter ( .clk (clk), .rst_n (rst_n), diff --git a/source/src/xsync_internal_generator.v b/source/src/xsync_internal_generator.v index ba50b72..05b4da6 100644 --- a/source/src/xsync_internal_generator.v +++ b/source/src/xsync_internal_generator.v @@ -38,7 +38,7 @@ // module xsync_internal_generator #( // parameter REG_START_ADD = 0, -// parameter SYS_CLOCK_FREQ = 10000000, +// parameter SYS_CLOCK_FREQ = 100000000, // parameter TEST = 0 // ) ( // input clk, //clock input diff --git a/source/src/zutils/zutils_debug_pwm_generator.v b/source/src/zutils/zutils_debug_pwm_generator.v index 9cab6fa..d4bccd9 100644 --- a/source/src/zutils/zutils_debug_pwm_generator.v +++ b/source/src/zutils/zutils_debug_pwm_generator.v @@ -1,5 +1,5 @@ module zutils_debug_pwm_generator #( - parameter SYS_CLOCK_FREQ = 10000000 + parameter SYS_CLOCK_FREQ = 100000000 ) ( input clk, input rst_n, diff --git a/source/src/zutils/zutils_genlock_clk_generator.v b/source/src/zutils/zutils_genlock_clk_generator.v index f05f3e5..041fb44 100644 --- a/source/src/zutils/zutils_genlock_clk_generator.v +++ b/source/src/zutils/zutils_genlock_clk_generator.v @@ -1,5 +1,5 @@ module zutils_genlock_clk_generator #( - parameter SYS_CLOCK_FREQ = 10000000 + parameter SYS_CLOCK_FREQ = 100000000 ) ( input clk, //clock input input rst_n, //asynchronous reset input, low active diff --git a/source/src/zutils/zutils_muti_debug_signal_gen.v b/source/src/zutils/zutils_muti_debug_signal_gen.v index cd51fef..791f4d6 100644 --- a/source/src/zutils/zutils_muti_debug_signal_gen.v +++ b/source/src/zutils/zutils_muti_debug_signal_gen.v @@ -1,5 +1,5 @@ module zutils_muti_debug_signal_gen #( - parameter SYS_CLOCK_FREQ = 10000000 + parameter SYS_CLOCK_FREQ = 100000000 ) ( input clk, input rst_n, diff --git a/source/src/zutils/zutils_pluse_generator.v b/source/src/zutils/zutils_pluse_generator.v index b30c8a9..fcdd172 100644 --- a/source/src/zutils/zutils_pluse_generator.v +++ b/source/src/zutils/zutils_pluse_generator.v @@ -1,5 +1,5 @@ module zutils_pluse_generator #( - parameter SYS_CLOCK_FREQ = 10000000 + parameter SYS_CLOCK_FREQ = 100000000 ) ( input clk, //clock input input rst_n, //asynchronous reset input, low active diff --git a/source/src/zutils/zutils_pwm_generator.v b/source/src/zutils/zutils_pwm_generator.v index ac8a19e..498215d 100644 --- a/source/src/zutils/zutils_pwm_generator.v +++ b/source/src/zutils/zutils_pwm_generator.v @@ -1,5 +1,5 @@ module zutils_pwm_generator #( - parameter SYS_CLOCK_FREQ = 10000000, + parameter SYS_CLOCK_FREQ = 100000000, parameter OUTPUT_FREQ = 1000 ) ( input clk, diff --git a/source/src/zutils/zutils_pwm_generator_advanced.v b/source/src/zutils/zutils_pwm_generator_advanced.v index e528220..27ced7a 100644 --- a/source/src/zutils/zutils_pwm_generator_advanced.v +++ b/source/src/zutils/zutils_pwm_generator_advanced.v @@ -1,5 +1,5 @@ module zutils_pwm_generator_advanced #( - parameter SYS_CLOCK_FREQ = 10000000, + parameter SYS_CLOCK_FREQ = 100000000, parameter OUTPUT_FREQ_P00 = 1000 //10.00HZ ) ( input clk, diff --git a/source/src/zutils/zutils_smpte_timecode_clk_generator.v b/source/src/zutils/zutils_smpte_timecode_clk_generator.v index 4ca24a5..4e648fe 100644 --- a/source/src/zutils/zutils_smpte_timecode_clk_generator.v +++ b/source/src/zutils/zutils_smpte_timecode_clk_generator.v @@ -1,5 +1,5 @@ module zutils_smpte_timecode_clk_generator #( - parameter SYS_CLOCK_FREQ = 10000000 + parameter SYS_CLOCK_FREQ = 100000000 ) ( input clk, //clock input input rst_n, //asynchronous reset input, low active diff --git a/source/src/zutils/zutils_timecode_convert.v b/source/src/zutils/zutils_timecode_convert.v index b84784d..87b6f04 100644 --- a/source/src/zutils/zutils_timecode_convert.v +++ b/source/src/zutils/zutils_timecode_convert.v @@ -14,7 +14,7 @@ module zutils_timecode_convert #( - parameter SYS_CLOCK_FREQ = 10000000 + parameter SYS_CLOCK_FREQ = 100000000 ) ( input clk, //clock input input rst_n, //asynchronous reset input, low active diff --git a/source/src/zutils/zutils_timecode_serial_data_gen.v b/source/src/zutils/zutils_timecode_serial_data_gen.v index 473097f..4879a8a 100644 --- a/source/src/zutils/zutils_timecode_serial_data_gen.v +++ b/source/src/zutils/zutils_timecode_serial_data_gen.v @@ -1,6 +1,6 @@ // module internal_timecode_generator #( -// parameter SYS_CLOCK_FREQ = 10000000 +// parameter SYS_CLOCK_FREQ = 100000000 // ) ( // input clk, //clock input // input rst_n, //asynchronous reset input, low active diff --git a/source/test/test_timecode_generator.v b/source/test/test_timecode_generator.v index 3d17edd..e1c939f 100644 --- a/source/test/test_timecode_generator.v +++ b/source/test/test_timecode_generator.v @@ -1,7 +1,7 @@ `timescale 10ns / 10ns module test_timecode_generator; // module timecode_generator #( -// parameter SYS_CLOCK_FREQ = 10000000 +// parameter SYS_CLOCK_FREQ = 100000000 // ) ( // input clk, //clock input // input rst_n, //asynchronous reset input, low active