From 2af77e0db1d1dbc9a1701a99120428a2b055ebb0 Mon Sep 17 00:00:00 2001 From: zhaohe Date: Sun, 10 Mar 2024 12:29:06 +0800 Subject: [PATCH] update --- camera_light_src_timing_controller_fpga.fdc | 4 +- camera_light_src_timing_controller_fpga.pds | 64 +++++---- pin.csv | 4 +- source/src/output/light_src_ctrl.v | 201 ++++++++++++++++++++++++++++ source/src/output/ttl_output.v | 201 ---------------------------- 5 files changed, 235 insertions(+), 239 deletions(-) create mode 100644 source/src/output/light_src_ctrl.v delete mode 100644 source/src/output/ttl_output.v diff --git a/camera_light_src_timing_controller_fpga.fdc b/camera_light_src_timing_controller_fpga.fdc index 5e8956b..1b941bf 100644 --- a/camera_light_src_timing_controller_fpga.fdc +++ b/camera_light_src_timing_controller_fpga.fdc @@ -21,13 +21,13 @@ define_attribute {p:spi_rx_pin} {PAP_IO_LOC} {R18} define_attribute {p:spi_rx_pin} {PAP_IO_VCCIO} {3.3} define_attribute {p:spi_rx_pin} {PAP_IO_STANDARD} {LVTTL33} define_attribute {p:uart_tx} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:uart_tx} {PAP_IO_LOC} {L18} +define_attribute {p:uart_tx} {PAP_IO_LOC} {L17} define_attribute {p:uart_tx} {PAP_IO_VCCIO} {3.3} define_attribute {p:uart_tx} {PAP_IO_STANDARD} {LVCMOS33} define_attribute {p:uart_tx} {PAP_IO_DRIVE} {4} define_attribute {p:uart_tx} {PAP_IO_SLEW} {SLOW} define_attribute {p:uart_rx} {PAP_IO_DIRECTION} {INPUT} -define_attribute {p:uart_rx} {PAP_IO_LOC} {L17} +define_attribute {p:uart_rx} {PAP_IO_LOC} {L18} define_attribute {p:uart_rx} {PAP_IO_VCCIO} {3.3} define_attribute {p:uart_rx} {PAP_IO_STANDARD} {LVTTL33} define_attribute {p:core_board_debug_led} {PAP_IO_DIRECTION} {OUTPUT} diff --git a/camera_light_src_timing_controller_fpga.pds b/camera_light_src_timing_controller_fpga.pds index c87c9a9..cf765db 100644 --- a/camera_light_src_timing_controller_fpga.pds +++ b/camera_light_src_timing_controller_fpga.pds @@ -1,5 +1,5 @@ (_flow fab_demo "2021.1-SP7" - (_comment "Generated by Fabric Compiler (version on 2021.1-SP7) at Sun Mar 10 11:54:51 2024") + (_comment "Generated by Fabric Compiler (version on 2021.1-SP7) at Sun Mar 10 12:19:08 2024") (_version "1.0.5") (_status "initial") (_project @@ -57,10 +57,6 @@ (_format verilog) (_timespec "2024-03-08T21:15:01") ) - (_file "source/src/output/ttl_output.v" - (_format verilog) - (_timespec "2024-03-08T21:15:01") - ) (_file "source/src/zutils/zutils_pwm_generator.v" (_format verilog) (_timespec "2024-03-08T21:15:01") @@ -216,7 +212,7 @@ (_input (_file "camera_light_src_timing_controller_fpga.fdc" (_format fdc) - (_timespec "2024-03-08T22:52:15") + (_timespec "2024-03-10T12:18:07") ) ) ) @@ -263,21 +259,21 @@ ) (_task tsk_compile (_command cmd_compile - (_gci_state (_integer 3)) + (_gci_state (_integer 2)) (_db_output (_file "compile/Top_comp.adf" (_format adif) - (_timespec "2024-03-10T11:41:33") + (_timespec "2024-03-10T12:18:42") ) ) (_output (_file "compile/Top.cmr" (_format verilog) - (_timespec "2024-03-10T11:41:33") + (_timespec "2024-03-10T12:18:42") ) (_file "compile/cmr.db" (_format text) - (_timespec "2024-03-10T11:41:33") + (_timespec "2024-03-10T12:18:42") ) ) ) @@ -287,27 +283,27 @@ ) (_task tsk_synthesis (_command cmd_synthesize - (_gci_state (_integer 3)) + (_gci_state (_integer 2)) (_option ads (_switch ON)) (_option selected_syn_tool_opt (_integer 2)) (_db_output (_file "synthesize/Top_syn.adf" (_format adif) - (_timespec "2024-03-10T11:41:40") + (_timespec "2024-03-10T12:18:49") ) ) (_output (_file "synthesize/Top_syn.vm" (_format structural_verilog) - (_timespec "2024-03-10T11:41:40") + (_timespec "2024-03-10T12:18:49") ) (_file "synthesize/Top.snr" (_format text) - (_timespec "2024-03-10T11:41:40") + (_timespec "2024-03-10T12:18:49") ) (_file "synthesize/snr.db" (_format text) - (_timespec "2024-03-10T11:41:40") + (_timespec "2024-03-10T12:18:49") ) ) ) @@ -324,25 +320,25 @@ ) (_task tsk_devmap (_command cmd_devmap - (_gci_state (_integer 3)) + (_gci_state (_integer 2)) (_db_output (_file "device_map/Top_map.adf" (_format adif) - (_timespec "2024-03-10T11:41:43") + (_timespec "2024-03-10T12:18:52") ) ) (_output (_file "device_map/Top_dmr.prt" (_format text) - (_timespec "2024-03-10T11:41:42") + (_timespec "2024-03-10T12:18:52") ) (_file "device_map/Top.dmr" (_format text) - (_timespec "2024-03-10T11:41:43") + (_timespec "2024-03-10T12:18:52") ) (_file "device_map/dmr.db" (_format text) - (_timespec "2024-03-10T11:41:43") + (_timespec "2024-03-10T12:18:52") ) ) ) @@ -351,7 +347,7 @@ (_input (_file "device_map/camera_light_src_timing_controller_fpga.pcf" (_format pcf) - (_timespec "2024-03-10T11:41:43") + (_timespec "2024-03-10T12:18:52") ) ) ) @@ -361,38 +357,38 @@ ) (_task tsk_pnr (_command cmd_pnr - (_gci_state (_integer 3)) + (_gci_state (_integer 2)) (_option mode (_string "fast")) (_db_output (_file "place_route/Top_pnr.adf" (_format adif) - (_timespec "2024-03-10T11:41:51") + (_timespec "2024-03-10T12:19:00") ) ) (_output (_file "place_route/Top.prr" (_format text) - (_timespec "2024-03-10T11:41:51") + (_timespec "2024-03-10T12:19:00") ) (_file "place_route/Top_prr.prt" (_format text) - (_timespec "2024-03-10T11:41:50") + (_timespec "2024-03-10T12:19:00") ) (_file "place_route/clock_utilization.txt" (_format text) - (_timespec "2024-03-10T11:41:50") + (_timespec "2024-03-10T12:19:00") ) (_file "place_route/Top_plc.adf" (_format adif) - (_timespec "2024-03-10T11:41:47") + (_timespec "2024-03-10T12:18:57") ) (_file "place_route/Top_pnr.netlist" (_format text) - (_timespec "2024-03-10T11:41:51") + (_timespec "2024-03-10T12:19:00") ) (_file "place_route/prr.db" (_format text) - (_timespec "2024-03-10T11:41:51") + (_timespec "2024-03-10T12:19:00") ) ) ) @@ -423,23 +419,23 @@ ) (_task tsk_gen_bitstream (_command cmd_gen_bitstream - (_gci_state (_integer 3)) + (_gci_state (_integer 2)) (_output (_file "generate_bitstream/Top.sbit" (_format text) - (_timespec "2024-03-10T11:41:58") + (_timespec "2024-03-10T12:19:08") ) (_file "generate_bitstream/Top.smsk" (_format text) - (_timespec "2024-03-10T11:41:58") + (_timespec "2024-03-10T12:19:08") ) (_file "generate_bitstream/Top.bgr" (_format text) - (_timespec "2024-03-10T11:41:58") + (_timespec "2024-03-10T12:19:08") ) (_file "generate_bitstream/bgr.db" (_format text) - (_timespec "2024-03-10T11:41:59") + (_timespec "2024-03-10T12:19:08") ) ) ) diff --git a/pin.csv b/pin.csv index 6409e8f..87ee38d 100644 --- a/pin.csv +++ b/pin.csv @@ -4,8 +4,8 @@ P17,spi_cs_pin ,INPUT L12,spi_clk_pin,INPUT R17,spi_tx_pin,OUTPUT R18,spi_rx_pin,INPUT -L18,uart_tx,OUTPUT -L17,uart_rx,INPUT +L17,uart_tx,OUTPUT +L18,uart_rx,INPUT T11,core_board_debug_led,OUTPUT M16,id[0],INPUT L16,id[1],INPUT diff --git a/source/src/output/light_src_ctrl.v b/source/src/output/light_src_ctrl.v new file mode 100644 index 0000000..3df5461 --- /dev/null +++ b/source/src/output/light_src_ctrl.v @@ -0,0 +1,201 @@ +`include "../config.v" +module ttl_output #( + parameter REG_START_ADD = 0, + parameter SYS_CLOCK_FREQ = 10000000, + parameter ID = 1 +) ( + input clk, //clock input + input rst_n, //asynchronous reset input, low active + + //寄存器读写接口 + input [31:0] addr, + input [31:0] wr_data, + input wr_en, + output wire [31:0] rd_data, + + input [31:0] signal_in, + + output ttloutput, //ttl输出信号 + output ttloutput_state_led //ttl输出状态信号 +); + + /******************************************************************************* + * 寄存器列表 * + *******************************************************************************/ + //!信号处理模式 0:固定输出低电平，1:固定输出高电平，2:分频倍频模式，3:转发模式，4:测试模式 + reg [31:0] reg_signal_process_mode; + //!TTLOUT_信号选择器 + reg [31:0] reg_input_signal_select; + //!TTLOUT_分频器 + reg [31:0] reg_pllout_freq_division_ctrl; + //!TTLOUT_频率倍增器 + reg [31:0] reg_pllout_freq_multiplication_ctrl; + //!TTLOUT_极性控制寄存器 + reg [31:0] reg_pllout_polarity_ctrl; + //!TTLOUT_触发信号边沿类型 + reg [31:0] reg_pllout_trigger_edge_select; + //!转发模式下的极性控制 + reg [31:0] reg_forward_mode_polarity_ctrl; + //!占位 + reg [31:0] reg_placeholder0; + // !频率探测偏差 + reg [31:0] reg_freq_detect_bias; + + //!输入信号频率探测 read only + wire [31:0] reg_sig_in_freq_detect; + //!输出信号频率探测 read only + wire [31:0] reg_sig_out_freq_detect; + + wire [31:0] reg_wr_index; //!寄存器写入时相对地址 + wire signal_in_choose; //!原始信号 + wire signal_in_af_pll; //!倍频后的信号 + wire signal_af_pll_af_polarity_ctrl; //!极性翻转后的信号 + wire signal_in_af_forward_mode_polarity_ctrl; //!转发模式下的输入信号 + wire signal_test; //!测试信号 + + + //信号流转图 + // + // signal_in[](原始信号) + // ---> reg_input_signal_select -->signal_in_choose(信号选择器) + // --> + // reg_pllout_trigger_edge_select + // reg_pllout_freq_division_ctrl ---> signal_in_af_pll(经分频倍频后的信号) + // reg_pllout_freq_multiplication_ctrl + // ---> signal_af_pll_af_polarity_ctrl + // + // + // 0:0 ---| + // 1:1 ---| + // 2:signal_af_pll_af_polarity_ctrl ---|--> + // 3:signal_in_af_forward_mode_polarity_ctrl ---| + // 4:test_sig ---| + // + + //!TTLOUT_寄存器自动赋值选择器 + zutils_register_advanced #( + .REG_START_ADD(REG_START_ADD) + ) _register ( + .clk (clk), + .rst_n (rst_n), + .addr (addr), + .wr_data (wr_data), + .wr_en (wr_en), + .rd_data (rd_data), + .reg1 (reg_signal_process_mode), + .reg2 (reg_input_signal_select), + .reg3 (reg_pllout_freq_division_ctrl), + .reg4 (reg_pllout_freq_multiplication_ctrl), + .reg5 (reg_pllout_polarity_ctrl), + .reg6 (reg_pllout_trigger_edge_select), + .reg7 (reg_forward_mode_polarity_ctrl), + .reg8 (reg_placeholder0), + .reg9 (reg_freq_detect_bias), + .regE (reg_sig_in_freq_detect), + .regF (reg_sig_out_freq_detect), + .reg_wr_sig(reg_wr_sig), + .reg_index (reg_wr_index) + ); + + //!寄存器写入逻辑 + always @(posedge clk or negedge rst_n) begin + if (!rst_n) begin + reg_signal_process_mode <= 0; + reg_input_signal_select <= 0; + reg_pllout_freq_division_ctrl <= 0; + reg_pllout_freq_multiplication_ctrl <= 0; + reg_pllout_polarity_ctrl <= 0; + reg_pllout_trigger_edge_select <= 1; + reg_forward_mode_polarity_ctrl <= 0; + reg_placeholder0 <= 0; + reg_freq_detect_bias <= `FREQ_DETECT_BIAS_DEFAULT; + end else begin + if (reg_wr_sig) begin + case (reg_wr_index) + 1: reg_signal_process_mode <= wr_data; + 2: reg_input_signal_select <= wr_data; + 3: reg_pllout_freq_division_ctrl <= wr_data; + 4: reg_pllout_freq_multiplication_ctrl <= wr_data; + 5: reg_pllout_polarity_ctrl <= wr_data; + 6: reg_pllout_trigger_edge_select <= wr_data; + 7: reg_forward_mode_polarity_ctrl <= wr_data; + 8: reg_placeholder0 <= wr_data; + 9: reg_freq_detect_bias <= wr_data; + default: begin + end + endcase + end + end + end + + //!信号选择器 + zutils_multiplexer_32t1 signal_in_multiplexer ( + .chooseindex(reg_input_signal_select), + .signal (signal_in), + .signalout (signal_in_choose) + ); + + //!pll信号处理 + zsimple_pll _simple_pll ( + .clk (clk), + .rst_n (rst_n), + .insignal (signal_in_choose), + .trigger_eage_type (reg_pllout_trigger_edge_select[0]), + .freq_detect_bias (reg_freq_detect_bias), + .freq_division (reg_pllout_freq_division_ctrl), + .freq_multiplication(reg_pllout_freq_multiplication_ctrl), + .polarity_ctrl (reg_pllout_polarity_ctrl[0]), + .cfg_change (reg_wr_sig), + .outsignal (signal_in_af_pll) + ); + + + //!100HZ测试信号发生器 + zutils_pwm_generator #( + .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ), + .OUTPUT_FREQ(100) + ) pwm100hz_gen ( + .clk (clk), + .rst_n (rst_n), + .output_signal(signal_test) + ); + + + + assign signal_in_af_forward_mode_polarity_ctrl = signal_in_choose ^ reg_forward_mode_polarity_ctrl[0]; + + //!信号输出选择器 + zutils_multiplexer_8t1 signal_output_multiplexer ( + .chooseindex(reg_signal_process_mode), + .signal0 (1'b0), + .signal1 (1'b1), + .signal2 (signal_in_af_pll), + .signal3 (signal_in_af_forward_mode_polarity_ctrl), + .signal4 (signal_test), + .signal5 (1'b0), + .signal6 (1'b0), + .signal7 (1'b0), + .signalout (ttloutput) + ); + + // + // + zutils_freq_detector_v2 in_freq_detector ( + .clk (clk), + .rst_n (rst_n), + .freq_detect_bias(reg_freq_detect_bias), + .pluse_input (signal_in_choose), + .pluse_width_cnt (reg_sig_in_freq_detect) + ); + + zutils_freq_detector_v2 output_freq_detector ( + .clk (clk), + .rst_n (rst_n), + .freq_detect_bias(reg_freq_detect_bias), + .pluse_input (ttloutput), + .pluse_width_cnt (reg_sig_out_freq_detect) + ); + assign ttloutput_state_led = 1; + + +endmodule diff --git a/source/src/output/ttl_output.v b/source/src/output/ttl_output.v deleted file mode 100644 index 3df5461..0000000 --- a/source/src/output/ttl_output.v +++ /dev/null @@ -1,201 +0,0 @@ -`include "../config.v" -module ttl_output #( - parameter REG_START_ADD = 0, - parameter SYS_CLOCK_FREQ = 10000000, - parameter ID = 1 -) ( - input clk, //clock input - input rst_n, //asynchronous reset input, low active - - //寄存器读写接口 - input [31:0] addr, - input [31:0] wr_data, - input wr_en, - output wire [31:0] rd_data, - - input [31:0] signal_in, - - output ttloutput, //ttl输出信号 - output ttloutput_state_led //ttl输出状态信号 -); - - /******************************************************************************* - * 寄存器列表 * - *******************************************************************************/ - //!信号处理模式 0:固定输出低电平，1:固定输出高电平，2:分频倍频模式，3:转发模式，4:测试模式 - reg [31:0] reg_signal_process_mode; - //!TTLOUT_信号选择器 - reg [31:0] reg_input_signal_select; - //!TTLOUT_分频器 - reg [31:0] reg_pllout_freq_division_ctrl; - //!TTLOUT_频率倍增器 - reg [31:0] reg_pllout_freq_multiplication_ctrl; - //!TTLOUT_极性控制寄存器 - reg [31:0] reg_pllout_polarity_ctrl; - //!TTLOUT_触发信号边沿类型 - reg [31:0] reg_pllout_trigger_edge_select; - //!转发模式下的极性控制 - reg [31:0] reg_forward_mode_polarity_ctrl; - //!占位 - reg [31:0] reg_placeholder0; - // !频率探测偏差 - reg [31:0] reg_freq_detect_bias; - - //!输入信号频率探测 read only - wire [31:0] reg_sig_in_freq_detect; - //!输出信号频率探测 read only - wire [31:0] reg_sig_out_freq_detect; - - wire [31:0] reg_wr_index; //!寄存器写入时相对地址 - wire signal_in_choose; //!原始信号 - wire signal_in_af_pll; //!倍频后的信号 - wire signal_af_pll_af_polarity_ctrl; //!极性翻转后的信号 - wire signal_in_af_forward_mode_polarity_ctrl; //!转发模式下的输入信号 - wire signal_test; //!测试信号 - - - //信号流转图 - // - // signal_in[](原始信号) - // ---> reg_input_signal_select -->signal_in_choose(信号选择器) - // --> - // reg_pllout_trigger_edge_select - // reg_pllout_freq_division_ctrl ---> signal_in_af_pll(经分频倍频后的信号) - // reg_pllout_freq_multiplication_ctrl - // ---> signal_af_pll_af_polarity_ctrl - // - // - // 0:0 ---| - // 1:1 ---| - // 2:signal_af_pll_af_polarity_ctrl ---|--> - // 3:signal_in_af_forward_mode_polarity_ctrl ---| - // 4:test_sig ---| - // - - //!TTLOUT_寄存器自动赋值选择器 - zutils_register_advanced #( - .REG_START_ADD(REG_START_ADD) - ) _register ( - .clk (clk), - .rst_n (rst_n), - .addr (addr), - .wr_data (wr_data), - .wr_en (wr_en), - .rd_data (rd_data), - .reg1 (reg_signal_process_mode), - .reg2 (reg_input_signal_select), - .reg3 (reg_pllout_freq_division_ctrl), - .reg4 (reg_pllout_freq_multiplication_ctrl), - .reg5 (reg_pllout_polarity_ctrl), - .reg6 (reg_pllout_trigger_edge_select), - .reg7 (reg_forward_mode_polarity_ctrl), - .reg8 (reg_placeholder0), - .reg9 (reg_freq_detect_bias), - .regE (reg_sig_in_freq_detect), - .regF (reg_sig_out_freq_detect), - .reg_wr_sig(reg_wr_sig), - .reg_index (reg_wr_index) - ); - - //!寄存器写入逻辑 - always @(posedge clk or negedge rst_n) begin - if (!rst_n) begin - reg_signal_process_mode <= 0; - reg_input_signal_select <= 0; - reg_pllout_freq_division_ctrl <= 0; - reg_pllout_freq_multiplication_ctrl <= 0; - reg_pllout_polarity_ctrl <= 0; - reg_pllout_trigger_edge_select <= 1; - reg_forward_mode_polarity_ctrl <= 0; - reg_placeholder0 <= 0; - reg_freq_detect_bias <= `FREQ_DETECT_BIAS_DEFAULT; - end else begin - if (reg_wr_sig) begin - case (reg_wr_index) - 1: reg_signal_process_mode <= wr_data; - 2: reg_input_signal_select <= wr_data; - 3: reg_pllout_freq_division_ctrl <= wr_data; - 4: reg_pllout_freq_multiplication_ctrl <= wr_data; - 5: reg_pllout_polarity_ctrl <= wr_data; - 6: reg_pllout_trigger_edge_select <= wr_data; - 7: reg_forward_mode_polarity_ctrl <= wr_data; - 8: reg_placeholder0 <= wr_data; - 9: reg_freq_detect_bias <= wr_data; - default: begin - end - endcase - end - end - end - - //!信号选择器 - zutils_multiplexer_32t1 signal_in_multiplexer ( - .chooseindex(reg_input_signal_select), - .signal (signal_in), - .signalout (signal_in_choose) - ); - - //!pll信号处理 - zsimple_pll _simple_pll ( - .clk (clk), - .rst_n (rst_n), - .insignal (signal_in_choose), - .trigger_eage_type (reg_pllout_trigger_edge_select[0]), - .freq_detect_bias (reg_freq_detect_bias), - .freq_division (reg_pllout_freq_division_ctrl), - .freq_multiplication(reg_pllout_freq_multiplication_ctrl), - .polarity_ctrl (reg_pllout_polarity_ctrl[0]), - .cfg_change (reg_wr_sig), - .outsignal (signal_in_af_pll) - ); - - - //!100HZ测试信号发生器 - zutils_pwm_generator #( - .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ), - .OUTPUT_FREQ(100) - ) pwm100hz_gen ( - .clk (clk), - .rst_n (rst_n), - .output_signal(signal_test) - ); - - - - assign signal_in_af_forward_mode_polarity_ctrl = signal_in_choose ^ reg_forward_mode_polarity_ctrl[0]; - - //!信号输出选择器 - zutils_multiplexer_8t1 signal_output_multiplexer ( - .chooseindex(reg_signal_process_mode), - .signal0 (1'b0), - .signal1 (1'b1), - .signal2 (signal_in_af_pll), - .signal3 (signal_in_af_forward_mode_polarity_ctrl), - .signal4 (signal_test), - .signal5 (1'b0), - .signal6 (1'b0), - .signal7 (1'b0), - .signalout (ttloutput) - ); - - // - // - zutils_freq_detector_v2 in_freq_detector ( - .clk (clk), - .rst_n (rst_n), - .freq_detect_bias(reg_freq_detect_bias), - .pluse_input (signal_in_choose), - .pluse_width_cnt (reg_sig_in_freq_detect) - ); - - zutils_freq_detector_v2 output_freq_detector ( - .clk (clk), - .rst_n (rst_n), - .freq_detect_bias(reg_freq_detect_bias), - .pluse_input (ttloutput), - .pluse_width_cnt (reg_sig_out_freq_detect) - ); - assign ttloutput_state_led = 1; - - -endmodule