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syncbox16ch_fpga
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zhaohe 1 year ago
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10fbbad7a5
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636eefe6cd
3 changed files with 27 additions and 27 deletions
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  1. 50
      camera_light_src_timing_controller_fpga.pds
  2. 2
      source/src/config.v
  3. 2
      source/src/trigger_source/trigger_source_base_module.v

50
camera_light_src_timing_controller_fpga.pds
View File

@ -1,5 +1,5 @@
(_flow fab_demo "2021.1-SP7"
(_comment "Generated by Fabric Compiler (version on 2021.1-SP7<build 86875>) at Tue Apr 23 18:32:07 2024")
(_comment "Generated by Fabric Compiler (version on 2021.1-SP7<build 86875>) at Tue Apr 23 19:57:55 2024")
(_version "1.0.5")
(_status "initial")
(_project
@ -187,7 +187,7 @@
)
(_file "source/src/trigger_source/trigger_source_base_module.v"
(_format verilog)
(_timespec "2024-04-23T15:11:45")
(_timespec "2024-04-23T19:31:04")
)
(_file "source/src/output/light_src_ctrl.v"
(_format verilog)
@ -279,17 +279,17 @@
(_db_output
(_file "compile/Top_comp.adf"
(_format adif)
(_timespec "2024-04-23T18:27:30")
(_timespec "2024-04-23T19:51:24")
)
)
(_output
(_file "compile/Top.cmr"
(_format verilog)
(_timespec "2024-04-23T18:27:28")
(_timespec "2024-04-23T19:51:22")
)
(_file "compile/cmr.db"
(_format text)
(_timespec "2024-04-23T18:27:30")
(_timespec "2024-04-23T19:51:24")
)
)
)
@ -305,21 +305,21 @@
(_db_output
(_file "synthesize/Top_syn.adf"
(_format adif)
(_timespec "2024-04-23T18:28:56")
(_timespec "2024-04-23T19:52:50")
)
)
(_output
(_file "synthesize/Top_syn.vm"
(_format structural_verilog)
(_timespec "2024-04-23T18:29:04")
(_timespec "2024-04-23T19:52:57")
)
(_file "synthesize/Top.snr"
(_format text)
(_timespec "2024-04-23T18:29:11")
(_timespec "2024-04-23T19:53:04")
)
(_file "synthesize/snr.db"
(_format text)
(_timespec "2024-04-23T18:29:11")
(_timespec "2024-04-23T19:53:05")
)
)
)
@ -340,21 +340,21 @@
(_db_output
(_file "device_map/Top_map.adf"
(_format adif)
(_timespec "2024-04-23T18:29:21")
(_timespec "2024-04-23T19:53:15")
)
)
(_output
(_file "device_map/Top_dmr.prt"
(_format text)
(_timespec "2024-04-23T18:29:14")
(_timespec "2024-04-23T19:53:08")
)
(_file "device_map/Top.dmr"
(_format text)
(_timespec "2024-04-23T18:29:21")
(_timespec "2024-04-23T19:53:15")
)
(_file "device_map/dmr.db"
(_format text)
(_timespec "2024-04-23T18:29:22")
(_timespec "2024-04-23T19:53:16")
)
)
)
@ -363,7 +363,7 @@
(_input
(_file "device_map/camera_light_src_timing_controller_fpga.pcf"
(_format pcf)
(_timespec "2024-04-23T18:29:21")
(_timespec "2024-04-23T19:53:15")
)
)
)
@ -378,33 +378,33 @@
(_db_output
(_file "place_route/Top_pnr.adf"
(_format adif)
(_timespec "2024-04-23T18:31:18")
(_timespec "2024-04-23T19:56:41")
)
)
(_output
(_file "place_route/Top.prr"
(_format text)
(_timespec "2024-04-23T18:31:18")
(_timespec "2024-04-23T19:56:41")
)
(_file "place_route/Top_prr.prt"
(_format text)
(_timespec "2024-04-23T18:31:18")
(_timespec "2024-04-23T19:56:39")
)
(_file "place_route/clock_utilization.txt"
(_format text)
(_timespec "2024-04-23T18:31:18")
(_timespec "2024-04-23T19:56:40")
)
(_file "place_route/Top_plc.adf"
(_format adif)
(_timespec "2024-04-23T18:30:12")
(_timespec "2024-04-23T19:54:03")
)
(_file "place_route/Top_pnr.netlist"
(_format text)
(_timespec "2024-04-23T18:31:18")
(_timespec "2024-04-23T19:56:41")
)
(_file "place_route/prr.db"
(_format text)
(_timespec "2024-04-23T18:31:19")
(_timespec "2024-04-23T19:56:42")
)
)
)
@ -439,19 +439,19 @@
(_output
(_file "generate_bitstream/Top.sbit"
(_format text)
(_timespec "2024-04-23T18:32:05")
(_timespec "2024-04-23T19:57:53")
)
(_file "generate_bitstream/Top.smsk"
(_format text)
(_timespec "2024-04-23T18:32:05")
(_timespec "2024-04-23T19:57:53")
)
(_file "generate_bitstream/Top.bgr"
(_format text)
(_timespec "2024-04-23T18:32:05")
(_timespec "2024-04-23T19:57:53")
)
(_file "generate_bitstream/bgr.db"
(_format text)
(_timespec "2024-04-23T18:32:06")
(_timespec "2024-04-23T19:57:55")
)
)
)

2
source/src/config.v
View File

@ -1,4 +1,4 @@
`define REGADDOFF__FPGA_VERSION 32'd3
`define REGADDOFF__FPGA_VERSION 32'd4
/*******************************************************************************
* 寄存器地址分配 *
*******************************************************************************/

2
source/src/trigger_source/trigger_source_base_module.v
View File

@ -82,7 +82,7 @@ module trigger_source_base_module #(
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
reg1_src_slect <= 0;
reg2_fileter_coefficient <= 0;
reg2_fileter_coefficient <= `FREQ_TTL_INPUT_FILTER;
reg3_freq_detect_bias <= `FREQ_DETECT_BIAS_DEFAULT;
reg4_mode <= `SIG_PROCESS_MODE__TRIGGER_MODE;
reg5_trigger_mode_trigger_edge <= 0;

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