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syncbox16ch_fpga
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update

master
zhaohe 1 year ago
parent
9a5ead9812
commit
6e6d9efdb9
6 changed files with 51 additions and 47 deletions
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  1. 66
      camera_light_src_timing_controller_fpga.pds
  2. 3
      source/src/config.v
  3. 1
      source/src/output/light_src_ctrl.v
  4. 6
      source/src/output/ttl_output_ctrl.v
  5. 2
      source/src/top.v
  6. 20
      source/src/trigger_source/trigger_source_base_module.v

66
camera_light_src_timing_controller_fpga.pds
View File

@ -1,5 +1,5 @@
(_flow fab_demo "2021.1-SP7"
(_comment "Generated by Fabric Compiler (version on 2021.1-SP7<build 86875>) at Sun Mar 10 19:57:45 2024")
(_comment "Generated by Fabric Compiler (version on 2021.1-SP7<build 86875>) at Sun Mar 10 23:34:39 2024")
(_version "1.0.5")
(_status "initial")
(_project
@ -19,7 +19,7 @@
(_input
(_file "source/src/top.v" + "Top:"
(_format verilog)
(_timespec "2024-03-10T19:56:30")
(_timespec "2024-03-10T23:27:42")
)
(_file "source/src/spi_reg_reader.v"
(_format verilog)
@ -191,15 +191,15 @@
)
(_file "source/src/trigger_source/trigger_source_base_module.v"
(_format verilog)
(_timespec "2024-03-10T18:52:01")
(_timespec "2024-03-10T22:18:31")
)
(_file "source/src/output/light_src_ctrl.v"
(_format verilog)
(_timespec "2024-03-10T19:37:57")
(_timespec "2024-03-10T23:34:38")
)
(_file "source/src/output/ttl_output_ctrl.v"
(_format verilog)
(_timespec "2024-03-10T19:14:59")
(_timespec "2024-03-10T22:41:52")
)
(_file "source/src/zutils/zutils_pluse_generator_v2.v"
(_format verilog)
@ -275,21 +275,21 @@
)
(_task tsk_compile
(_command cmd_compile
(_gci_state (_integer 2))
(_gci_state (_integer 3))
(_db_output
(_file "compile/Top_comp.adf"
(_format adif)
(_timespec "2024-03-10T19:56:56")
(_timespec "2024-03-10T23:27:55")
)
)
(_output
(_file "compile/Top.cmr"
(_format verilog)
(_timespec "2024-03-10T19:56:55")
(_timespec "2024-03-10T23:27:53")
)
(_file "compile/cmr.db"
(_format text)
(_timespec "2024-03-10T19:56:57")
(_timespec "2024-03-10T23:27:55")
)
)
)
@ -299,27 +299,27 @@
)
(_task tsk_synthesis
(_command cmd_synthesize
(_gci_state (_integer 2))
(_gci_state (_integer 3))
(_option ads (_switch ON))
(_option selected_syn_tool_opt (_integer 2))
(_db_output
(_file "synthesize/Top_syn.adf"
(_format adif)
(_timespec "2024-03-10T19:57:12")
(_timespec "2024-03-10T23:28:09")
)
)
(_output
(_file "synthesize/Top_syn.vm"
(_format structural_verilog)
(_timespec "2024-03-10T19:57:12")
(_timespec "2024-03-10T23:28:10")
)
(_file "synthesize/Top.snr"
(_format text)
(_timespec "2024-03-10T19:57:13")
(_timespec "2024-03-10T23:28:10")
)
(_file "synthesize/snr.db"
(_format text)
(_timespec "2024-03-10T19:57:13")
(_timespec "2024-03-10T23:28:10")
)
)
)
@ -336,25 +336,25 @@
)
(_task tsk_devmap
(_command cmd_devmap
(_gci_state (_integer 2))
(_gci_state (_integer 3))
(_db_output
(_file "device_map/Top_map.adf"
(_format adif)
(_timespec "2024-03-10T19:57:16")
(_timespec "2024-03-10T23:28:14")
)
)
(_output
(_file "device_map/Top_dmr.prt"
(_format text)
(_timespec "2024-03-10T19:57:15")
(_timespec "2024-03-10T23:28:13")
)
(_file "device_map/Top.dmr"
(_format text)
(_timespec "2024-03-10T19:57:16")
(_timespec "2024-03-10T23:28:14")
)
(_file "device_map/dmr.db"
(_format text)
(_timespec "2024-03-10T19:57:16")
(_timespec "2024-03-10T23:28:14")
)
)
)
@ -363,7 +363,7 @@
(_input
(_file "device_map/camera_light_src_timing_controller_fpga.pcf"
(_format pcf)
(_timespec "2024-03-10T19:57:16")
(_timespec "2024-03-10T23:28:14")
)
)
)
@ -373,38 +373,38 @@
)
(_task tsk_pnr
(_command cmd_pnr
(_gci_state (_integer 2))
(_gci_state (_integer 3))
(_option mode (_string "fast"))
(_db_output
(_file "place_route/Top_pnr.adf"
(_format adif)
(_timespec "2024-03-10T19:57:33")
(_timespec "2024-03-10T23:28:45")
)
)
(_output
(_file "place_route/Top.prr"
(_format text)
(_timespec "2024-03-10T19:57:33")
(_timespec "2024-03-10T23:28:45")
)
(_file "place_route/Top_prr.prt"
(_format text)
(_timespec "2024-03-10T19:57:33")
(_timespec "2024-03-10T23:28:44")
)
(_file "place_route/clock_utilization.txt"
(_format text)
(_timespec "2024-03-10T19:57:33")
(_timespec "2024-03-10T23:28:44")
)
(_file "place_route/Top_plc.adf"
(_format adif)
(_timespec "2024-03-10T19:57:23")
(_timespec "2024-03-10T23:28:21")
)
(_file "place_route/Top_pnr.netlist"
(_format text)
(_timespec "2024-03-10T19:57:33")
(_timespec "2024-03-10T23:28:45")
)
(_file "place_route/prr.db"
(_format text)
(_timespec "2024-03-10T19:57:34")
(_timespec "2024-03-10T23:28:46")
)
)
)
@ -435,23 +435,23 @@
)
(_task tsk_gen_bitstream
(_command cmd_gen_bitstream
(_gci_state (_integer 2))
(_gci_state (_integer 3))
(_output
(_file "generate_bitstream/Top.sbit"
(_format text)
(_timespec "2024-03-10T19:57:45")
(_timespec "2024-03-10T23:29:07")
)
(_file "generate_bitstream/Top.smsk"
(_format text)
(_timespec "2024-03-10T19:57:45")
(_timespec "2024-03-10T23:29:07")
)
(_file "generate_bitstream/Top.bgr"
(_format text)
(_timespec "2024-03-10T19:57:45")
(_timespec "2024-03-10T23:29:07")
)
(_file "generate_bitstream/bgr.db"
(_format text)
(_timespec "2024-03-10T19:57:45")
(_timespec "2024-03-10T23:29:08")
)
)
)

3
source/src/config.v
View File

@ -65,3 +65,6 @@
`define SIG_EXT_TRIGGER_4_I4 32'd26
`define SIG_PROCESS_MODE__TRIGGER_MODE 32'd0
`define SIG_PROCESS_MODE__TRANSPARENT_MODE 32'd1
`define SIG_PROCESS_MODE__BIND_MODE 32'd2

1
source/src/output/light_src_ctrl.v
View File

@ -171,3 +171,4 @@ module light_src_ctrl #(
assign lt_en = signal_en_output;
endmodule

6
source/src/output/ttl_output_ctrl.v
View File

@ -54,7 +54,7 @@ module ttl_output_ctrl #(
//!寄存器写入逻辑
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
reg1_output_ctrl_mode <= 0;
reg1_output_ctrl_mode <= `SIG_PROCESS_MODE__BIND_MODE;
reg2_lt_en_bind <= 32'hffff_ffff;
reg3_lt_en_offset <= (SYS_CLOCK_FREQ / 32'd1000_000); //1us
@ -125,8 +125,8 @@ module ttl_output_ctrl #(
always @(*) begin
case (reg1_output_ctrl_mode)
0: output_sig <= output_sig_0 & trigger_sig;
1: output_sig <= signal_in_choose;
`SIG_PROCESS_MODE__BIND_MODE: output_sig <= output_sig_0 & trigger_sig;
`SIG_PROCESS_MODE__TRANSPARENT_MODE: output_sig <= signal_in_choose;
default: begin
output_sig <= 0;
end

2
source/src/top.v
View File

@ -209,7 +209,7 @@ module Top (
);
trigger_source_base_module #(
.REG_START_ADD (`REGADDOFF__INTERNAL_CLK),
.REG_START_ADD (`REGADDOFF__INTERNAL_TRIGGER),
.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ)
) internal_trigger_clk_trigger_source_base_module (
.clk (sys_clk),

20
source/src/trigger_source/trigger_source_base_module.v
View File

@ -49,8 +49,8 @@ module trigger_source_base_module #(
reg [31:0] regA_sequential_control_pluse_cnt_max; //!顺序控制脉冲最大计数
wire [31:0] regE_in_signal_freq; //!输入脉冲频率
wire [31:0] regF_out_signal_freq; //!输出脉冲频率
wire [31:0] regE_in_signal_freq; //!输入脉冲频率
wire [31:0] regF_out_signal_freq; //!输出脉冲频率
wire [31:0] reg_wr_index;
@ -84,7 +84,7 @@ module trigger_source_base_module #(
reg1_src_slect <= 0;
reg2_fileter_coefficient <= 0;
reg3_freq_detect_bias <= `FREQ_DETECT_BIAS_DEFAULT;
reg4_mode <= 0;
reg4_mode <= `SIG_PROCESS_MODE__TRIGGER_MODE;
reg5_trigger_mode_trigger_edge <= 0;
reg6_trigger_mode_freq_division <= 0;
reg7_trigger_mode_freq_multiplication <= 0;
@ -111,10 +111,10 @@ module trigger_source_base_module #(
assign in_sig[0] = in_sig_0;
assign in_sig[1] = in_sig_1;
reg sig_af_choose; //!选择后的触发信号
wire sig_af_choose_af_filter; //!滤波后的脉冲
wire sig_af_choose_af_filter_af_pll; //!PLL后的脉冲
reg signal_out_final; //!最终输出的信号
reg sig_af_choose; //!选择后的触发信号
wire sig_af_choose_af_filter; //!滤波后的脉冲
wire sig_af_choose_af_filter_af_pll; //!PLL后的脉冲
reg signal_out_final; //!最终输出的信号
always @(*) begin
if (reg1_src_slect <= 1) begin
@ -164,9 +164,9 @@ module trigger_source_base_module #(
always @(*) begin
case (reg4_mode)
0: signal_out_final <= sig_af_choose_af_filter_af_pll;
1: signal_out_final <= sig_af_choose_af_filter;
default: signal_out_final <= 0;
`SIG_PROCESS_MODE__TRIGGER_MODE: signal_out_final <= sig_af_choose_af_filter_af_pll;
`SIG_PROCESS_MODE__TRANSPARENT_MODE: signal_out_final <= sig_af_choose_af_filter;
default: signal_out_final <= 0;
endcase
end

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