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syncbox16ch_fpga
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update

master
zhaohe 1 year ago
parent
6ea2bb1056
commit
70263d558e
7 changed files with 26 additions and 70 deletions
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  1. 2
      camera_light_src_timing_controller_fpga.fdc
  2. 80
      camera_light_src_timing_controller_fpga.pds
  3. BIN
      fdc_generator.exe
  4. 2
      pango_tools/build.bat
  5. 8
      pango_tools/fdc_generator.cpp
  6. 2
      pin.csv
  7. 2
      source/src/top.v

2
camera_light_src_timing_controller_fpga.fdc
View File

@ -53,7 +53,7 @@ define_attribute {p:id[3]} {PAP_IO_LOC} {J17}
define_attribute {p:id[3]} {PAP_IO_VCCIO} {3.3}
define_attribute {p:id[3]} {PAP_IO_STANDARD} {LVTTL33}
define_attribute {p:id[4]} {PAP_IO_DIRECTION} {INPUT}
define_attribute {p:id[4]} {PAP_IO_LOC} {J15}
define_attribute {p:id[4]} {PAP_IO_LOC} {E15}
define_attribute {p:id[4]} {PAP_IO_VCCIO} {3.3}
define_attribute {p:id[4]} {PAP_IO_STANDARD} {LVTTL33}
define_attribute {p:stm32_output_bus[0]} {PAP_IO_DIRECTION} {OUTPUT}

80
camera_light_src_timing_controller_fpga.pds
View File

@ -1,5 +1,5 @@
(_flow fab_demo "2021.1-SP7"
(_comment "Generated by Fabric Compiler (version on 2021.1-SP7<build 86875>) at Fri Mar 8 22:23:29 2024")
(_comment "Generated by Fabric Compiler (version on 2021.1-SP7<build 86875>) at Fri Mar 8 22:52:30 2024")
(_version "1.0.5")
(_status "initial")
(_project
@ -19,7 +19,7 @@
(_input
(_file "source/src/top.v" + "Top:"
(_format verilog)
(_timespec "2024-03-08T22:23:28")
(_timespec "2024-03-08T22:52:12")
)
(_file "source/src/spi_reg_reader.v"
(_format verilog)
@ -232,7 +232,7 @@
(_input
(_file "camera_light_src_timing_controller_fpga.fdc"
(_format fdc)
(_timespec "2024-03-08T22:09:41")
(_timespec "2024-03-08T22:52:15")
)
)
)
@ -279,21 +279,21 @@
)
(_task tsk_compile
(_command cmd_compile
(_gci_state (_integer 3))
(_gci_state (_integer 2))
(_db_output
(_file "compile/Top_comp.adf"
(_format adif)
(_timespec "2024-03-08T22:07:17")
(_timespec "2024-03-08T22:52:25")
)
)
(_output
(_file "compile/Top.cmr"
(_format verilog)
(_timespec "2024-03-08T22:07:17")
(_timespec "2024-03-08T22:52:25")
)
(_file "compile/cmr.db"
(_format text)
(_timespec "2024-03-08T22:07:17")
(_timespec "2024-03-08T22:52:26")
)
)
)
@ -303,27 +303,27 @@
)
(_task tsk_synthesis
(_command cmd_synthesize
(_gci_state (_integer 3))
(_gci_state (_integer 2))
(_option ads (_switch ON))
(_option selected_syn_tool_opt (_integer 2))
(_db_output
(_file "synthesize/Top_syn.adf"
(_format adif)
(_timespec "2024-03-08T22:07:19")
(_timespec "2024-03-08T22:52:28")
)
)
(_output
(_file "synthesize/Top_syn.vm"
(_format structural_verilog)
(_timespec "2024-03-08T22:07:19")
(_timespec "2024-03-08T22:52:28")
)
(_file "synthesize/Top.snr"
(_format text)
(_timespec "2024-03-08T22:07:19")
(_timespec "2024-03-08T22:52:28")
)
(_file "synthesize/snr.db"
(_format text)
(_timespec "2024-03-08T22:07:19")
(_timespec "2024-03-08T22:52:28")
)
)
)
@ -340,27 +340,7 @@
)
(_task tsk_devmap
(_command cmd_devmap
(_gci_state (_integer 3))
(_db_output
(_file "device_map/Top_map.adf"
(_format adif)
(_timespec "2024-03-08T22:08:03")
)
)
(_output
(_file "device_map/Top_dmr.prt"
(_format text)
(_timespec "2024-03-08T22:08:03")
)
(_file "device_map/Top.dmr"
(_format text)
(_timespec "2024-03-08T22:08:03")
)
(_file "device_map/dmr.db"
(_format text)
(_timespec "2024-03-08T22:08:03")
)
)
(_gci_state (_integer 0))
)
(_widget wgt_edit_placement_cons
(_attribute _click_to_run (_switch ON))
@ -377,40 +357,8 @@
)
(_task tsk_pnr
(_command cmd_pnr
(_gci_state (_integer 3))
(_gci_state (_integer 0))
(_option mode (_string "fast"))
(_db_output
(_file "place_route/Top_pnr.adf"
(_format adif)
(_timespec "2024-03-08T22:08:07")
)
)
(_output
(_file "place_route/Top.prr"
(_format text)
(_timespec "2024-03-08T22:08:07")
)
(_file "place_route/Top_prr.prt"
(_format text)
(_timespec "2024-03-08T22:08:07")
)
(_file "place_route/clock_utilization.txt"
(_format text)
(_timespec "2024-03-08T22:08:07")
)
(_file "place_route/Top_plc.adf"
(_format adif)
(_timespec "2024-03-08T22:08:07")
)
(_file "place_route/Top_pnr.netlist"
(_format text)
(_timespec "2024-03-08T22:08:07")
)
(_file "place_route/prr.db"
(_format text)
(_timespec "2024-03-08T22:08:08")
)
)
)
(_widget wgt_power_calculator
(_attribute _click_to_run (_switch ON))

BIN
fdc_generator.exe
View File

2
pango_tools/build.bat
View File

@ -1 +1 @@
g++ -static -static-libgcc -static-libstdc++ -lwsock32 -lstdc++ zcsv.cpp logger.cpp fdc_generator.cpp -o fdc_generator.exe
g++ -static -static-libgcc -static-libstdc++ -lwsock32 -lstdc++ zcsv.cpp logger.cpp fdc_generator.cpp -o ../fdc_generator.exe

8
pango_tools/fdc_generator.cpp
View File

@ -1,6 +1,7 @@
#include <windows.h>
#include <iostream>
#include <set>
#include "logger.hpp"
#include "zcsv.hpp"
@ -50,10 +51,17 @@ int _main() {
ofstream file;
file.open(outputfilename, ios::out | ios::trunc);
set<string> pins;
for (uint32_t i = 1; i < maxRow - 1; i++) {
string pin = zcsv->getdata(i + 1, 1);
string name = zcsv->getdata(i + 1, 2);
string direction = zcsv->getdata(i + 1, 3);
if(pins.find(pin) != pins.end()){
ZLOGE(TAG, "parse pin.csv fail, pin repeat, line num:%d,%s", i + 1, pin.c_str());
return -1;
}
pins.insert(pin);
if (direction == "INPUT") {
file << "define_attribute {p:" << name << "} {PAP_IO_DIRECTION} {INPUT}" << endl;

2
pin.csv
View File

@ -11,7 +11,7 @@ M16,id[0],INPUT
L16,id[1],INPUT
J18,id[2],INPUT
J17,id[3],INPUT
J15,id[4],INPUT
E15,id[4],INPUT
M18,stm32_output_bus[0],OUTPUT
K18,stm32_output_bus[1],OUTPUT
K17,stm32_output_bus[2],OUTPUT

2
source/src/top.v
View File

@ -10,7 +10,7 @@ module Top (
input wire spi_rx_pin,
output wire spi_tx_pin,
input wire uart_tx,
output wire uart_tx,
input wire uart_rx,

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