diff --git a/README.md b/README.md index 96412cc..92ec7b5 100644 --- a/README.md +++ b/README.md @@ -1,6 +1,16 @@ -cfg_gen_sfc -device_name W25Q128Q -opcode 107 -sbit_start_address 0 -sbit generate_bitstream/Top.sbit +``` + sfc转换指令 + cfg_gen_sfc -device_name W25Q128Q -opcode 107 -sbit_start_address 0 -sbit generate_bitstream/Top.sbit + +``` ``` - TODO: - 1. 内部触发和外部触发都使用 trigger_source_base_module模组，trigger_source_base_module初始化时，其默认过滤参数大于0，会过滤掉内部触发模块产生的信号。 + V6: + 1.光耦输入默认反向 + 2.修改内部触发默认滤波参数为0 + 3.光耦输入和TTL输入默认可调 + V5: + 1.解决上电灯闪烁的问题 + 2.修改默认滤波参数为10 + 3.优化分频倍频逻辑，支持不稳定频率输入 ``` \ No newline at end of file diff --git a/camera_light_src_timing_controller_fpga.pds b/camera_light_src_timing_controller_fpga.pds index 7a91fe7..86405d4 100644 --- a/camera_light_src_timing_controller_fpga.pds +++ b/camera_light_src_timing_controller_fpga.pds @@ -1,5 +1,5 @@ (_flow fab_demo "2021.1-SP7" - (_comment "Generated by Fabric Compiler (version on 2021.1-SP7) at Thu Apr 25 16:42:04 2024") + (_comment "Generated by Fabric Compiler (version on 2021.1-SP7) at Mon May 6 11:31:28 2024") (_version "1.0.5") (_status "initial") (_project @@ -19,7 +19,7 @@ (_input (_file "source/src/top.v" + "Top:" (_format verilog) - (_timespec "2024-04-25T16:35:18") + (_timespec "2024-05-06T11:27:37") ) (_file "source/src/spi_reg_reader.v" (_format verilog) @@ -187,7 +187,7 @@ ) (_file "source/src/trigger_source/trigger_source_base_module.v" (_format verilog) - (_timespec "2024-04-23T19:31:04") + (_timespec "2024-05-06T11:27:26") ) (_file "source/src/output/light_src_ctrl.v" (_format verilog) @@ -279,17 +279,17 @@ (_db_output (_file "compile/Top_comp.adf" (_format adif) - (_timespec "2024-04-25T16:38:12") + (_timespec "2024-05-06T11:30:03") ) ) (_output (_file "compile/Top.cmr" (_format verilog) - (_timespec "2024-04-25T16:38:10") + (_timespec "2024-05-06T11:30:01") ) (_file "compile/cmr.db" (_format text) - (_timespec "2024-04-25T16:38:12") + (_timespec "2024-05-06T11:30:03") ) ) ) @@ -305,21 +305,21 @@ (_db_output (_file "synthesize/Top_syn.adf" (_format adif) - (_timespec "2024-04-25T16:38:30") + (_timespec "2024-05-06T11:30:21") ) ) (_output (_file "synthesize/Top_syn.vm" (_format structural_verilog) - (_timespec "2024-04-25T16:38:31") + (_timespec "2024-05-06T11:30:22") ) (_file "synthesize/Top.snr" (_format text) - (_timespec "2024-04-25T16:38:32") + (_timespec "2024-05-06T11:30:23") ) (_file "synthesize/snr.db" (_format text) - (_timespec "2024-04-25T16:38:32") + (_timespec "2024-05-06T11:30:23") ) ) ) @@ -340,21 +340,21 @@ (_db_output (_file "device_map/Top_map.adf" (_format adif) - (_timespec "2024-04-25T16:38:36") + (_timespec "2024-05-06T11:30:29") ) ) (_output (_file "device_map/Top_dmr.prt" (_format text) - (_timespec "2024-04-25T16:38:35") + (_timespec "2024-05-06T11:30:27") ) (_file "device_map/Top.dmr" (_format text) - (_timespec "2024-04-25T16:38:36") + (_timespec "2024-05-06T11:30:29") ) (_file "device_map/dmr.db" (_format text) - (_timespec "2024-04-25T16:38:37") + (_timespec "2024-05-06T11:30:29") ) ) ) @@ -363,7 +363,7 @@ (_input (_file "device_map/camera_light_src_timing_controller_fpga.pcf" (_format pcf) - (_timespec "2024-04-25T16:38:36") + (_timespec "2024-05-06T11:30:29") ) ) ) @@ -378,33 +378,33 @@ (_db_output (_file "place_route/Top_pnr.adf" (_format adif) - (_timespec "2024-04-25T16:41:20") + (_timespec "2024-05-06T11:31:11") ) ) (_output (_file "place_route/Top.prr" (_format text) - (_timespec "2024-04-25T16:41:20") + (_timespec "2024-05-06T11:31:11") ) (_file "place_route/Top_prr.prt" (_format text) - (_timespec "2024-04-25T16:41:18") + (_timespec "2024-05-06T11:31:11") ) (_file "place_route/clock_utilization.txt" (_format text) - (_timespec "2024-04-25T16:41:18") + (_timespec "2024-05-06T11:31:11") ) (_file "place_route/Top_plc.adf" (_format adif) - (_timespec "2024-04-25T16:39:01") + (_timespec "2024-05-06T11:30:40") ) (_file "place_route/Top_pnr.netlist" (_format text) - (_timespec "2024-04-25T16:41:20") + (_timespec "2024-05-06T11:31:11") ) (_file "place_route/prr.db" (_format text) - (_timespec "2024-04-25T16:41:21") + (_timespec "2024-05-06T11:31:12") ) ) ) @@ -439,19 +439,19 @@ (_output (_file "generate_bitstream/Top.sbit" (_format text) - (_timespec "2024-04-25T16:42:03") + (_timespec "2024-05-06T11:31:28") ) (_file "generate_bitstream/Top.smsk" (_format text) - (_timespec "2024-04-25T16:42:03") + (_timespec "2024-05-06T11:31:28") ) (_file "generate_bitstream/Top.bgr" (_format text) - (_timespec "2024-04-25T16:42:03") + (_timespec "2024-05-06T11:31:28") ) (_file "generate_bitstream/bgr.db" (_format text) - (_timespec "2024-04-25T16:42:04") + (_timespec "2024-05-06T11:31:28") ) ) ) diff --git a/release/V6/clst_v6.sbit b/release/V6/clst_v6.sbit new file mode 100644 index 0000000..7130e79 Binary files /dev/null and b/release/V6/clst_v6.sbit differ diff --git a/release/V6/clst_v6.sfc b/release/V6/clst_v6.sfc new file mode 100644 index 0000000..d4120c0 Binary files /dev/null and b/release/V6/clst_v6.sfc differ diff --git a/source/src/config.v b/source/src/config.v index 0c859bf..e228b34 100644 --- a/source/src/config.v +++ b/source/src/config.v @@ -1,4 +1,4 @@ -`define REGADDOFF__FPGA_VERSION 32'd5 +`define REGADDOFF__FPGA_VERSION 32'd6 /******************************************************************************* * 寄存器地址分配 * *******************************************************************************/ diff --git a/source/src/top.v b/source/src/top.v index 106560f..a7343e6 100644 --- a/source/src/top.v +++ b/source/src/top.v @@ -100,8 +100,8 @@ module Top ( .clkout3 (sys_clk_100m) ); localparam SYS_CLOCK_FREQ = 100000000; - assign sys_clk = sys_clk_100m; - assign sys_rst_n = stm32_input_bus[0] & pll_lock; + assign sys_clk = sys_clk_100m; + assign sys_rst_n = stm32_input_bus[0] & pll_lock; assign tmp_contrl_pin[0] = !sys_rst_n; assign tmp_contrl_pin[1] = !sys_rst_n; @@ -215,7 +215,8 @@ module Top ( trigger_source_base_module #( .REG_START_ADD (`REGADDOFF__INTERNAL_TRIGGER), - .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ) + .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ), + .FREQ_DETECT_BIAS(0) ) internal_trigger_clk_trigger_source_base_module ( .clk (sys_clk), .rst_n(sys_rst_n), @@ -250,7 +251,7 @@ module Top ( .wr_en (RegReaderBus_wr_en), .rd_data(rd_data_trigger_in1), - .in_sig_0(optocoupler_in1), + .in_sig_0(!optocoupler_in1), .in_sig_1(diff_in1), .out_trigger_sig (sig_bus[`SIG_EXT_TRIGGER_1]), @@ -274,7 +275,7 @@ module Top ( .wr_en (RegReaderBus_wr_en), .rd_data(rd_data_trigger_in2), - .in_sig_0(optocoupler_in2), + .in_sig_0(!optocoupler_in2), .in_sig_1(diff_in2), .out_trigger_sig (sig_bus[`SIG_EXT_TRIGGER_2]), @@ -296,7 +297,7 @@ module Top ( .wr_en (RegReaderBus_wr_en), .rd_data(rd_data_trigger_in3), - .in_sig_0(optocoupler_in3), + .in_sig_0(!optocoupler_in3), .in_sig_1(diff_in3), .out_trigger_sig (sig_bus[`SIG_EXT_TRIGGER_3]), @@ -318,7 +319,7 @@ module Top ( .wr_en (RegReaderBus_wr_en), .rd_data(rd_data_trigger_in4), - .in_sig_0(optocoupler_in4), + .in_sig_0(!optocoupler_in4), .in_sig_1(diff_in4), .out_trigger_sig (sig_bus[`SIG_EXT_TRIGGER_4]), diff --git a/source/src/trigger_source/trigger_source_base_module.v b/source/src/trigger_source/trigger_source_base_module.v index ee1662c..248d9c9 100644 --- a/source/src/trigger_source/trigger_source_base_module.v +++ b/source/src/trigger_source/trigger_source_base_module.v @@ -1,7 +1,8 @@ `include "../config.v" module trigger_source_base_module #( parameter REG_START_ADD = 0, - parameter SYS_CLOCK_FREQ = 100000000 + parameter SYS_CLOCK_FREQ = 100000000, + parameter FREQ_DETECT_BIAS = `FREQ_DETECT_BIAS_DEFAULT ) ( input clk, //! 时钟输入 @@ -107,9 +108,11 @@ module trigger_source_base_module #( end end - wire [1:0] in_sig; + wire [3:0] in_sig; assign in_sig[0] = in_sig_0; assign in_sig[1] = in_sig_1; + assign in_sig[2] = !in_sig_0; + assign in_sig[3] = !in_sig_1; reg sig_af_choose; //!选择后的触发信号 wire sig_af_choose_af_filter; //!滤波后的脉冲 @@ -117,7 +120,7 @@ module trigger_source_base_module #( reg signal_out_final; //!最终输出的信号 always @(*) begin - if (reg1_src_slect <= 1) begin + if (reg1_src_slect <= 3) begin sig_af_choose = in_sig[reg1_src_slect]; end else begin sig_af_choose = 0;