diff --git a/.gitignore b/.gitignore index cdc6358..e32e8a2 100644 --- a/.gitignore +++ b/.gitignore @@ -17,3 +17,4 @@ report_timing/ ipcore/ram/ram.idf impl.tcl generate.log +out/* \ No newline at end of file diff --git a/README.md b/README.md index 21024f7..8162ccc 100644 --- a/README.md +++ b/README.md @@ -5,21 +5,5 @@ ``` ``` - V10: - 1.修复当寄存器变化频率的时候,SPI读取数据错误的BUG - V9: - 1.修复PL无法2+倍频的BUG - V7: - 1.修复PLL的BUG - V6: - 1.光耦输入默认反向 - 2.修改内部触发默认滤波参数为0 - 3.光耦输入和TTL输入默认可调 - V5: - 1.解决上电灯闪烁的问题 - 2.修改默认滤波参数为10 - 3.优化分频倍频逻辑,支持不稳定频率输入 - -TODO: - 寄存器变化频率的时候,SPI读取数据错误的BUG(PS:没有完全解决,暂时不知道问题在哪) + ``` \ No newline at end of file diff --git a/camera_light_src_timing_controller_fpga.fdc b/app.fdc similarity index 56% rename from camera_light_src_timing_controller_fpga.fdc rename to app.fdc index 0d3fc3c..91e6481 100644 --- a/camera_light_src_timing_controller_fpga.fdc +++ b/app.fdc @@ -36,36 +36,6 @@ define_attribute {p:core_board_debug_led} {PAP_IO_VCCIO} {3.3} define_attribute {p:core_board_debug_led} {PAP_IO_STANDARD} {LVCMOS33} define_attribute {p:core_board_debug_led} {PAP_IO_DRIVE} {4} define_attribute {p:core_board_debug_led} {PAP_IO_SLEW} {SLOW} -define_attribute {p:tmp_contrl_pin[0]} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:tmp_contrl_pin[0]} {PAP_IO_LOC} {M16} -define_attribute {p:tmp_contrl_pin[0]} {PAP_IO_VCCIO} {3.3} -define_attribute {p:tmp_contrl_pin[0]} {PAP_IO_STANDARD} {LVCMOS33} -define_attribute {p:tmp_contrl_pin[0]} {PAP_IO_DRIVE} {4} -define_attribute {p:tmp_contrl_pin[0]} {PAP_IO_SLEW} {SLOW} -define_attribute {p:tmp_contrl_pin[1]} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:tmp_contrl_pin[1]} {PAP_IO_LOC} {L16} -define_attribute {p:tmp_contrl_pin[1]} {PAP_IO_VCCIO} {3.3} -define_attribute {p:tmp_contrl_pin[1]} {PAP_IO_STANDARD} {LVCMOS33} -define_attribute {p:tmp_contrl_pin[1]} {PAP_IO_DRIVE} {4} -define_attribute {p:tmp_contrl_pin[1]} {PAP_IO_SLEW} {SLOW} -define_attribute {p:tmp_contrl_pin[2]} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:tmp_contrl_pin[2]} {PAP_IO_LOC} {J18} -define_attribute {p:tmp_contrl_pin[2]} {PAP_IO_VCCIO} {3.3} -define_attribute {p:tmp_contrl_pin[2]} {PAP_IO_STANDARD} {LVCMOS33} -define_attribute {p:tmp_contrl_pin[2]} {PAP_IO_DRIVE} {4} -define_attribute {p:tmp_contrl_pin[2]} {PAP_IO_SLEW} {SLOW} -define_attribute {p:tmp_contrl_pin[3]} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:tmp_contrl_pin[3]} {PAP_IO_LOC} {J17} -define_attribute {p:tmp_contrl_pin[3]} {PAP_IO_VCCIO} {3.3} -define_attribute {p:tmp_contrl_pin[3]} {PAP_IO_STANDARD} {LVCMOS33} -define_attribute {p:tmp_contrl_pin[3]} {PAP_IO_DRIVE} {4} -define_attribute {p:tmp_contrl_pin[3]} {PAP_IO_SLEW} {SLOW} -define_attribute {p:tmp_contrl_pin[4]} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:tmp_contrl_pin[4]} {PAP_IO_LOC} {E15} -define_attribute {p:tmp_contrl_pin[4]} {PAP_IO_VCCIO} {3.3} -define_attribute {p:tmp_contrl_pin[4]} {PAP_IO_STANDARD} {LVCMOS33} -define_attribute {p:tmp_contrl_pin[4]} {PAP_IO_DRIVE} {4} -define_attribute {p:tmp_contrl_pin[4]} {PAP_IO_SLEW} {SLOW} define_attribute {p:stm32_output_bus[0]} {PAP_IO_DIRECTION} {OUTPUT} define_attribute {p:stm32_output_bus[0]} {PAP_IO_LOC} {M18} define_attribute {p:stm32_output_bus[0]} {PAP_IO_VCCIO} {3.3} @@ -242,143 +212,25 @@ define_attribute {p:debug_bus[15]} {PAP_IO_VCCIO} {3.3} define_attribute {p:debug_bus[15]} {PAP_IO_STANDARD} {LVCMOS33} define_attribute {p:debug_bus[15]} {PAP_IO_DRIVE} {4} define_attribute {p:debug_bus[15]} {PAP_IO_SLEW} {SLOW} -define_attribute {p:optocoupler_out1} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:optocoupler_out1} {PAP_IO_LOC} {N18} -define_attribute {p:optocoupler_out1} {PAP_IO_VCCIO} {3.3} -define_attribute {p:optocoupler_out1} {PAP_IO_STANDARD} {LVCMOS33} -define_attribute {p:optocoupler_out1} {PAP_IO_DRIVE} {4} -define_attribute {p:optocoupler_out1} {PAP_IO_SLEW} {SLOW} -define_attribute {p:optocoupler_out2} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:optocoupler_out2} {PAP_IO_LOC} {L15} -define_attribute {p:optocoupler_out2} {PAP_IO_VCCIO} {3.3} -define_attribute {p:optocoupler_out2} {PAP_IO_STANDARD} {LVCMOS33} -define_attribute {p:optocoupler_out2} {PAP_IO_DRIVE} {4} -define_attribute {p:optocoupler_out2} {PAP_IO_SLEW} {SLOW} -define_attribute {p:optocoupler_out3} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:optocoupler_out3} {PAP_IO_LOC} {L14} -define_attribute {p:optocoupler_out3} {PAP_IO_VCCIO} {3.3} -define_attribute {p:optocoupler_out3} {PAP_IO_STANDARD} {LVCMOS33} -define_attribute {p:optocoupler_out3} {PAP_IO_DRIVE} {4} -define_attribute {p:optocoupler_out3} {PAP_IO_SLEW} {SLOW} -define_attribute {p:optocoupler_out4} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:optocoupler_out4} {PAP_IO_LOC} {M14} -define_attribute {p:optocoupler_out4} {PAP_IO_VCCIO} {3.3} -define_attribute {p:optocoupler_out4} {PAP_IO_STANDARD} {LVCMOS33} -define_attribute {p:optocoupler_out4} {PAP_IO_DRIVE} {4} -define_attribute {p:optocoupler_out4} {PAP_IO_SLEW} {SLOW} -define_attribute {p:optocoupler_in1} {PAP_IO_DIRECTION} {INPUT} -define_attribute {p:optocoupler_in1} {PAP_IO_LOC} {C15} -define_attribute {p:optocoupler_in1} {PAP_IO_VCCIO} {3.3} -define_attribute {p:optocoupler_in1} {PAP_IO_STANDARD} {LVTTL33} -define_attribute {p:optocoupler_in2} {PAP_IO_DIRECTION} {INPUT} -define_attribute {p:optocoupler_in2} {PAP_IO_LOC} {D15} -define_attribute {p:optocoupler_in2} {PAP_IO_VCCIO} {3.3} -define_attribute {p:optocoupler_in2} {PAP_IO_STANDARD} {LVTTL33} -define_attribute {p:optocoupler_in3} {PAP_IO_DIRECTION} {INPUT} -define_attribute {p:optocoupler_in3} {PAP_IO_LOC} {D13} -define_attribute {p:optocoupler_in3} {PAP_IO_VCCIO} {3.3} -define_attribute {p:optocoupler_in3} {PAP_IO_STANDARD} {LVTTL33} -define_attribute {p:optocoupler_in4} {PAP_IO_DIRECTION} {INPUT} -define_attribute {p:optocoupler_in4} {PAP_IO_LOC} {C13} -define_attribute {p:optocoupler_in4} {PAP_IO_VCCIO} {3.3} -define_attribute {p:optocoupler_in4} {PAP_IO_STANDARD} {LVTTL33} -define_attribute {p:diff_out1} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:diff_out1} {PAP_IO_LOC} {M13} -define_attribute {p:diff_out1} {PAP_IO_VCCIO} {3.3} -define_attribute {p:diff_out1} {PAP_IO_STANDARD} {LVCMOS33} -define_attribute {p:diff_out1} {PAP_IO_DRIVE} {4} -define_attribute {p:diff_out1} {PAP_IO_SLEW} {SLOW} -define_attribute {p:diff_out2} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:diff_out2} {PAP_IO_LOC} {U18} -define_attribute {p:diff_out2} {PAP_IO_VCCIO} {3.3} -define_attribute {p:diff_out2} {PAP_IO_STANDARD} {LVCMOS33} -define_attribute {p:diff_out2} {PAP_IO_DRIVE} {4} -define_attribute {p:diff_out2} {PAP_IO_SLEW} {SLOW} -define_attribute {p:diff_out3} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:diff_out3} {PAP_IO_LOC} {U17} -define_attribute {p:diff_out3} {PAP_IO_VCCIO} {3.3} -define_attribute {p:diff_out3} {PAP_IO_STANDARD} {LVCMOS33} -define_attribute {p:diff_out3} {PAP_IO_DRIVE} {4} -define_attribute {p:diff_out3} {PAP_IO_SLEW} {SLOW} -define_attribute {p:diff_out4} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:diff_out4} {PAP_IO_LOC} {T18} -define_attribute {p:diff_out4} {PAP_IO_VCCIO} {3.3} -define_attribute {p:diff_out4} {PAP_IO_STANDARD} {LVCMOS33} -define_attribute {p:diff_out4} {PAP_IO_DRIVE} {4} -define_attribute {p:diff_out4} {PAP_IO_SLEW} {SLOW} -define_attribute {p:diff_in1} {PAP_IO_DIRECTION} {INPUT} -define_attribute {p:diff_in1} {PAP_IO_LOC} {B18} -define_attribute {p:diff_in1} {PAP_IO_VCCIO} {3.3} -define_attribute {p:diff_in1} {PAP_IO_STANDARD} {LVTTL33} -define_attribute {p:diff_in2} {PAP_IO_DIRECTION} {INPUT} -define_attribute {p:diff_in2} {PAP_IO_LOC} {B17} -define_attribute {p:diff_in2} {PAP_IO_VCCIO} {3.3} -define_attribute {p:diff_in2} {PAP_IO_STANDARD} {LVTTL33} -define_attribute {p:diff_in3} {PAP_IO_DIRECTION} {INPUT} -define_attribute {p:diff_in3} {PAP_IO_LOC} {A17} -define_attribute {p:diff_in3} {PAP_IO_VCCIO} {3.3} -define_attribute {p:diff_in3} {PAP_IO_STANDARD} {LVTTL33} -define_attribute {p:diff_in4} {PAP_IO_DIRECTION} {INPUT} -define_attribute {p:diff_in4} {PAP_IO_LOC} {E16} -define_attribute {p:diff_in4} {PAP_IO_VCCIO} {3.3} -define_attribute {p:diff_in4} {PAP_IO_STANDARD} {LVTTL33} -define_attribute {p:lt1_intensity_ctrl} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:lt1_intensity_ctrl} {PAP_IO_LOC} {T17} -define_attribute {p:lt1_intensity_ctrl} {PAP_IO_VCCIO} {3.3} -define_attribute {p:lt1_intensity_ctrl} {PAP_IO_STANDARD} {LVCMOS33} -define_attribute {p:lt1_intensity_ctrl} {PAP_IO_DRIVE} {4} -define_attribute {p:lt1_intensity_ctrl} {PAP_IO_SLEW} {SLOW} -define_attribute {p:lt1_en} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:lt1_en} {PAP_IO_LOC} {V16} -define_attribute {p:lt1_en} {PAP_IO_VCCIO} {3.3} -define_attribute {p:lt1_en} {PAP_IO_STANDARD} {LVCMOS33} -define_attribute {p:lt1_en} {PAP_IO_DRIVE} {4} -define_attribute {p:lt1_en} {PAP_IO_SLEW} {SLOW} -define_attribute {p:lt1_error_sig_in} {PAP_IO_DIRECTION} {INPUT} -define_attribute {p:lt1_error_sig_in} {PAP_IO_LOC} {A14} -define_attribute {p:lt1_error_sig_in} {PAP_IO_VCCIO} {3.3} -define_attribute {p:lt1_error_sig_in} {PAP_IO_STANDARD} {LVTTL33} -define_attribute {p:lt2_intensity_ctrl} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:lt2_intensity_ctrl} {PAP_IO_LOC} {V18} -define_attribute {p:lt2_intensity_ctrl} {PAP_IO_VCCIO} {3.3} -define_attribute {p:lt2_intensity_ctrl} {PAP_IO_STANDARD} {LVCMOS33} -define_attribute {p:lt2_intensity_ctrl} {PAP_IO_DRIVE} {4} -define_attribute {p:lt2_intensity_ctrl} {PAP_IO_SLEW} {SLOW} -define_attribute {p:lt2_en} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:lt2_en} {PAP_IO_LOC} {T16} -define_attribute {p:lt2_en} {PAP_IO_VCCIO} {3.3} -define_attribute {p:lt2_en} {PAP_IO_STANDARD} {LVCMOS33} -define_attribute {p:lt2_en} {PAP_IO_DRIVE} {4} -define_attribute {p:lt2_en} {PAP_IO_SLEW} {SLOW} -define_attribute {p:lt2_error_sig_in} {PAP_IO_DIRECTION} {INPUT} -define_attribute {p:lt2_error_sig_in} {PAP_IO_LOC} {B14} -define_attribute {p:lt2_error_sig_in} {PAP_IO_VCCIO} {3.3} -define_attribute {p:lt2_error_sig_in} {PAP_IO_STANDARD} {LVTTL33} -define_attribute {p:lt3_intensity_ctrl} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:lt3_intensity_ctrl} {PAP_IO_LOC} {V17} -define_attribute {p:lt3_intensity_ctrl} {PAP_IO_VCCIO} {3.3} -define_attribute {p:lt3_intensity_ctrl} {PAP_IO_STANDARD} {LVCMOS33} -define_attribute {p:lt3_intensity_ctrl} {PAP_IO_DRIVE} {4} -define_attribute {p:lt3_intensity_ctrl} {PAP_IO_SLEW} {SLOW} -define_attribute {p:lt3_en} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:lt3_en} {PAP_IO_LOC} {R16} -define_attribute {p:lt3_en} {PAP_IO_VCCIO} {3.3} -define_attribute {p:lt3_en} {PAP_IO_STANDARD} {LVCMOS33} -define_attribute {p:lt3_en} {PAP_IO_DRIVE} {4} -define_attribute {p:lt3_en} {PAP_IO_SLEW} {SLOW} -define_attribute {p:lt3_error_sig_in} {PAP_IO_DIRECTION} {INPUT} -define_attribute {p:lt3_error_sig_in} {PAP_IO_LOC} {A12} -define_attribute {p:lt3_error_sig_in} {PAP_IO_VCCIO} {3.3} -define_attribute {p:lt3_error_sig_in} {PAP_IO_STANDARD} {LVTTL33} -define_attribute {p:lt4_intensity_ctrl} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:lt4_intensity_ctrl} {PAP_IO_LOC} {U16} -define_attribute {p:lt4_intensity_ctrl} {PAP_IO_VCCIO} {3.3} -define_attribute {p:lt4_intensity_ctrl} {PAP_IO_STANDARD} {LVCMOS33} -define_attribute {p:lt4_intensity_ctrl} {PAP_IO_DRIVE} {4} -define_attribute {p:lt4_intensity_ctrl} {PAP_IO_SLEW} {SLOW} -define_attribute {p:lt4_en} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:lt4_en} {PAP_IO_LOC} {R15} -define_attribute {p:lt4_en} {PAP_IO_VCCIO} {3.3} -define_attribute {p:lt4_en} {PAP_IO_STANDARD} {LVCMOS33} -define_attribute {p:lt4_en} {PAP_IO_DRIVE} {4} -define_attribute {p:lt4_en} {PAP_IO_SLEW} {SLOW} +define_attribute {p:out1} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:out1} {PAP_IO_LOC} {N18} +define_attribute {p:out1} {PAP_IO_VCCIO} {3.3} +define_attribute {p:out1} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:out1} {PAP_IO_DRIVE} {4} +define_attribute {p:out1} {PAP_IO_SLEW} {SLOW} +define_attribute {p:extOutputEn1} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:extOutputEn1} {PAP_IO_LOC} {L15} +define_attribute {p:extOutputEn1} {PAP_IO_VCCIO} {3.3} +define_attribute {p:extOutputEn1} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:extOutputEn1} {PAP_IO_DRIVE} {4} +define_attribute {p:extOutputEn1} {PAP_IO_SLEW} {SLOW} +define_attribute {p:extOutputEn2} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:extOutputEn2} {PAP_IO_LOC} {L14} +define_attribute {p:extOutputEn2} {PAP_IO_VCCIO} {3.3} +define_attribute {p:extOutputEn2} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:extOutputEn2} {PAP_IO_DRIVE} {4} +define_attribute {p:extOutputEn2} {PAP_IO_SLEW} {SLOW} +define_attribute {p:triSig} {PAP_IO_DIRECTION} {INPUT} +define_attribute {p:triSig} {PAP_IO_LOC} {M16} +define_attribute {p:triSig} {PAP_IO_VCCIO} {3.3} +define_attribute {p:triSig} {PAP_IO_STANDARD} {LVTTL33} diff --git a/out/linecounter.json b/out/linecounter.json deleted file mode 100644 index 665af5a..0000000 --- a/out/linecounter.json +++ /dev/null @@ -1,2753 +0,0 @@ -{ - "extension": "linecounter", - "version": "0.2.7", - "workspace": "d:\\workspace\\fpga_demo\\camera_light_src_timing_controller_fpga", - "linecount": [ - { - "version": "0.2.7", - "counttime": "2024-01-11 20:40:13", - "filesum": 413, - "codesum": 552462, - "commentsum": 14393, - "blanksum": 31258, - "statistics": { - ".md": { - "code": 45, - "comment": 3, - "blank": 27 - }, - ".fdc": { - "code": 3427, - "comment": 0, - "blank": 40 - }, - ".txt": { - "code": 50, - "comment": 0, - "blank": 6 - }, - ".snr": { - "code": 2119, - "comment": 0, - "blank": 256 - }, - ".ccr": { - "code": 227, - "comment": 0, - "blank": 172 - }, - ".log": { - "code": 233241, - "comment": 4574, - "blank": 16262 - }, - ".prt": { - "code": 960, - "comment": 0, - "blank": 0 - }, - ".tcl": { - "code": 1915, - "comment": 65, - "blank": 8 - }, - ".prr": { - "code": 363, - "comment": 0, - "blank": 27 - }, - ".db": { - "code": 46034, - "comment": 0, - "blank": 0 - }, - ".bat": { - "code": 11, - "comment": 0, - "blank": 0 - }, - ".ini": { - "code": 126, - "comment": 3324, - "blank": 706 - }, - "": { - "code": 106783, - "comment": 28, - "blank": 0 - }, - ".rtr": { - "code": 2754, - "comment": 0, - "blank": 404 - }, - ".qpg": { - "code": 0, - "comment": 0, - "blank": 0 - }, - ".netlist": { - "code": 94241, - "comment": 0, - "blank": 7587 - }, - ".v": { - "code": 3118, - "comment": 1206, - "blank": 641 - }, - ".pvf": { - "code": 1314, - "comment": 0, - "blank": 437 - }, - ".vm": { - "code": 51623, - "comment": 5188, - "blank": 4614 - }, - ".bak": { - "code": 85, - "comment": 5, - "blank": 7 - }, - ".pds": { - "code": 295, - "comment": 0, - "blank": 0 - }, - ".bgr": { - "code": 38, - "comment": 0, - "blank": 8 - }, - ".pcf": { - "code": 69, - "comment": 0, - "blank": 1 - }, - ".cmr": { - "code": 5, - "comment": 0, - "blank": 5 - }, - ".vhdl": { - "code": 42, - "comment": 0, - "blank": 8 - }, - ".idf": { - "code": 2826, - "comment": 0, - "blank": 0 - }, - ".pdf": { - "code": 188, - "comment": 0, - "blank": 0 - }, - ".dmr": { - "code": 563, - "comment": 0, - "blank": 42 - } - }, - "filelist": [ - { - "blank": 0, - "code": 18, - "comment": 0, - "filename": ".gitignore" - }, - { - "blank": 0, - "code": 188, - "comment": 0, - "filename": "ACPGL22G核心板原理图.pdf" - }, - { - "blank": 1, - "code": 1, - "comment": 0, - "filename": "compile\\bak\\async_receiver.cmr" - }, - { - "blank": 0, - "code": 1388, - "comment": 0, - "filename": "compile\\bak\\cmr.db" - }, - { - "blank": 1, - "code": 1, - "comment": 0, - "filename": "compile\\bak\\camera_light_src_timing_controller_fpga.cmr" - }, - { - "blank": 1, - "code": 1, - "comment": 0, - "filename": "compile\\bak\\src_ttl_parser.cmr" - }, - { - "blank": 1, - "code": 1, - "comment": 0, - "filename": "compile\\bak\\Top.cmr" - }, - { - "blank": 0, - "code": 1385, - "comment": 0, - "filename": "compile\\cmr.db" - }, - { - "blank": 202, - "code": 209, - "comment": 0, - "filename": "compile\\formal.pvf" - }, - { - "blank": 1, - "code": 469, - "comment": 0, - "filename": "compile\\logbackup\\run_2024-01-11-18-32-44.log" - }, - { - "blank": 1, - "code": 465, - "comment": 0, - "filename": "compile\\logbackup\\run_2024-01-11-18-34-31.log" - }, - { - "blank": 1, - "code": 464, - "comment": 0, - "filename": "compile\\logbackup\\run_2024-01-11-18-35-36.log" - }, - { - "blank": 1, - "code": 464, - "comment": 0, - "filename": "compile\\logbackup\\run_2024-01-11-18-35-49.log" - }, - { - "blank": 0, - "code": 51, - "comment": 0, - "filename": "compile\\logbackup\\run_2024-01-11-18-40-38.log" - }, - { - "blank": 0, - "code": 167, - "comment": 0, - "filename": "compile\\logbackup\\run_2024-01-11-18-41-10.log" - }, - { - "blank": 1, - "code": 378, - "comment": 0, - "filename": "compile\\logbackup\\run_2024-01-11-18-41-32.log" - }, - { - "blank": 1, - "code": 378, - "comment": 0, - "filename": "compile\\logbackup\\run_2024-01-11-18-41-52.log" - }, - { - "blank": 8, - "code": 565, - "comment": 0, - "filename": "compile\\logbackup\\run_2024-01-11-18-42-10.log" - }, - { - "blank": 8, - "code": 583, - "comment": 0, - "filename": "compile\\logbackup\\run_2024-01-11-20-39-09.log" - }, - { - "blank": 8, - "code": 582, - "comment": 0, - "filename": "compile\\run.log" - }, - { - "blank": 1, - "code": 1, - "comment": 0, - "filename": "compile\\Top.cmr" - }, - { - "filename": "compile\\Top_comp.adf", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "blank": 0, - "code": 32, - "comment": 0, - "filename": "constraint_backup\\camera_light_src_timing_controller_fpga_2023_12_08_17_04_22.fdc" - }, - { - "blank": 0, - "code": 58, - "comment": 0, - "filename": "constraint_backup\\camera_light_src_timing_controller_fpga_2023_12_08_17_06_54.fdc" - }, - { - "blank": 0, - "code": 59, - "comment": 0, - "filename": "constraint_backup\\camera_light_src_timing_controller_fpga_2023_12_08_19_10_31.fdc" - }, - { - "blank": 0, - "code": 59, - "comment": 0, - "filename": "constraint_backup\\camera_light_src_timing_controller_fpga_2023_12_08_19_12_05.fdc" - }, - { - "blank": 0, - "code": 60, - "comment": 0, - "filename": "constraint_backup\\camera_light_src_timing_controller_fpga_2023_12_08_19_12_53.fdc" - }, - { - "blank": 0, - "code": 60, - "comment": 0, - "filename": "constraint_backup\\camera_light_src_timing_controller_fpga_2023_12_13_14_05_07.fdc" - }, - { - "blank": 0, - "code": 66, - "comment": 0, - "filename": "constraint_backup\\camera_light_src_timing_controller_fpga_2023_12_13_14_23_52.fdc" - }, - { - "blank": 0, - "code": 66, - "comment": 0, - "filename": "constraint_backup\\camera_light_src_timing_controller_fpga_2023_12_13_14_27_06.fdc" - }, - { - "blank": 0, - "code": 66, - "comment": 0, - "filename": "constraint_backup\\camera_light_src_timing_controller_fpga_2023_12_13_14_34_42.fdc" - }, - { - "blank": 0, - "code": 72, - "comment": 0, - "filename": "constraint_backup\\camera_light_src_timing_controller_fpga_2023_12_13_15_08_22.fdc" - }, - { - "blank": 0, - "code": 78, - "comment": 0, - "filename": "constraint_backup\\camera_light_src_timing_controller_fpga_2023_12_13_15_27_17.fdc" - }, - { - "blank": 0, - "code": 84, - "comment": 0, - "filename": "constraint_backup\\camera_light_src_timing_controller_fpga_2023_12_13_15_49_20.fdc" - }, - { - "blank": 0, - "code": 84, - "comment": 0, - "filename": "constraint_backup\\camera_light_src_timing_controller_fpga_2023_12_13_16_03_13.fdc" - }, - { - "blank": 0, - "code": 126, - "comment": 0, - "filename": "constraint_backup\\camera_light_src_timing_controller_fpga_2023_12_13_22_12_43.fdc" - }, - { - "blank": 0, - "code": 126, - "comment": 0, - "filename": "constraint_backup\\camera_light_src_timing_controller_fpga_2023_12_13_22_49_15.fdc" - }, - { - "blank": 0, - "code": 156, - "comment": 0, - "filename": "constraint_backup\\camera_light_src_timing_controller_fpga_2023_12_14_21_17_52.fdc" - }, - { - "blank": 0, - "code": 166, - "comment": 0, - "filename": "constraint_backup\\camera_light_src_timing_controller_fpga_2023_12_14_21_55_40.fdc" - }, - { - "blank": 0, - "code": 8, - "comment": 0, - "filename": "constraint_backup\\camera_light_src_timing_controller_fpga_2024_01_06_19_22_21.fdc" - }, - { - "blank": 0, - "code": 14, - "comment": 0, - "filename": "constraint_backup\\camera_light_src_timing_controller_fpga_2024_01_07_14_16_20.fdc" - }, - { - "blank": 0, - "code": 32, - "comment": 0, - "filename": "constraint_backup\\camera_light_src_timing_controller_fpga_2024_01_08_15_30_41.fdc" - }, - { - "blank": 3, - "code": 144, - "comment": 0, - "filename": "constraint_backup\\camera_light_src_timing_controller_fpga_2024_01_08_15_39_15.fdc" - }, - { - "blank": 5, - "code": 162, - "comment": 0, - "filename": "constraint_backup\\camera_light_src_timing_controller_fpga_2024_01_08_15_44_05.fdc" - }, - { - "blank": 10, - "code": 541, - "comment": 0, - "filename": "constraint_backup\\camera_light_src_timing_controller_fpga_2024_01_08_16_40_22.fdc" - }, - { - "blank": 10, - "code": 545, - "comment": 0, - "filename": "constraint_backup\\camera_light_src_timing_controller_fpga_2024_01_08_16_54_45.fdc" - }, - { - "filename": "data.wf", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "blank": 0, - "code": 5671, - "comment": 0, - "filename": "device_map\\bak\\dmr.db" - }, - { - "blank": 21, - "code": 169, - "comment": 0, - "filename": "device_map\\bak\\camera_light_src_timing_controller_fpga.dmr" - }, - { - "blank": 0, - "code": 240, - "comment": 0, - "filename": "device_map\\bak\\camera_light_src_timing_controller_fpga_dmr.prt" - }, - { - "blank": 21, - "code": 394, - "comment": 0, - "filename": "device_map\\bak\\Top.dmr" - }, - { - "blank": 0, - "code": 240, - "comment": 0, - "filename": "device_map\\bak\\Top_dmr.prt" - }, - { - "blank": 0, - "code": 853, - "comment": 0, - "filename": "device_map\\formal.pvf" - }, - { - "blank": 1, - "code": 69, - "comment": 0, - "filename": "device_map\\camera_light_src_timing_controller_fpga.pcf" - }, - { - "blank": 2, - "code": 67, - "comment": 0, - "filename": "device_map\\logbackup\\run_2024-01-09-15-13-07.log" - }, - { - "blank": 2, - "code": 67, - "comment": 0, - "filename": "device_map\\logbackup\\run_2024-01-10-21-59-05.log" - }, - { - "blank": 2, - "code": 73, - "comment": 0, - "filename": "device_map\\logbackup\\run_2024-01-10-22-06-06.log" - }, - { - "blank": 2, - "code": 73, - "comment": 0, - "filename": "device_map\\logbackup\\run_2024-01-11-09-22-30.log" - }, - { - "blank": 2, - "code": 73, - "comment": 0, - "filename": "device_map\\logbackup\\run_2024-01-11-09-40-15.log" - }, - { - "blank": 2, - "code": 73, - "comment": 0, - "filename": "device_map\\logbackup\\run_2024-01-11-09-43-56.log" - }, - { - "blank": 2, - "code": 73, - "comment": 0, - "filename": "device_map\\logbackup\\run_2024-01-11-11-13-42.log" - }, - { - "blank": 2, - "code": 73, - "comment": 0, - "filename": "device_map\\logbackup\\run_2024-01-11-11-47-31.log" - }, - { - "blank": 2, - "code": 73, - "comment": 0, - "filename": "device_map\\logbackup\\run_2024-01-11-16-09-16.log" - }, - { - "blank": 2, - "code": 73, - "comment": 0, - "filename": "device_map\\logbackup\\run_2024-01-11-16-32-24.log" - }, - { - "blank": 2, - "code": 73, - "comment": 0, - "filename": "device_map\\run.log" - }, - { - "blank": 0, - "code": 280, - "comment": 0, - "filename": "generate_bitstream\\bak\\bgr.db" - }, - { - "blank": 4, - "code": 19, - "comment": 0, - "filename": "generate_bitstream\\bak\\camera_light_src_timing_controller_fpga.bgr" - }, - { - "filename": "generate_bitstream\\bak\\camera_light_src_timing_controller_fpga.sbit", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "filename": "generate_bitstream\\bak\\camera_light_src_timing_controller_fpga.smsk", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "blank": 4, - "code": 19, - "comment": 0, - "filename": "generate_bitstream\\bak\\Top.bgr" - }, - { - "filename": "generate_bitstream\\bak\\Top.sbit", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "filename": "generate_bitstream\\bak\\Top.smsk", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "blank": 0, - "code": 24, - "comment": 0, - "filename": "generate_bitstream\\logbackup\\run_2024-01-09-15-15-53.log" - }, - { - "blank": 0, - "code": 24, - "comment": 0, - "filename": "generate_bitstream\\logbackup\\run_2024-01-10-22-00-59.log" - }, - { - "blank": 0, - "code": 24, - "comment": 0, - "filename": "generate_bitstream\\logbackup\\run_2024-01-10-22-07-57.log" - }, - { - "blank": 0, - "code": 24, - "comment": 0, - "filename": "generate_bitstream\\logbackup\\run_2024-01-11-09-23-14.log" - }, - { - "blank": 0, - "code": 24, - "comment": 0, - "filename": "generate_bitstream\\logbackup\\run_2024-01-11-09-41-40.log" - }, - { - "blank": 0, - "code": 24, - "comment": 0, - "filename": "generate_bitstream\\logbackup\\run_2024-01-11-09-45-33.log" - }, - { - "blank": 0, - "code": 24, - "comment": 0, - "filename": "generate_bitstream\\logbackup\\run_2024-01-11-11-15-51.log" - }, - { - "blank": 0, - "code": 24, - "comment": 0, - "filename": "generate_bitstream\\logbackup\\run_2024-01-11-11-49-40.log" - }, - { - "blank": 0, - "code": 24, - "comment": 0, - "filename": "generate_bitstream\\logbackup\\run_2024-01-11-16-10-09.log" - }, - { - "blank": 0, - "code": 24, - "comment": 0, - "filename": "generate_bitstream\\logbackup\\run_2024-01-11-16-33-19.log" - }, - { - "blank": 0, - "code": 24, - "comment": 0, - "filename": "generate_bitstream\\run.log" - }, - { - "filename": "generate_bitstream\\Top.sfc", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "blank": 0, - "code": 20, - "comment": 0, - "filename": "generate_netlist\\run.log" - }, - { - "blank": 1, - "code": 1795, - "comment": 0, - "filename": "impl.tcl" - }, - { - "blank": 0, - "code": 641, - "comment": 0, - "filename": "ipcore\\genlock_sig_gen_pll\\genlock_sig_gen_pll.idf" - }, - { - "blank": 0, - "code": 2, - "comment": 0, - "filename": "ipcore\\inclkpll\\.last_generated" - }, - { - "blank": 0, - "code": 17, - "comment": 0, - "filename": "ipcore\\inclkpll\\generate.log" - }, - { - "blank": 0, - "code": 651, - "comment": 0, - "filename": "ipcore\\inclkpll\\inclkpll.idf" - }, - { - "blank": 8, - "code": 43, - "comment": 15, - "filename": "ipcore\\inclkpll\\inclkpll.v" - }, - { - "blank": 24, - "code": 134, - "comment": 18, - "filename": "ipcore\\inclkpll\\inclkpll_tb.v" - }, - { - "blank": 2, - "code": 5, - "comment": 9, - "filename": "ipcore\\inclkpll\\inclkpll_tmpl.v" - }, - { - "blank": 4, - "code": 19, - "comment": 0, - "filename": "ipcore\\inclkpll\\inclkpll_tmpl.vhdl" - }, - { - "blank": 0, - "code": 108, - "comment": 0, - "filename": "ipcore\\ram\\ram.idf" - }, - { - "blank": 0, - "code": 122, - "comment": 0, - "filename": "ipcore\\smult\\smult.idf" - }, - { - "blank": 0, - "code": 2, - "comment": 0, - "filename": "ipcore\\SPLL\\.last_generated" - }, - { - "blank": 0, - "code": 17, - "comment": 0, - "filename": "ipcore\\SPLL\\generate.log" - }, - { - "blank": 0, - "code": 663, - "comment": 0, - "filename": "ipcore\\SPLL\\SPLL.idf" - }, - { - "blank": 8, - "code": 45, - "comment": 15, - "filename": "ipcore\\SPLL\\SPLL.v" - }, - { - "blank": 24, - "code": 136, - "comment": 18, - "filename": "ipcore\\SPLL\\SPLL_tb.v" - }, - { - "blank": 2, - "code": 7, - "comment": 11, - "filename": "ipcore\\SPLL\\SPLL_tmpl.v" - }, - { - "blank": 4, - "code": 23, - "comment": 0, - "filename": "ipcore\\SPLL\\SPLL_tmpl.vhdl" - }, - { - "blank": 0, - "code": 641, - "comment": 0, - "filename": "ipcore\\ttl_pll\\ttl_pll.idf" - }, - { - "blank": 12, - "code": 563, - "comment": 0, - "filename": "camera_light_src_timing_controller_fpga.fdc" - }, - { - "blank": 0, - "code": 295, - "comment": 0, - "filename": "camera_light_src_timing_controller_fpga.pds" - }, - { - "blank": 1, - "code": 16, - "comment": 0, - "filename": "log\\cfg.log" - }, - { - "blank": 0, - "code": 17102, - "comment": 0, - "filename": "log\\configuration.log" - }, - { - "blank": 0, - "code": 7, - "comment": 0, - "filename": "log\\dbg.log" - }, - { - "blank": 13, - "code": 13, - "comment": 0, - "filename": "log\\DbgTclCmd.log" - }, - { - "blank": 26, - "code": 2381, - "comment": 0, - "filename": "log\\debugger.log" - }, - { - "blank": 0, - "code": 23, - "comment": 0, - "filename": "log\\ins.log" - }, - { - "blank": 0, - "code": 7, - "comment": 0, - "filename": "log\\js.log" - }, - { - "blank": 0, - "code": 13300, - "comment": 0, - "filename": "log\\jtagserver.log" - }, - { - "blank": 3, - "code": 290, - "comment": 0, - "filename": "logbackup\\run_2024-01-08-20-56-59.log" - }, - { - "blank": 2109, - "code": 18287, - "comment": 0, - "filename": "logbackup\\run_2024-01-08-21-33-22.log" - }, - { - "blank": 3, - "code": 221, - "comment": 0, - "filename": "logbackup\\run_2024-01-08-21-38-14.log" - }, - { - "blank": 387, - "code": 3455, - "comment": 0, - "filename": "logbackup\\run_2024-01-08-21-46-47.log" - }, - { - "blank": 3, - "code": 329, - "comment": 0, - "filename": "logbackup\\run_2024-01-08-22-10-08.log" - }, - { - "blank": 1705, - "code": 15202, - "comment": 0, - "filename": "logbackup\\run_2024-01-08-22-25-01.log" - }, - { - "blank": 5, - "code": 517, - "comment": 0, - "filename": "logbackup\\run_2024-01-09-11-00-15.log" - }, - { - "blank": 220, - "code": 7608, - "comment": 0, - "filename": "logbackup\\run_2024-01-09-22-55-17.log" - }, - { - "blank": 0, - "code": 18, - "comment": 0, - "filename": "logbackup\\run_2024-01-10-11-09-19.log" - }, - { - "blank": 3307, - "code": 47493, - "comment": 0, - "filename": "logbackup\\run_2024-01-11-12-54-38.log" - }, - { - "blank": 0, - "code": 7, - "comment": 0, - "filename": "msg_level.txt" - }, - { - "blank": 0, - "code": 299, - "comment": 0, - "filename": "pango_sim_libraries\\adc\\_info" - }, - { - "filename": "pango_sim_libraries\\adc\\_lib.qdb", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "filename": "pango_sim_libraries\\adc\\_lib1_1.qdb", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "filename": "pango_sim_libraries\\adc\\_lib1_1.qpg", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "filename": "pango_sim_libraries\\adc\\_lib1_1.qtl", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "blank": 0, - "code": 4, - "comment": 0, - "filename": "pango_sim_libraries\\adc\\_vmake" - }, - { - "blank": 0, - "code": 587, - "comment": 0, - "filename": "pango_sim_libraries\\adc_e2\\_info" - }, - { - "filename": "pango_sim_libraries\\adc_e2\\_lib.qdb", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "filename": "pango_sim_libraries\\adc_e2\\_lib1_2.qdb", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "filename": "pango_sim_libraries\\adc_e2\\_lib1_2.qpg", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "filename": "pango_sim_libraries\\adc_e2\\_lib1_2.qtl", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "blank": 0, - "code": 4, - "comment": 0, - "filename": "pango_sim_libraries\\adc_e2\\_vmake" - }, - { - "blank": 0, - "code": 59, - "comment": 0, - "filename": "pango_sim_libraries\\ddc_e2\\_info" - }, - { - "filename": "pango_sim_libraries\\ddc_e2\\_lib.qdb", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "filename": "pango_sim_libraries\\ddc_e2\\_lib1_0.qdb", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "filename": "pango_sim_libraries\\ddc_e2\\_lib1_0.qpg", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "filename": "pango_sim_libraries\\ddc_e2\\_lib1_0.qtl", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "blank": 0, - "code": 4, - "comment": 0, - "filename": "pango_sim_libraries\\ddc_e2\\_vmake" - }, - { - "blank": 0, - "code": 3656, - "comment": 1, - "filename": "pango_sim_libraries\\ddrc\\_info" - }, - { - "filename": "pango_sim_libraries\\ddrc\\_lib.qdb", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "filename": "pango_sim_libraries\\ddrc\\_lib1_6.qdb", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "filename": "pango_sim_libraries\\ddrc\\_lib1_6.qpg", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "filename": "pango_sim_libraries\\ddrc\\_lib1_6.qtl", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "blank": 0, - "code": 4, - "comment": 0, - "filename": "pango_sim_libraries\\ddrc\\_vmake" - }, - { - "blank": 0, - "code": 635, - "comment": 0, - "filename": "pango_sim_libraries\\ddrphy\\_info" - }, - { - "filename": "pango_sim_libraries\\ddrphy\\_lib.qdb", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "filename": "pango_sim_libraries\\ddrphy\\_lib1_2.qdb", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "filename": "pango_sim_libraries\\ddrphy\\_lib1_2.qpg", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "filename": "pango_sim_libraries\\ddrphy\\_lib1_2.qtl", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "blank": 0, - "code": 4, - "comment": 0, - "filename": "pango_sim_libraries\\ddrphy\\_vmake" - }, - { - "blank": 0, - "code": 179, - "comment": 0, - "filename": "pango_sim_libraries\\dll_e2\\_info" - }, - { - "filename": "pango_sim_libraries\\dll_e2\\_lib.qdb", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "filename": "pango_sim_libraries\\dll_e2\\_lib1_0.qdb", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "filename": "pango_sim_libraries\\dll_e2\\_lib1_0.qpg", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "filename": "pango_sim_libraries\\dll_e2\\_lib1_0.qtl", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "blank": 0, - "code": 4, - "comment": 0, - "filename": "pango_sim_libraries\\dll_e2\\_vmake" - }, - { - "blank": 0, - "code": 6227, - "comment": 1, - "filename": "pango_sim_libraries\\hsst\\_info" - }, - { - "filename": "pango_sim_libraries\\hsst\\_lib.qdb", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "filename": "pango_sim_libraries\\hsst\\_lib1_6.qdb", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "filename": "pango_sim_libraries\\hsst\\_lib1_6.qpg", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "filename": "pango_sim_libraries\\hsst\\_lib1_6.qtl", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "blank": 0, - "code": 4, - "comment": 0, - "filename": "pango_sim_libraries\\hsst\\_vmake" - }, - { - "blank": 0, - "code": 9299, - "comment": 2, - "filename": "pango_sim_libraries\\hsst_e2\\_info" - }, - { - "filename": "pango_sim_libraries\\hsst_e2\\_lib.qdb", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "filename": "pango_sim_libraries\\hsst_e2\\_lib1_6.qdb", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "filename": "pango_sim_libraries\\hsst_e2\\_lib1_6.qpg", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "filename": "pango_sim_libraries\\hsst_e2\\_lib1_6.qtl", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "blank": 0, - "code": 4, - "comment": 0, - "filename": "pango_sim_libraries\\hsst_e2\\_vmake" - }, - { - "blank": 0, - "code": 35, - "comment": 0, - "filename": "pango_sim_libraries\\hssthp_bufds\\_info" - }, - { - "filename": "pango_sim_libraries\\hssthp_bufds\\_lib.qdb", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "filename": "pango_sim_libraries\\hssthp_bufds\\_lib1_0.qdb", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "blank": 0, - "code": 0, - "comment": 0, - "filename": "pango_sim_libraries\\hssthp_bufds\\_lib1_0.qpg" - }, - { - "filename": "pango_sim_libraries\\hssthp_bufds\\_lib1_0.qtl", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "blank": 0, - "code": 4, - "comment": 0, - "filename": "pango_sim_libraries\\hssthp_bufds\\_vmake" - }, - { - "blank": 0, - "code": 4187, - "comment": 4, - "filename": "pango_sim_libraries\\hssthp_hpll\\_info" - }, - { - "filename": "pango_sim_libraries\\hssthp_hpll\\_lib.qdb", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "filename": "pango_sim_libraries\\hssthp_hpll\\_lib1_6.qdb", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "filename": "pango_sim_libraries\\hssthp_hpll\\_lib1_6.qpg", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "filename": "pango_sim_libraries\\hssthp_hpll\\_lib1_6.qtl", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "blank": 0, - "code": 4, - "comment": 0, - "filename": "pango_sim_libraries\\hssthp_hpll\\_vmake" - }, - { - "blank": 0, - "code": 12035, - "comment": 7, - "filename": "pango_sim_libraries\\hssthp_lane\\_info" - }, - { - "filename": "pango_sim_libraries\\hssthp_lane\\_lib.qdb", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "filename": "pango_sim_libraries\\hssthp_lane\\_lib1_6.qdb", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "filename": "pango_sim_libraries\\hssthp_lane\\_lib1_6.qpg", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "filename": "pango_sim_libraries\\hssthp_lane\\_lib1_6.qtl", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "blank": 0, - "code": 4, - "comment": 0, - "filename": "pango_sim_libraries\\hssthp_lane\\_vmake" - }, - { - "blank": 0, - "code": 8171, - "comment": 1, - "filename": "pango_sim_libraries\\hsstlp_lane\\_info" - }, - { - "filename": "pango_sim_libraries\\hsstlp_lane\\_lib.qdb", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "filename": "pango_sim_libraries\\hsstlp_lane\\_lib1_6.qdb", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "filename": "pango_sim_libraries\\hsstlp_lane\\_lib1_6.qpg", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "filename": "pango_sim_libraries\\hsstlp_lane\\_lib1_6.qtl", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "blank": 0, - "code": 4, - "comment": 0, - "filename": "pango_sim_libraries\\hsstlp_lane\\_vmake" - }, - { - "blank": 0, - "code": 2963, - "comment": 1, - "filename": "pango_sim_libraries\\hsstlp_pll\\_info" - }, - { - "filename": "pango_sim_libraries\\hsstlp_pll\\_lib.qdb", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "filename": "pango_sim_libraries\\hsstlp_pll\\_lib1_6.qdb", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "filename": "pango_sim_libraries\\hsstlp_pll\\_lib1_6.qpg", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "filename": "pango_sim_libraries\\hsstlp_pll\\_lib1_6.qtl", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "blank": 0, - "code": 4, - "comment": 0, - "filename": "pango_sim_libraries\\hsstlp_pll\\_vmake" - }, - { - "blank": 0, - "code": 3491, - "comment": 0, - "filename": "pango_sim_libraries\\iolhp_fifo\\_info" - }, - { - "filename": "pango_sim_libraries\\iolhp_fifo\\_lib.qdb", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "filename": "pango_sim_libraries\\iolhp_fifo\\_lib1_6.qdb", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "blank": 0, - "code": 0, - "comment": 0, - "filename": "pango_sim_libraries\\iolhp_fifo\\_lib1_6.qpg" - }, - { - "filename": "pango_sim_libraries\\iolhp_fifo\\_lib1_6.qtl", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "blank": 0, - "code": 4, - "comment": 0, - "filename": "pango_sim_libraries\\iolhp_fifo\\_vmake" - }, - { - "blank": 0, - "code": 2843, - "comment": 0, - "filename": "pango_sim_libraries\\iolhr_dft\\_info" - }, - { - "filename": "pango_sim_libraries\\iolhr_dft\\_lib.qdb", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "filename": "pango_sim_libraries\\iolhr_dft\\_lib1_6.qdb", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "filename": "pango_sim_libraries\\iolhr_dft\\_lib1_6.qpg", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "filename": "pango_sim_libraries\\iolhr_dft\\_lib1_6.qtl", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "blank": 0, - "code": 4, - "comment": 0, - "filename": "pango_sim_libraries\\iolhr_dft\\_vmake" - }, - { - "blank": 0, - "code": 155, - "comment": 0, - "filename": "pango_sim_libraries\\ipal_e1\\_info" - }, - { - "filename": "pango_sim_libraries\\ipal_e1\\_lib.qdb", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "filename": "pango_sim_libraries\\ipal_e1\\_lib1_0.qdb", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "filename": "pango_sim_libraries\\ipal_e1\\_lib1_0.qpg", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "filename": "pango_sim_libraries\\ipal_e1\\_lib1_0.qtl", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "blank": 0, - "code": 4, - "comment": 0, - "filename": "pango_sim_libraries\\ipal_e1\\_vmake" - }, - { - "blank": 0, - "code": 179, - "comment": 0, - "filename": "pango_sim_libraries\\ipal_e2\\_info" - }, - { - "filename": "pango_sim_libraries\\ipal_e2\\_lib.qdb", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "filename": "pango_sim_libraries\\ipal_e2\\_lib1_0.qdb", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "filename": "pango_sim_libraries\\ipal_e2\\_lib1_0.qpg", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "filename": "pango_sim_libraries\\ipal_e2\\_lib1_0.qtl", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "blank": 0, - "code": 4, - "comment": 0, - "filename": "pango_sim_libraries\\ipal_e2\\_vmake" - }, - { - "blank": 0, - "code": 59, - "comment": 0, - "filename": "pango_sim_libraries\\iserdes_e1\\_info" - }, - { - "filename": "pango_sim_libraries\\iserdes_e1\\_lib.qdb", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "filename": "pango_sim_libraries\\iserdes_e1\\_lib1_0.qdb", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "blank": 0, - "code": 0, - "comment": 0, - "filename": "pango_sim_libraries\\iserdes_e1\\_lib1_0.qpg" - }, - { - "filename": "pango_sim_libraries\\iserdes_e1\\_lib1_0.qtl", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "blank": 0, - "code": 4, - "comment": 0, - "filename": "pango_sim_libraries\\iserdes_e1\\_vmake" - }, - { - "blank": 0, - "code": 2627, - "comment": 1, - "filename": "pango_sim_libraries\\iserdes_e2\\_info" - }, - { - "filename": "pango_sim_libraries\\iserdes_e2\\_lib.qdb", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "filename": "pango_sim_libraries\\iserdes_e2\\_lib1_6.qdb", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "filename": "pango_sim_libraries\\iserdes_e2\\_lib1_6.qpg", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "filename": "pango_sim_libraries\\iserdes_e2\\_lib1_6.qtl", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "blank": 0, - "code": 4, - "comment": 0, - "filename": "pango_sim_libraries\\iserdes_e2\\_vmake" - }, - { - "blank": 0, - "code": 203, - "comment": 0, - "filename": "pango_sim_libraries\\iserdes_fifo\\_info" - }, - { - "filename": "pango_sim_libraries\\iserdes_fifo\\_lib.qdb", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "filename": "pango_sim_libraries\\iserdes_fifo\\_lib1_0.qdb", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "blank": 0, - "code": 0, - "comment": 0, - "filename": "pango_sim_libraries\\iserdes_fifo\\_lib1_0.qpg" - }, - { - "filename": "pango_sim_libraries\\iserdes_fifo\\_lib1_0.qtl", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "blank": 0, - "code": 4, - "comment": 0, - "filename": "pango_sim_libraries\\iserdes_fifo\\_vmake" - }, - { - "blank": 353, - "code": 72, - "comment": 1662, - "filename": "pango_sim_libraries\\modelsim.ini" - }, - { - "blank": 2, - "code": 58, - "comment": 65, - "filename": "pango_sim_libraries\\msim_pango.tcl" - }, - { - "blank": 0, - "code": 59, - "comment": 0, - "filename": "pango_sim_libraries\\oserdes_e1\\_info" - }, - { - "filename": "pango_sim_libraries\\oserdes_e1\\_lib.qdb", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "filename": "pango_sim_libraries\\oserdes_e1\\_lib1_0.qdb", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "blank": 0, - "code": 0, - "comment": 0, - "filename": "pango_sim_libraries\\oserdes_e1\\_lib1_0.qpg" - }, - { - "filename": "pango_sim_libraries\\oserdes_e1\\_lib1_0.qtl", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "blank": 0, - "code": 4, - "comment": 0, - "filename": "pango_sim_libraries\\oserdes_e1\\_vmake" - }, - { - "blank": 0, - "code": 2843, - "comment": 1, - "filename": "pango_sim_libraries\\oserdes_e2\\_info" - }, - { - "filename": "pango_sim_libraries\\oserdes_e2\\_lib.qdb", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "filename": "pango_sim_libraries\\oserdes_e2\\_lib1_6.qdb", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "filename": "pango_sim_libraries\\oserdes_e2\\_lib1_6.qpg", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "filename": "pango_sim_libraries\\oserdes_e2\\_lib1_6.qtl", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "blank": 0, - "code": 4, - "comment": 0, - "filename": "pango_sim_libraries\\oserdes_e2\\_vmake" - }, - { - "blank": 0, - "code": 203, - "comment": 0, - "filename": "pango_sim_libraries\\oserdes_fifo\\_info" - }, - { - "filename": "pango_sim_libraries\\oserdes_fifo\\_lib.qdb", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "filename": "pango_sim_libraries\\oserdes_fifo\\_lib1_0.qdb", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "blank": 0, - "code": 0, - "comment": 0, - "filename": "pango_sim_libraries\\oserdes_fifo\\_lib1_0.qpg" - }, - { - "filename": "pango_sim_libraries\\oserdes_fifo\\_lib1_0.qtl", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "blank": 0, - "code": 4, - "comment": 0, - "filename": "pango_sim_libraries\\oserdes_fifo\\_vmake" - }, - { - "blank": 0, - "code": 5699, - "comment": 2, - "filename": "pango_sim_libraries\\pciegen2\\_info" - }, - { - "filename": "pango_sim_libraries\\pciegen2\\_lib.qdb", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "filename": "pango_sim_libraries\\pciegen2\\_lib1_6.qdb", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "filename": "pango_sim_libraries\\pciegen2\\_lib1_6.qpg", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "filename": "pango_sim_libraries\\pciegen2\\_lib1_6.qtl", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "blank": 0, - "code": 4, - "comment": 0, - "filename": "pango_sim_libraries\\pciegen2\\_vmake" - }, - { - "blank": 0, - "code": 7434, - "comment": 2, - "filename": "pango_sim_libraries\\pciegen3\\_info" - }, - { - "filename": "pango_sim_libraries\\pciegen3\\_lib.qdb", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "filename": "pango_sim_libraries\\pciegen3\\_lib1_6.qdb", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "filename": "pango_sim_libraries\\pciegen3\\_lib1_6.qpg", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "filename": "pango_sim_libraries\\pciegen3\\_lib1_6.qtl", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "blank": 0, - "code": 4, - "comment": 0, - "filename": "pango_sim_libraries\\pciegen3\\_vmake" - }, - { - "blank": 0, - "code": 1, - "comment": 0, - "filename": "pango_sim_libraries\\run_sim.bat" - }, - { - "blank": 0, - "code": 1205, - "comment": 0, - "filename": "pango_sim_libraries\\transcript" - }, - { - "blank": 0, - "code": 16148, - "comment": 2, - "filename": "pango_sim_libraries\\usim\\_info" - }, - { - "filename": "pango_sim_libraries\\usim\\_lib.qdb", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "filename": "pango_sim_libraries\\usim\\_lib1_13.qdb", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "filename": "pango_sim_libraries\\usim\\_lib1_13.qpg", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "filename": "pango_sim_libraries\\usim\\_lib1_13.qtl", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "blank": 0, - "code": 4, - "comment": 0, - "filename": "pango_sim_libraries\\usim\\_vmake" - }, - { - "blank": 0, - "code": 14424, - "comment": 3, - "filename": "pango_sim_libraries\\vsim\\_info" - }, - { - "filename": "pango_sim_libraries\\vsim\\_lib.qdb", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "filename": "pango_sim_libraries\\vsim\\_lib1_13.qdb", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "filename": "pango_sim_libraries\\vsim\\_lib1_13.qpg", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "filename": "pango_sim_libraries\\vsim\\_lib1_13.qtl", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "blank": 0, - "code": 4, - "comment": 0, - "filename": "pango_sim_libraries\\vsim\\_vmake" - }, - { - "blank": 2351, - "code": 33751, - "comment": 0, - "filename": "pds.log" - }, - { - "blank": 4, - "code": 2, - "comment": 0, - "filename": "pin.md" - }, - { - "blank": 6, - "code": 43, - "comment": 0, - "filename": "place_route\\bak\\clock_utilization.txt" - }, - { - "blank": 13, - "code": 115, - "comment": 0, - "filename": "place_route\\bak\\camera_light_src_timing_controller_fpga.prr" - }, - { - "filename": "place_route\\bak\\camera_light_src_timing_controller_fpga_plc.adf", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "blank": 104, - "code": 1382, - "comment": 0, - "filename": "place_route\\bak\\camera_light_src_timing_controller_fpga_pnr.netlist" - }, - { - "blank": 0, - "code": 240, - "comment": 0, - "filename": "place_route\\bak\\camera_light_src_timing_controller_fpga_prr.prt" - }, - { - "blank": 0, - "code": 5824, - "comment": 0, - "filename": "place_route\\bak\\prr.db" - }, - { - "blank": 14, - "code": 248, - "comment": 0, - "filename": "place_route\\bak\\Top.prr" - }, - { - "filename": "place_route\\bak\\Top_plc.adf", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "blank": 7483, - "code": 92859, - "comment": 0, - "filename": "place_route\\bak\\Top_pnr.netlist" - }, - { - "blank": 0, - "code": 240, - "comment": 0, - "filename": "place_route\\bak\\Top_prr.prt" - }, - { - "blank": 0, - "code": 33, - "comment": 0, - "filename": "place_route\\des.log" - }, - { - "blank": 13, - "code": 531, - "comment": 0, - "filename": "place_route\\logbackup\\run_2024-01-09-15-15-18.log" - }, - { - "blank": 13, - "code": 522, - "comment": 0, - "filename": "place_route\\logbackup\\run_2024-01-10-22-00-40.log" - }, - { - "blank": 13, - "code": 511, - "comment": 0, - "filename": "place_route\\logbackup\\run_2024-01-10-22-07-41.log" - }, - { - "blank": 13, - "code": 587, - "comment": 0, - "filename": "place_route\\logbackup\\run_2024-01-11-09-23-00.log" - }, - { - "blank": 13, - "code": 556, - "comment": 0, - "filename": "place_route\\logbackup\\run_2024-01-11-09-41-26.log" - }, - { - "blank": 13, - "code": 501, - "comment": 0, - "filename": "place_route\\logbackup\\run_2024-01-11-09-45-12.log" - }, - { - "blank": 13, - "code": 530, - "comment": 0, - "filename": "place_route\\logbackup\\run_2024-01-11-11-15-25.log" - }, - { - "blank": 13, - "code": 530, - "comment": 0, - "filename": "place_route\\logbackup\\run_2024-01-11-11-49-15.log" - }, - { - "blank": 13, - "code": 514, - "comment": 0, - "filename": "place_route\\logbackup\\run_2024-01-11-16-09-52.log" - }, - { - "blank": 13, - "code": 536, - "comment": 0, - "filename": "place_route\\logbackup\\run_2024-01-11-16-33-01.log" - }, - { - "blank": 13, - "code": 513, - "comment": 0, - "filename": "place_route\\run.log" - }, - { - "blank": 23, - "code": 43, - "comment": 3, - "filename": "README.md" - }, - { - "blank": 0, - "code": 22, - "comment": 0, - "filename": "report_power\\run.log" - }, - { - "blank": 202, - "code": 1238, - "comment": 0, - "filename": "report_timing\\bak\\camera_light_src_timing_controller_fpga.rtr" - }, - { - "blank": 0, - "code": 31055, - "comment": 0, - "filename": "report_timing\\bak\\rtr.db" - }, - { - "blank": 202, - "code": 1516, - "comment": 0, - "filename": "report_timing\\bak\\Top.rtr" - }, - { - "blank": 316, - "code": 2102, - "comment": 0, - "filename": "report_timing\\logbackup\\run_2024-01-09-15-15-24.log" - }, - { - "blank": 316, - "code": 2578, - "comment": 0, - "filename": "report_timing\\logbackup\\run_2024-01-10-22-00-46.log" - }, - { - "blank": 208, - "code": 1564, - "comment": 0, - "filename": "report_timing\\logbackup\\run_2024-01-10-22-07-47.log" - }, - { - "blank": 208, - "code": 1492, - "comment": 0, - "filename": "report_timing\\logbackup\\run_2024-01-11-09-23-05.log" - }, - { - "blank": 208, - "code": 1476, - "comment": 0, - "filename": "report_timing\\logbackup\\run_2024-01-11-09-41-31.log" - }, - { - "blank": 208, - "code": 1520, - "comment": 0, - "filename": "report_timing\\logbackup\\run_2024-01-11-09-45-18.log" - }, - { - "blank": 208, - "code": 1480, - "comment": 0, - "filename": "report_timing\\logbackup\\run_2024-01-11-11-15-32.log" - }, - { - "blank": 208, - "code": 1480, - "comment": 0, - "filename": "report_timing\\logbackup\\run_2024-01-11-11-49-21.log" - }, - { - "blank": 208, - "code": 1536, - "comment": 0, - "filename": "report_timing\\logbackup\\run_2024-01-11-16-09-57.log" - }, - { - "blank": 208, - "code": 1634, - "comment": 0, - "filename": "report_timing\\logbackup\\run_2024-01-11-16-33-06.log" - }, - { - "blank": 208, - "code": 1610, - "comment": 0, - "filename": "report_timing\\run.log" - }, - { - "blank": 2265, - "code": 30854, - "comment": 0, - "filename": "run.log" - }, - { - "blank": 353, - "code": 54, - "comment": 1662, - "filename": "sim\\behav\\modelsim.ini" - }, - { - "blank": 0, - "code": 10, - "comment": 0, - "filename": "sim\\behav\\run_behav.bat" - }, - { - "blank": 2, - "code": 51, - "comment": 0, - "filename": "sim\\behav\\run_behav_compile.tcl" - }, - { - "blank": 0, - "code": 626, - "comment": 4574, - "filename": "sim\\behav\\run_behav_simulate.log" - }, - { - "blank": 3, - "code": 11, - "comment": 0, - "filename": "sim\\behav\\run_behav_simulate.tcl" - }, - { - "filename": "sim\\behav\\vsim.wlf", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "blank": 0, - "code": 745, - "comment": 0, - "filename": "sim\\behav\\work\\_info" - }, - { - "filename": "sim\\behav\\work\\_lib.qdb", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "filename": "sim\\behav\\work\\_lib1_12.qdb", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "filename": "sim\\behav\\work\\_lib1_12.qpg", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "filename": "sim\\behav\\work\\_lib1_12.qtl", - "isbinaryfile": true, - "blank": 0, - "code": 0, - "comment": 0 - }, - { - "blank": 0, - "code": 4, - "comment": 0, - "filename": "sim\\behav\\work\\_vmake" - }, - { - "blank": 16, - "code": 60, - "comment": 32, - "filename": "source\\src\\camera_sync_signal_output.v" - }, - { - "blank": 3, - "code": 22, - "comment": 4, - "filename": "source\\src\\debuger.v" - }, - { - "blank": 0, - "code": 0, - "comment": 0, - "filename": "source\\src\\input\\src_genlock.v" - }, - { - "blank": 32, - "code": 0, - "comment": 176, - "filename": "source\\src\\input\\src_timecode.v" - }, - { - "blank": 15, - "code": 0, - "comment": 116, - "filename": "source\\src\\input\\src_ttl_parser.v" - }, - { - "blank": 23, - "code": 89, - "comment": 57, - "filename": "source\\src\\output\\ttl_output.v" - }, - { - "blank": 4, - "code": 41, - "comment": 6, - "filename": "source\\src\\rd_data_router.v" - }, - { - "blank": 32, - "code": 160, - "comment": 65, - "filename": "source\\src\\spi_reg_reader.v" - }, - { - "blank": 21, - "code": 132, - "comment": 8, - "filename": "source\\src\\timecode\\timecode_basesig_generator.v" - }, - { - "blank": 25, - "code": 87, - "comment": 6, - "filename": "source\\src\\timecode\\timecode_generator.v" - }, - { - "blank": 22, - "code": 124, - "comment": 221, - "filename": "source\\src\\timecode\\timecode_nextcode.v" - }, - { - "blank": 16, - "code": 89, - "comment": 12, - "filename": "source\\src\\timecode\\timecode_serialization.v" - }, - { - "blank": 22, - "code": 73, - "comment": 18, - "filename": "source\\src\\timecode_output.v" - }, - { - "blank": 25, - "code": 69, - "comment": 32, - "filename": "source\\src\\top.v" - }, - { - "blank": 40, - "code": 178, - "comment": 89, - "filename": "source\\src\\xsync_internal_generator.v" - }, - { - "blank": 22, - "code": 99, - "comment": 33, - "filename": "source\\src\\xsync_internal_sub\\internal_timecode_generator.v" - }, - { - "blank": 4, - "code": 17, - "comment": 4, - "filename": "source\\src\\zutils\\baud_rate_gen.v" - }, - { - "blank": 5, - "code": 54, - "comment": 3, - "filename": "source\\src\\zutils\\ztutils_timecode_next_code.v" - }, - { - "blank": 19, - "code": 82, - "comment": 85, - "filename": "source\\src\\zutils\\zutils_clk_parser.v" - }, - { - "blank": 2, - "code": 12, - "comment": 2, - "filename": "source\\src\\zutils\\zutils_debug_led.v" - }, - { - "blank": 5, - "code": 38, - "comment": 8, - "filename": "source\\src\\zutils\\zutils_edge_detecter.v" - }, - { - "blank": 14, - "code": 98, - "comment": 2, - "filename": "source\\src\\zutils\\zutils_genlock_clk_generator.v" - }, - { - "blank": 4, - "code": 61, - "comment": 1, - "filename": "source\\src\\zutils\\zutils_multiplexer_16t1.v" - }, - { - "blank": 0, - "code": 17, - "comment": 0, - "filename": "source\\src\\zutils\\zutils_multiplexer_2t1.v" - }, - { - "blank": 5, - "code": 109, - "comment": 0, - "filename": "source\\src\\zutils\\zutils_multiplexer_32t1.v" - }, - { - "blank": 6, - "code": 140, - "comment": 0, - "filename": "source\\src\\zutils\\zutils_multiplexer_32t1_v2.v" - }, - { - "blank": 2, - "code": 28, - "comment": 0, - "filename": "source\\src\\zutils\\zutils_multiplexer_4t1.v" - }, - { - "blank": 6, - "code": 30, - "comment": 0, - "filename": "source\\src\\zutils\\zutils_muti_debug_signal_gen.v" - }, - { - "blank": 11, - "code": 62, - "comment": 3, - "filename": "source\\src\\zutils\\zutils_pluse_generator.v" - }, - { - "blank": 5, - "code": 31, - "comment": 1, - "filename": "source\\src\\zutils\\zutils_pwm_generator.v" - }, - { - "blank": 7, - "code": 37, - "comment": 1, - "filename": "source\\src\\zutils\\zutils_pwm_generator_advanced.v" - }, - { - "blank": 8, - "code": 84, - "comment": 23, - "filename": "source\\src\\zutils\\zutils_register.v" - }, - { - "blank": 7, - "code": 85, - "comment": 5, - "filename": "source\\src\\zutils\\zutils_register.v.bak" - }, - { - "blank": 14, - "code": 73, - "comment": 16, - "filename": "source\\src\\zutils\\zutils_register_advanced.v" - }, - { - "blank": 1, - "code": 21, - "comment": 2, - "filename": "source\\src\\zutils\\zutils_reset_sig_gen.v" - }, - { - "blank": 2, - "code": 27, - "comment": 3, - "filename": "source\\src\\zutils\\zutils_signal_filter.v" - }, - { - "blank": 8, - "code": 68, - "comment": 2, - "filename": "source\\src\\zutils\\zutils_smpte_timecode_clk_generator.v" - }, - { - "blank": 14, - "code": 71, - "comment": 20, - "filename": "source\\src\\zutils\\zutils_timecode_convert.v" - }, - { - "blank": 31, - "code": 96, - "comment": 22, - "filename": "source\\src\\zutils\\zutils_timecode_serial_data_gen.v" - }, - { - "blank": 6, - "code": 22, - "comment": 3, - "filename": "source\\test\\test_baud_rate_gen.v" - }, - { - "blank": 17, - "code": 49, - "comment": 18, - "filename": "source\\test\\test_spi_reg_reader.v" - }, - { - "blank": 20, - "code": 54, - "comment": 17, - "filename": "source\\test\\test_timecode_generator.v" - }, - { - "blank": 24, - "code": 85, - "comment": 4, - "filename": "source\\test\\test_top.v" - }, - { - "blank": 11, - "code": 37, - "comment": 3, - "filename": "source\\test\\test_transmitter.v" - }, - { - "blank": 4, - "code": 22, - "comment": 2, - "filename": "source\\test\\test_uart_reg_reader.v" - }, - { - "blank": 41, - "code": 39, - "comment": 0, - "filename": "synthesize\\async_receiver.ccr" - }, - { - "blank": 1, - "code": 1, - "comment": 0, - "filename": "synthesize\\async_receiver.snr" - }, - { - "blank": 126, - "code": 892, - "comment": 0, - "filename": "synthesize\\bak\\camera_light_src_timing_controller_fpga.snr" - }, - { - "blank": 76, - "code": 1012, - "comment": 78, - "filename": "synthesize\\bak\\camera_light_src_timing_controller_fpga_syn.vm" - }, - { - "blank": 0, - "code": 431, - "comment": 0, - "filename": "synthesize\\bak\\snr.db" - }, - { - "blank": 127, - "code": 1224, - "comment": 0, - "filename": "synthesize\\bak\\Top.snr" - }, - { - "blank": 4538, - "code": 50611, - "comment": 5110, - "filename": "synthesize\\bak\\Top_syn.vm" - }, - { - "blank": 235, - "code": 252, - "comment": 0, - "filename": "synthesize\\formal.pvf" - }, - { - "blank": 31, - "code": 15, - "comment": 0, - "filename": "synthesize\\camera_light_src_timing_controller_fpga.ccr" - }, - { - "blank": 141, - "code": 1393, - "comment": 0, - "filename": "synthesize\\logbackup\\run_2024-01-11-15-21-16.log" - }, - { - "blank": 141, - "code": 1393, - "comment": 0, - "filename": "synthesize\\logbackup\\run_2024-01-11-15-23-20.log" - }, - { - "blank": 141, - "code": 1393, - "comment": 0, - "filename": "synthesize\\logbackup\\run_2024-01-11-15-23-41.log" - }, - { - "blank": 141, - "code": 1429, - "comment": 0, - "filename": "synthesize\\logbackup\\run_2024-01-11-15-28-07.log" - }, - { - "blank": 140, - "code": 1401, - "comment": 0, - "filename": "synthesize\\logbackup\\run_2024-01-11-16-09-11.log" - }, - { - "blank": 140, - "code": 1422, - "comment": 0, - "filename": "synthesize\\logbackup\\run_2024-01-11-16-32-19.log" - }, - { - "blank": 140, - "code": 1407, - "comment": 0, - "filename": "synthesize\\logbackup\\run_2024-01-11-17-11-00.log" - }, - { - "blank": 4, - "code": 149, - "comment": 0, - "filename": "synthesize\\logbackup\\run_2024-01-11-18-36-07.log" - }, - { - "blank": 140, - "code": 1395, - "comment": 0, - "filename": "synthesize\\logbackup\\run_2024-01-11-18-43-01.log" - }, - { - "blank": 33, - "code": 174, - "comment": 0, - "filename": "synthesize\\logbackup\\run_2024-01-11-20-39-12.log" - }, - { - "blank": 4, - "code": 152, - "comment": 0, - "filename": "synthesize\\run.log" - }, - { - "blank": 69, - "code": 155, - "comment": 0, - "filename": "synthesize\\src_ttl_parser.ccr" - }, - { - "blank": 1, - "code": 1, - "comment": 0, - "filename": "synthesize\\src_ttl_parser.snr" - }, - { - "blank": 31, - "code": 18, - "comment": 0, - "filename": "synthesize\\Top.ccr" - }, - { - "blank": 1, - "code": 1, - "comment": 0, - "filename": "synthesize\\Top.snr" - } - ] - } - ] -} \ No newline at end of file diff --git a/out/linecounter.txt b/out/linecounter.txt deleted file mode 100644 index 230fe0e..0000000 --- a/out/linecounter.txt +++ /dev/null @@ -1,457 +0,0 @@ -=============================================================================== -EXTENSION NAME : linecounter -EXTENSION VERSION : 0.2.7 -------------------------------------------------------------------------------- -count time : 2024-01-11 20:40:13 -count workspace : d:\workspace\fpga_demo\camera_light_src_timing_controller_fpga -total files : 413 -total code lines : 552462 -total comment lines : 14393 -total blank lines : 31258 - - statistics - | extension| total code| total comment| total blank|percent| - ------------------------------------------------------------------------- - | .md| 45| 3| 27| 0.0081| - | .fdc| 3427| 0| 40| 0.62| - | .txt| 50| 0| 6| 0.0091| - | .snr| 2119| 0| 256| 0.38| - | .ccr| 227| 0| 172| 0.041| - | .log| 233241| 4574| 16262| 42| - | .prt| 960| 0| 0| 0.17| - | .tcl| 1915| 65| 8| 0.35| - | .prr| 363| 0| 27| 0.066| - | .db| 46034| 0| 0| 8.3| - | .bat| 11| 0| 0| 0.0020| - | .ini| 126| 3324| 706| 0.023| - | | 106783| 28| 0| 19| - | .rtr| 2754| 0| 404| 0.50| - | .qpg| 0| 0| 0| 0.0| - | .netlist| 94241| 0| 7587| 17| - | .v| 3118| 1206| 641| 0.56| - | .pvf| 1314| 0| 437| 0.24| - | .vm| 51623| 5188| 4614| 9.3| - | .bak| 85| 5| 7| 0.015| - | .pds| 295| 0| 0| 0.053| - | .bgr| 38| 0| 8| 0.0069| - | .pcf| 69| 0| 1| 0.012| - | .cmr| 5| 0| 5|0.00091| - | .vhdl| 42| 0| 8| 0.0076| - | .idf| 2826| 0| 0| 0.51| - | .pdf| 188| 0| 0| 0.034| - | .dmr| 563| 0| 42| 0.10| - ------------------------------------------------------------------------- -.gitignore, code is 18, comment is 0, blank is 0. -ACPGL22G核心板原理图.pdf, code is 188, comment is 0, blank is 0. -compile\bak\async_receiver.cmr, code is 1, comment is 0, blank is 1. -compile\bak\cmr.db, code is 1388, comment is 0, blank is 0. -compile\bak\camera_light_src_timing_controller_fpga.cmr, code is 1, comment is 0, blank is 1. -compile\bak\src_ttl_parser.cmr, code is 1, comment is 0, blank is 1. -compile\bak\Top.cmr, code is 1, comment is 0, blank is 1. -compile\cmr.db, code is 1385, comment is 0, blank is 0. -compile\formal.pvf, code is 209, comment is 0, blank is 202. -compile\logbackup\run_2024-01-11-18-32-44.log, code is 469, comment is 0, blank is 1. -compile\logbackup\run_2024-01-11-18-34-31.log, code is 465, comment is 0, blank is 1. -compile\logbackup\run_2024-01-11-18-35-36.log, code is 464, comment is 0, blank is 1. -compile\logbackup\run_2024-01-11-18-35-49.log, code is 464, comment is 0, blank is 1. -compile\logbackup\run_2024-01-11-18-40-38.log, code is 51, comment is 0, blank is 0. -compile\logbackup\run_2024-01-11-18-41-10.log, code is 167, comment is 0, blank is 0. -compile\logbackup\run_2024-01-11-18-41-32.log, code is 378, comment is 0, blank is 1. -compile\logbackup\run_2024-01-11-18-41-52.log, code is 378, comment is 0, blank is 1. -compile\logbackup\run_2024-01-11-18-42-10.log, code is 565, comment is 0, blank is 8. -compile\logbackup\run_2024-01-11-20-39-09.log, code is 583, comment is 0, blank is 8. -compile\run.log, code is 582, comment is 0, blank is 8. -compile\Top.cmr, code is 1, comment is 0, blank is 1. -compile\Top_comp.adf, it is a binary file. -constraint_backup\camera_light_src_timing_controller_fpga_2023_12_08_17_04_22.fdc, code is 32, comment is 0, blank is 0. -constraint_backup\camera_light_src_timing_controller_fpga_2023_12_08_17_06_54.fdc, code is 58, comment is 0, blank is 0. -constraint_backup\camera_light_src_timing_controller_fpga_2023_12_08_19_10_31.fdc, code is 59, comment is 0, blank is 0. -constraint_backup\camera_light_src_timing_controller_fpga_2023_12_08_19_12_05.fdc, code is 59, comment is 0, blank is 0. -constraint_backup\camera_light_src_timing_controller_fpga_2023_12_08_19_12_53.fdc, code is 60, comment is 0, blank is 0. -constraint_backup\camera_light_src_timing_controller_fpga_2023_12_13_14_05_07.fdc, code is 60, comment is 0, blank is 0. -constraint_backup\camera_light_src_timing_controller_fpga_2023_12_13_14_23_52.fdc, code is 66, comment is 0, blank is 0. -constraint_backup\camera_light_src_timing_controller_fpga_2023_12_13_14_27_06.fdc, code is 66, comment is 0, blank is 0. -constraint_backup\camera_light_src_timing_controller_fpga_2023_12_13_14_34_42.fdc, code is 66, comment is 0, blank is 0. -constraint_backup\camera_light_src_timing_controller_fpga_2023_12_13_15_08_22.fdc, code is 72, comment is 0, blank is 0. -constraint_backup\camera_light_src_timing_controller_fpga_2023_12_13_15_27_17.fdc, code is 78, comment is 0, blank is 0. -constraint_backup\camera_light_src_timing_controller_fpga_2023_12_13_15_49_20.fdc, code is 84, comment is 0, blank is 0. -constraint_backup\camera_light_src_timing_controller_fpga_2023_12_13_16_03_13.fdc, code is 84, comment is 0, blank is 0. -constraint_backup\camera_light_src_timing_controller_fpga_2023_12_13_22_12_43.fdc, code is 126, comment is 0, blank is 0. -constraint_backup\camera_light_src_timing_controller_fpga_2023_12_13_22_49_15.fdc, code is 126, comment is 0, blank is 0. -constraint_backup\camera_light_src_timing_controller_fpga_2023_12_14_21_17_52.fdc, code is 156, comment is 0, blank is 0. -constraint_backup\camera_light_src_timing_controller_fpga_2023_12_14_21_55_40.fdc, code is 166, comment is 0, blank is 0. -constraint_backup\camera_light_src_timing_controller_fpga_2024_01_06_19_22_21.fdc, code is 8, comment is 0, blank is 0. -constraint_backup\camera_light_src_timing_controller_fpga_2024_01_07_14_16_20.fdc, code is 14, comment is 0, blank is 0. -constraint_backup\camera_light_src_timing_controller_fpga_2024_01_08_15_30_41.fdc, code is 32, comment is 0, blank is 0. -constraint_backup\camera_light_src_timing_controller_fpga_2024_01_08_15_39_15.fdc, code is 144, comment is 0, blank is 3. -constraint_backup\camera_light_src_timing_controller_fpga_2024_01_08_15_44_05.fdc, code is 162, comment is 0, blank is 5. -constraint_backup\camera_light_src_timing_controller_fpga_2024_01_08_16_40_22.fdc, code is 541, comment is 0, blank is 10. -constraint_backup\camera_light_src_timing_controller_fpga_2024_01_08_16_54_45.fdc, code is 545, comment is 0, blank is 10. -data.wf, it is a binary file. -device_map\bak\dmr.db, code is 5671, comment is 0, blank is 0. -device_map\bak\camera_light_src_timing_controller_fpga.dmr, code is 169, comment is 0, blank is 21. -device_map\bak\camera_light_src_timing_controller_fpga_dmr.prt, code is 240, comment is 0, blank is 0. -device_map\bak\Top.dmr, code is 394, comment is 0, blank is 21. -device_map\bak\Top_dmr.prt, code is 240, comment is 0, blank is 0. -device_map\formal.pvf, code is 853, comment is 0, blank is 0. -device_map\camera_light_src_timing_controller_fpga.pcf, code is 69, comment is 0, blank is 1. -device_map\logbackup\run_2024-01-09-15-13-07.log, code is 67, comment is 0, blank is 2. -device_map\logbackup\run_2024-01-10-21-59-05.log, code is 67, comment is 0, blank is 2. -device_map\logbackup\run_2024-01-10-22-06-06.log, code is 73, comment is 0, blank is 2. -device_map\logbackup\run_2024-01-11-09-22-30.log, code is 73, comment is 0, blank is 2. -device_map\logbackup\run_2024-01-11-09-40-15.log, code is 73, comment is 0, blank is 2. -device_map\logbackup\run_2024-01-11-09-43-56.log, code is 73, comment is 0, blank is 2. -device_map\logbackup\run_2024-01-11-11-13-42.log, code is 73, comment is 0, blank is 2. -device_map\logbackup\run_2024-01-11-11-47-31.log, code is 73, comment is 0, blank is 2. -device_map\logbackup\run_2024-01-11-16-09-16.log, code is 73, comment is 0, blank is 2. -device_map\logbackup\run_2024-01-11-16-32-24.log, code is 73, comment is 0, blank is 2. -device_map\run.log, code is 73, comment is 0, blank is 2. -generate_bitstream\bak\bgr.db, code is 280, comment is 0, blank is 0. -generate_bitstream\bak\camera_light_src_timing_controller_fpga.bgr, code is 19, comment is 0, blank is 4. -generate_bitstream\bak\camera_light_src_timing_controller_fpga.sbit, it is a binary file. -generate_bitstream\bak\camera_light_src_timing_controller_fpga.smsk, it is a binary file. -generate_bitstream\bak\Top.bgr, code is 19, comment is 0, blank is 4. -generate_bitstream\bak\Top.sbit, it is a binary file. -generate_bitstream\bak\Top.smsk, it is a binary file. -generate_bitstream\logbackup\run_2024-01-09-15-15-53.log, code is 24, comment is 0, blank is 0. -generate_bitstream\logbackup\run_2024-01-10-22-00-59.log, code is 24, comment is 0, blank is 0. -generate_bitstream\logbackup\run_2024-01-10-22-07-57.log, code is 24, comment is 0, blank is 0. -generate_bitstream\logbackup\run_2024-01-11-09-23-14.log, code is 24, comment is 0, blank is 0. -generate_bitstream\logbackup\run_2024-01-11-09-41-40.log, code is 24, comment is 0, blank is 0. -generate_bitstream\logbackup\run_2024-01-11-09-45-33.log, code is 24, comment is 0, blank is 0. -generate_bitstream\logbackup\run_2024-01-11-11-15-51.log, code is 24, comment is 0, blank is 0. -generate_bitstream\logbackup\run_2024-01-11-11-49-40.log, code is 24, comment is 0, blank is 0. -generate_bitstream\logbackup\run_2024-01-11-16-10-09.log, code is 24, comment is 0, blank is 0. -generate_bitstream\logbackup\run_2024-01-11-16-33-19.log, code is 24, comment is 0, blank is 0. -generate_bitstream\run.log, code is 24, comment is 0, blank is 0. -generate_bitstream\Top.sfc, it is a binary file. -generate_netlist\run.log, code is 20, comment is 0, blank is 0. -impl.tcl, code is 1795, comment is 0, blank is 1. -ipcore\genlock_sig_gen_pll\genlock_sig_gen_pll.idf, code is 641, comment is 0, blank is 0. -ipcore\inclkpll\.last_generated, code is 2, comment is 0, blank is 0. -ipcore\inclkpll\generate.log, code is 17, comment is 0, blank is 0. -ipcore\inclkpll\inclkpll.idf, code is 651, comment is 0, blank is 0. -ipcore\inclkpll\inclkpll.v, code is 43, comment is 15, blank is 8. -ipcore\inclkpll\inclkpll_tb.v, code is 134, comment is 18, blank is 24. -ipcore\inclkpll\inclkpll_tmpl.v, code is 5, comment is 9, blank is 2. -ipcore\inclkpll\inclkpll_tmpl.vhdl, code is 19, comment is 0, blank is 4. -ipcore\ram\ram.idf, code is 108, comment is 0, blank is 0. -ipcore\smult\smult.idf, code is 122, comment is 0, blank is 0. -ipcore\SPLL\.last_generated, code is 2, comment is 0, blank is 0. -ipcore\SPLL\generate.log, code is 17, comment is 0, blank is 0. -ipcore\SPLL\SPLL.idf, code is 663, comment is 0, blank is 0. -ipcore\SPLL\SPLL.v, code is 45, comment is 15, blank is 8. -ipcore\SPLL\SPLL_tb.v, code is 136, comment is 18, blank is 24. -ipcore\SPLL\SPLL_tmpl.v, code is 7, comment is 11, blank is 2. -ipcore\SPLL\SPLL_tmpl.vhdl, code is 23, comment is 0, blank is 4. -ipcore\ttl_pll\ttl_pll.idf, code is 641, comment is 0, blank is 0. -camera_light_src_timing_controller_fpga.fdc, code is 563, comment is 0, blank is 12. -camera_light_src_timing_controller_fpga.pds, code is 295, comment is 0, blank is 0. -log\cfg.log, code is 16, comment is 0, blank is 1. -log\configuration.log, code is 17102, comment is 0, blank is 0. -log\dbg.log, code is 7, comment is 0, blank is 0. -log\DbgTclCmd.log, code is 13, comment is 0, blank is 13. -log\debugger.log, code is 2381, comment is 0, blank is 26. -log\ins.log, code is 23, comment is 0, blank is 0. -log\js.log, code is 7, comment is 0, blank is 0. -log\jtagserver.log, code is 13300, comment is 0, blank is 0. -logbackup\run_2024-01-08-20-56-59.log, code is 290, comment is 0, blank is 3. -logbackup\run_2024-01-08-21-33-22.log, code is 18287, comment is 0, blank is 2109. -logbackup\run_2024-01-08-21-38-14.log, code is 221, comment is 0, blank is 3. -logbackup\run_2024-01-08-21-46-47.log, code is 3455, comment is 0, blank is 387. -logbackup\run_2024-01-08-22-10-08.log, code is 329, comment is 0, blank is 3. -logbackup\run_2024-01-08-22-25-01.log, code is 15202, comment is 0, blank is 1705. -logbackup\run_2024-01-09-11-00-15.log, code is 517, comment is 0, blank is 5. -logbackup\run_2024-01-09-22-55-17.log, code is 7608, comment is 0, blank is 220. -logbackup\run_2024-01-10-11-09-19.log, code is 18, comment is 0, blank is 0. -logbackup\run_2024-01-11-12-54-38.log, code is 47493, comment is 0, blank is 3307. -msg_level.txt, code is 7, comment is 0, blank is 0. -pango_sim_libraries\adc\_info, code is 299, comment is 0, blank is 0. -pango_sim_libraries\adc\_lib.qdb, it is a binary file. -pango_sim_libraries\adc\_lib1_1.qdb, it is a binary file. -pango_sim_libraries\adc\_lib1_1.qpg, it is a binary file. -pango_sim_libraries\adc\_lib1_1.qtl, it is a binary file. -pango_sim_libraries\adc\_vmake, code is 4, comment is 0, blank is 0. -pango_sim_libraries\adc_e2\_info, code is 587, comment is 0, blank is 0. -pango_sim_libraries\adc_e2\_lib.qdb, it is a binary file. -pango_sim_libraries\adc_e2\_lib1_2.qdb, it is a binary file. -pango_sim_libraries\adc_e2\_lib1_2.qpg, it is a binary file. -pango_sim_libraries\adc_e2\_lib1_2.qtl, it is a binary file. -pango_sim_libraries\adc_e2\_vmake, code is 4, comment is 0, blank is 0. -pango_sim_libraries\ddc_e2\_info, code is 59, comment is 0, blank is 0. -pango_sim_libraries\ddc_e2\_lib.qdb, it is a binary file. -pango_sim_libraries\ddc_e2\_lib1_0.qdb, it is a binary file. -pango_sim_libraries\ddc_e2\_lib1_0.qpg, it is a binary file. -pango_sim_libraries\ddc_e2\_lib1_0.qtl, it is a binary file. -pango_sim_libraries\ddc_e2\_vmake, code is 4, comment is 0, blank is 0. -pango_sim_libraries\ddrc\_info, code is 3656, comment is 1, blank is 0. -pango_sim_libraries\ddrc\_lib.qdb, it is a binary file. -pango_sim_libraries\ddrc\_lib1_6.qdb, it is a binary file. -pango_sim_libraries\ddrc\_lib1_6.qpg, it is a binary file. -pango_sim_libraries\ddrc\_lib1_6.qtl, it is a binary file. -pango_sim_libraries\ddrc\_vmake, code is 4, comment is 0, blank is 0. -pango_sim_libraries\ddrphy\_info, code is 635, comment is 0, blank is 0. -pango_sim_libraries\ddrphy\_lib.qdb, it is a binary file. -pango_sim_libraries\ddrphy\_lib1_2.qdb, it is a binary file. -pango_sim_libraries\ddrphy\_lib1_2.qpg, it is a binary file. -pango_sim_libraries\ddrphy\_lib1_2.qtl, it is a binary file. -pango_sim_libraries\ddrphy\_vmake, code is 4, comment is 0, blank is 0. -pango_sim_libraries\dll_e2\_info, code is 179, comment is 0, blank is 0. -pango_sim_libraries\dll_e2\_lib.qdb, it is a binary file. -pango_sim_libraries\dll_e2\_lib1_0.qdb, it is a binary file. -pango_sim_libraries\dll_e2\_lib1_0.qpg, it is a binary file. -pango_sim_libraries\dll_e2\_lib1_0.qtl, it is a binary file. -pango_sim_libraries\dll_e2\_vmake, code is 4, comment is 0, blank is 0. -pango_sim_libraries\hsst\_info, code is 6227, comment is 1, blank is 0. -pango_sim_libraries\hsst\_lib.qdb, it is a binary file. -pango_sim_libraries\hsst\_lib1_6.qdb, it is a binary file. -pango_sim_libraries\hsst\_lib1_6.qpg, it is a binary file. -pango_sim_libraries\hsst\_lib1_6.qtl, it is a binary file. -pango_sim_libraries\hsst\_vmake, code is 4, comment is 0, blank is 0. -pango_sim_libraries\hsst_e2\_info, code is 9299, comment is 2, blank is 0. -pango_sim_libraries\hsst_e2\_lib.qdb, it is a binary file. -pango_sim_libraries\hsst_e2\_lib1_6.qdb, it is a binary file. -pango_sim_libraries\hsst_e2\_lib1_6.qpg, it is a binary file. -pango_sim_libraries\hsst_e2\_lib1_6.qtl, it is a binary file. -pango_sim_libraries\hsst_e2\_vmake, code is 4, comment is 0, blank is 0. -pango_sim_libraries\hssthp_bufds\_info, code is 35, comment is 0, blank is 0. -pango_sim_libraries\hssthp_bufds\_lib.qdb, it is a binary file. -pango_sim_libraries\hssthp_bufds\_lib1_0.qdb, it is a binary file. -pango_sim_libraries\hssthp_bufds\_lib1_0.qpg, code is 0, comment is 0, blank is 0. -pango_sim_libraries\hssthp_bufds\_lib1_0.qtl, it is a binary file. -pango_sim_libraries\hssthp_bufds\_vmake, code is 4, comment is 0, blank is 0. -pango_sim_libraries\hssthp_hpll\_info, code is 4187, comment is 4, blank is 0. -pango_sim_libraries\hssthp_hpll\_lib.qdb, it is a binary file. -pango_sim_libraries\hssthp_hpll\_lib1_6.qdb, it is a binary file. -pango_sim_libraries\hssthp_hpll\_lib1_6.qpg, it is a binary file. -pango_sim_libraries\hssthp_hpll\_lib1_6.qtl, it is a binary file. -pango_sim_libraries\hssthp_hpll\_vmake, code is 4, comment is 0, blank is 0. -pango_sim_libraries\hssthp_lane\_info, code is 12035, comment is 7, blank is 0. -pango_sim_libraries\hssthp_lane\_lib.qdb, it is a binary file. -pango_sim_libraries\hssthp_lane\_lib1_6.qdb, it is a binary file. -pango_sim_libraries\hssthp_lane\_lib1_6.qpg, it is a binary file. -pango_sim_libraries\hssthp_lane\_lib1_6.qtl, it is a binary file. -pango_sim_libraries\hssthp_lane\_vmake, code is 4, comment is 0, blank is 0. -pango_sim_libraries\hsstlp_lane\_info, code is 8171, comment is 1, blank is 0. -pango_sim_libraries\hsstlp_lane\_lib.qdb, it is a binary file. -pango_sim_libraries\hsstlp_lane\_lib1_6.qdb, it is a binary file. -pango_sim_libraries\hsstlp_lane\_lib1_6.qpg, it is a binary file. -pango_sim_libraries\hsstlp_lane\_lib1_6.qtl, it is a binary file. -pango_sim_libraries\hsstlp_lane\_vmake, code is 4, comment is 0, blank is 0. -pango_sim_libraries\hsstlp_pll\_info, code is 2963, comment is 1, blank is 0. -pango_sim_libraries\hsstlp_pll\_lib.qdb, it is a binary file. -pango_sim_libraries\hsstlp_pll\_lib1_6.qdb, it is a binary file. -pango_sim_libraries\hsstlp_pll\_lib1_6.qpg, it is a binary file. -pango_sim_libraries\hsstlp_pll\_lib1_6.qtl, it is a binary file. -pango_sim_libraries\hsstlp_pll\_vmake, code is 4, comment is 0, blank is 0. -pango_sim_libraries\iolhp_fifo\_info, code is 3491, comment is 0, blank is 0. -pango_sim_libraries\iolhp_fifo\_lib.qdb, it is a binary file. -pango_sim_libraries\iolhp_fifo\_lib1_6.qdb, it is a binary file. -pango_sim_libraries\iolhp_fifo\_lib1_6.qpg, code is 0, comment is 0, blank is 0. -pango_sim_libraries\iolhp_fifo\_lib1_6.qtl, it is a binary file. -pango_sim_libraries\iolhp_fifo\_vmake, code is 4, comment is 0, blank is 0. -pango_sim_libraries\iolhr_dft\_info, code is 2843, comment is 0, blank is 0. -pango_sim_libraries\iolhr_dft\_lib.qdb, it is a binary file. -pango_sim_libraries\iolhr_dft\_lib1_6.qdb, it is a binary file. -pango_sim_libraries\iolhr_dft\_lib1_6.qpg, it is a binary file. -pango_sim_libraries\iolhr_dft\_lib1_6.qtl, it is a binary file. -pango_sim_libraries\iolhr_dft\_vmake, code is 4, comment is 0, blank is 0. -pango_sim_libraries\ipal_e1\_info, code is 155, comment is 0, blank is 0. -pango_sim_libraries\ipal_e1\_lib.qdb, it is a binary file. -pango_sim_libraries\ipal_e1\_lib1_0.qdb, it is a binary file. -pango_sim_libraries\ipal_e1\_lib1_0.qpg, it is a binary file. -pango_sim_libraries\ipal_e1\_lib1_0.qtl, it is a binary file. -pango_sim_libraries\ipal_e1\_vmake, code is 4, comment is 0, blank is 0. -pango_sim_libraries\ipal_e2\_info, code is 179, comment is 0, blank is 0. -pango_sim_libraries\ipal_e2\_lib.qdb, it is a binary file. -pango_sim_libraries\ipal_e2\_lib1_0.qdb, it is a binary file. -pango_sim_libraries\ipal_e2\_lib1_0.qpg, it is a binary file. -pango_sim_libraries\ipal_e2\_lib1_0.qtl, it is a binary file. -pango_sim_libraries\ipal_e2\_vmake, code is 4, comment is 0, blank is 0. -pango_sim_libraries\iserdes_e1\_info, code is 59, comment is 0, blank is 0. -pango_sim_libraries\iserdes_e1\_lib.qdb, it is a binary file. -pango_sim_libraries\iserdes_e1\_lib1_0.qdb, it is a binary file. -pango_sim_libraries\iserdes_e1\_lib1_0.qpg, code is 0, comment is 0, blank is 0. -pango_sim_libraries\iserdes_e1\_lib1_0.qtl, it is a binary file. -pango_sim_libraries\iserdes_e1\_vmake, code is 4, comment is 0, blank is 0. -pango_sim_libraries\iserdes_e2\_info, code is 2627, comment is 1, blank is 0. -pango_sim_libraries\iserdes_e2\_lib.qdb, it is a binary file. -pango_sim_libraries\iserdes_e2\_lib1_6.qdb, it is a binary file. -pango_sim_libraries\iserdes_e2\_lib1_6.qpg, it is a binary file. -pango_sim_libraries\iserdes_e2\_lib1_6.qtl, it is a binary file. -pango_sim_libraries\iserdes_e2\_vmake, code is 4, comment is 0, blank is 0. -pango_sim_libraries\iserdes_fifo\_info, code is 203, comment is 0, blank is 0. -pango_sim_libraries\iserdes_fifo\_lib.qdb, it is a binary file. -pango_sim_libraries\iserdes_fifo\_lib1_0.qdb, it is a binary file. -pango_sim_libraries\iserdes_fifo\_lib1_0.qpg, code is 0, comment is 0, blank is 0. -pango_sim_libraries\iserdes_fifo\_lib1_0.qtl, it is a binary file. -pango_sim_libraries\iserdes_fifo\_vmake, code is 4, comment is 0, blank is 0. -pango_sim_libraries\modelsim.ini, code is 72, comment is 1662, blank is 353. -pango_sim_libraries\msim_pango.tcl, code is 58, comment is 65, blank is 2. -pango_sim_libraries\oserdes_e1\_info, code is 59, comment is 0, blank is 0. -pango_sim_libraries\oserdes_e1\_lib.qdb, it is a binary file. -pango_sim_libraries\oserdes_e1\_lib1_0.qdb, it is a binary file. -pango_sim_libraries\oserdes_e1\_lib1_0.qpg, code is 0, comment is 0, blank is 0. -pango_sim_libraries\oserdes_e1\_lib1_0.qtl, it is a binary file. -pango_sim_libraries\oserdes_e1\_vmake, code is 4, comment is 0, blank is 0. -pango_sim_libraries\oserdes_e2\_info, code is 2843, comment is 1, blank is 0. -pango_sim_libraries\oserdes_e2\_lib.qdb, it is a binary file. -pango_sim_libraries\oserdes_e2\_lib1_6.qdb, it is a binary file. -pango_sim_libraries\oserdes_e2\_lib1_6.qpg, it is a binary file. -pango_sim_libraries\oserdes_e2\_lib1_6.qtl, it is a binary file. -pango_sim_libraries\oserdes_e2\_vmake, code is 4, comment is 0, blank is 0. -pango_sim_libraries\oserdes_fifo\_info, code is 203, comment is 0, blank is 0. -pango_sim_libraries\oserdes_fifo\_lib.qdb, it is a binary file. -pango_sim_libraries\oserdes_fifo\_lib1_0.qdb, it is a binary file. -pango_sim_libraries\oserdes_fifo\_lib1_0.qpg, code is 0, comment is 0, blank is 0. -pango_sim_libraries\oserdes_fifo\_lib1_0.qtl, it is a binary file. -pango_sim_libraries\oserdes_fifo\_vmake, code is 4, comment is 0, blank is 0. -pango_sim_libraries\pciegen2\_info, code is 5699, comment is 2, blank is 0. -pango_sim_libraries\pciegen2\_lib.qdb, it is a binary file. -pango_sim_libraries\pciegen2\_lib1_6.qdb, it is a binary file. -pango_sim_libraries\pciegen2\_lib1_6.qpg, it is a binary file. -pango_sim_libraries\pciegen2\_lib1_6.qtl, it is a binary file. -pango_sim_libraries\pciegen2\_vmake, code is 4, comment is 0, blank is 0. -pango_sim_libraries\pciegen3\_info, code is 7434, comment is 2, blank is 0. -pango_sim_libraries\pciegen3\_lib.qdb, it is a binary file. -pango_sim_libraries\pciegen3\_lib1_6.qdb, it is a binary file. -pango_sim_libraries\pciegen3\_lib1_6.qpg, it is a binary file. -pango_sim_libraries\pciegen3\_lib1_6.qtl, it is a binary file. -pango_sim_libraries\pciegen3\_vmake, code is 4, comment is 0, blank is 0. -pango_sim_libraries\run_sim.bat, code is 1, comment is 0, blank is 0. -pango_sim_libraries\transcript, code is 1205, comment is 0, blank is 0. -pango_sim_libraries\usim\_info, code is 16148, comment is 2, blank is 0. -pango_sim_libraries\usim\_lib.qdb, it is a binary file. -pango_sim_libraries\usim\_lib1_13.qdb, it is a binary file. -pango_sim_libraries\usim\_lib1_13.qpg, it is a binary file. -pango_sim_libraries\usim\_lib1_13.qtl, it is a binary file. -pango_sim_libraries\usim\_vmake, code is 4, comment is 0, blank is 0. -pango_sim_libraries\vsim\_info, code is 14424, comment is 3, blank is 0. -pango_sim_libraries\vsim\_lib.qdb, it is a binary file. -pango_sim_libraries\vsim\_lib1_13.qdb, it is a binary file. -pango_sim_libraries\vsim\_lib1_13.qpg, it is a binary file. -pango_sim_libraries\vsim\_lib1_13.qtl, it is a binary file. -pango_sim_libraries\vsim\_vmake, code is 4, comment is 0, blank is 0. -pds.log, code is 33751, comment is 0, blank is 2351. -pin.md, code is 2, comment is 0, blank is 4. -place_route\bak\clock_utilization.txt, code is 43, comment is 0, blank is 6. -place_route\bak\camera_light_src_timing_controller_fpga.prr, code is 115, comment is 0, blank is 13. -place_route\bak\camera_light_src_timing_controller_fpga_plc.adf, it is a binary file. -place_route\bak\camera_light_src_timing_controller_fpga_pnr.netlist, code is 1382, comment is 0, blank is 104. -place_route\bak\camera_light_src_timing_controller_fpga_prr.prt, code is 240, comment is 0, blank is 0. -place_route\bak\prr.db, code is 5824, comment is 0, blank is 0. -place_route\bak\Top.prr, code is 248, comment is 0, blank is 14. -place_route\bak\Top_plc.adf, it is a binary file. -place_route\bak\Top_pnr.netlist, code is 92859, comment is 0, blank is 7483. -place_route\bak\Top_prr.prt, code is 240, comment is 0, blank is 0. -place_route\des.log, code is 33, comment is 0, blank is 0. -place_route\logbackup\run_2024-01-09-15-15-18.log, code is 531, comment is 0, blank is 13. -place_route\logbackup\run_2024-01-10-22-00-40.log, code is 522, comment is 0, blank is 13. -place_route\logbackup\run_2024-01-10-22-07-41.log, code is 511, comment is 0, blank is 13. -place_route\logbackup\run_2024-01-11-09-23-00.log, code is 587, comment is 0, blank is 13. -place_route\logbackup\run_2024-01-11-09-41-26.log, code is 556, comment is 0, blank is 13. -place_route\logbackup\run_2024-01-11-09-45-12.log, code is 501, comment is 0, blank is 13. -place_route\logbackup\run_2024-01-11-11-15-25.log, code is 530, comment is 0, blank is 13. -place_route\logbackup\run_2024-01-11-11-49-15.log, code is 530, comment is 0, blank is 13. -place_route\logbackup\run_2024-01-11-16-09-52.log, code is 514, comment is 0, blank is 13. -place_route\logbackup\run_2024-01-11-16-33-01.log, code is 536, comment is 0, blank is 13. -place_route\run.log, code is 513, comment is 0, blank is 13. -README.md, code is 43, comment is 3, blank is 23. -report_power\run.log, code is 22, comment is 0, blank is 0. -report_timing\bak\camera_light_src_timing_controller_fpga.rtr, code is 1238, comment is 0, blank is 202. -report_timing\bak\rtr.db, code is 31055, comment is 0, blank is 0. -report_timing\bak\Top.rtr, code is 1516, comment is 0, blank is 202. -report_timing\logbackup\run_2024-01-09-15-15-24.log, code is 2102, comment is 0, blank is 316. -report_timing\logbackup\run_2024-01-10-22-00-46.log, code is 2578, comment is 0, blank is 316. -report_timing\logbackup\run_2024-01-10-22-07-47.log, code is 1564, comment is 0, blank is 208. -report_timing\logbackup\run_2024-01-11-09-23-05.log, code is 1492, comment is 0, blank is 208. -report_timing\logbackup\run_2024-01-11-09-41-31.log, code is 1476, comment is 0, blank is 208. -report_timing\logbackup\run_2024-01-11-09-45-18.log, code is 1520, comment is 0, blank is 208. -report_timing\logbackup\run_2024-01-11-11-15-32.log, code is 1480, comment is 0, blank is 208. -report_timing\logbackup\run_2024-01-11-11-49-21.log, code is 1480, comment is 0, blank is 208. -report_timing\logbackup\run_2024-01-11-16-09-57.log, code is 1536, comment is 0, blank is 208. -report_timing\logbackup\run_2024-01-11-16-33-06.log, code is 1634, comment is 0, blank is 208. -report_timing\run.log, code is 1610, comment is 0, blank is 208. -run.log, code is 30854, comment is 0, blank is 2265. -sim\behav\modelsim.ini, code is 54, comment is 1662, blank is 353. -sim\behav\run_behav.bat, code is 10, comment is 0, blank is 0. -sim\behav\run_behav_compile.tcl, code is 51, comment is 0, blank is 2. -sim\behav\run_behav_simulate.log, code is 626, comment is 4574, blank is 0. -sim\behav\run_behav_simulate.tcl, code is 11, comment is 0, blank is 3. -sim\behav\vsim.wlf, it is a binary file. -sim\behav\work\_info, code is 745, comment is 0, blank is 0. -sim\behav\work\_lib.qdb, it is a binary file. -sim\behav\work\_lib1_12.qdb, it is a binary file. -sim\behav\work\_lib1_12.qpg, it is a binary file. -sim\behav\work\_lib1_12.qtl, it is a binary file. -sim\behav\work\_vmake, code is 4, comment is 0, blank is 0. -source\src\camera_sync_signal_output.v, code is 60, comment is 32, blank is 16. -source\src\debuger.v, code is 22, comment is 4, blank is 3. -source\src\input\src_genlock.v, code is 0, comment is 0, blank is 0. -source\src\input\src_timecode.v, code is 0, comment is 176, blank is 32. -source\src\input\src_ttl_parser.v, code is 0, comment is 116, blank is 15. -source\src\output\ttl_output.v, code is 89, comment is 57, blank is 23. -source\src\rd_data_router.v, code is 41, comment is 6, blank is 4. -source\src\spi_reg_reader.v, code is 160, comment is 65, blank is 32. -source\src\timecode\timecode_basesig_generator.v, code is 132, comment is 8, blank is 21. -source\src\timecode\timecode_generator.v, code is 87, comment is 6, blank is 25. -source\src\timecode\timecode_nextcode.v, code is 124, comment is 221, blank is 22. -source\src\timecode\timecode_serialization.v, code is 89, comment is 12, blank is 16. -source\src\timecode_output.v, code is 73, comment is 18, blank is 22. -source\src\top.v, code is 69, comment is 32, blank is 25. -source\src\xsync_internal_generator.v, code is 178, comment is 89, blank is 40. -source\src\xsync_internal_sub\internal_timecode_generator.v, code is 99, comment is 33, blank is 22. -source\src\zutils\baud_rate_gen.v, code is 17, comment is 4, blank is 4. -source\src\zutils\ztutils_timecode_next_code.v, code is 54, comment is 3, blank is 5. -source\src\zutils\zutils_clk_parser.v, code is 82, comment is 85, blank is 19. -source\src\zutils\zutils_debug_led.v, code is 12, comment is 2, blank is 2. -source\src\zutils\zutils_edge_detecter.v, code is 38, comment is 8, blank is 5. -source\src\zutils\zutils_genlock_clk_generator.v, code is 98, comment is 2, blank is 14. -source\src\zutils\zutils_multiplexer_16t1.v, code is 61, comment is 1, blank is 4. -source\src\zutils\zutils_multiplexer_2t1.v, code is 17, comment is 0, blank is 0. -source\src\zutils\zutils_multiplexer_32t1.v, code is 109, comment is 0, blank is 5. -source\src\zutils\zutils_multiplexer_32t1_v2.v, code is 140, comment is 0, blank is 6. -source\src\zutils\zutils_multiplexer_4t1.v, code is 28, comment is 0, blank is 2. -source\src\zutils\zutils_muti_debug_signal_gen.v, code is 30, comment is 0, blank is 6. -source\src\zutils\zutils_pluse_generator.v, code is 62, comment is 3, blank is 11. -source\src\zutils\zutils_pwm_generator.v, code is 31, comment is 1, blank is 5. -source\src\zutils\zutils_pwm_generator_advanced.v, code is 37, comment is 1, blank is 7. -source\src\zutils\zutils_register.v, code is 84, comment is 23, blank is 8. -source\src\zutils\zutils_register.v.bak, code is 85, comment is 5, blank is 7. -source\src\zutils\zutils_register_advanced.v, code is 73, comment is 16, blank is 14. -source\src\zutils\zutils_reset_sig_gen.v, code is 21, comment is 2, blank is 1. -source\src\zutils\zutils_signal_filter.v, code is 27, comment is 3, blank is 2. -source\src\zutils\zutils_smpte_timecode_clk_generator.v, code is 68, comment is 2, blank is 8. -source\src\zutils\zutils_timecode_convert.v, code is 71, comment is 20, blank is 14. -source\src\zutils\zutils_timecode_serial_data_gen.v, code is 96, comment is 22, blank is 31. -source\test\test_baud_rate_gen.v, code is 22, comment is 3, blank is 6. -source\test\test_spi_reg_reader.v, code is 49, comment is 18, blank is 17. -source\test\test_timecode_generator.v, code is 54, comment is 17, blank is 20. -source\test\test_top.v, code is 85, comment is 4, blank is 24. -source\test\test_transmitter.v, code is 37, comment is 3, blank is 11. -source\test\test_uart_reg_reader.v, code is 22, comment is 2, blank is 4. -synthesize\async_receiver.ccr, code is 39, comment is 0, blank is 41. -synthesize\async_receiver.snr, code is 1, comment is 0, blank is 1. -synthesize\bak\camera_light_src_timing_controller_fpga.snr, code is 892, comment is 0, blank is 126. -synthesize\bak\camera_light_src_timing_controller_fpga_syn.vm, code is 1012, comment is 78, blank is 76. -synthesize\bak\snr.db, code is 431, comment is 0, blank is 0. -synthesize\bak\Top.snr, code is 1224, comment is 0, blank is 127. -synthesize\bak\Top_syn.vm, code is 50611, comment is 5110, blank is 4538. -synthesize\formal.pvf, code is 252, comment is 0, blank is 235. -synthesize\camera_light_src_timing_controller_fpga.ccr, code is 15, comment is 0, blank is 31. -synthesize\logbackup\run_2024-01-11-15-21-16.log, code is 1393, comment is 0, blank is 141. -synthesize\logbackup\run_2024-01-11-15-23-20.log, code is 1393, comment is 0, blank is 141. -synthesize\logbackup\run_2024-01-11-15-23-41.log, code is 1393, comment is 0, blank is 141. -synthesize\logbackup\run_2024-01-11-15-28-07.log, code is 1429, comment is 0, blank is 141. -synthesize\logbackup\run_2024-01-11-16-09-11.log, code is 1401, comment is 0, blank is 140. -synthesize\logbackup\run_2024-01-11-16-32-19.log, code is 1422, comment is 0, blank is 140. -synthesize\logbackup\run_2024-01-11-17-11-00.log, code is 1407, comment is 0, blank is 140. -synthesize\logbackup\run_2024-01-11-18-36-07.log, code is 149, comment is 0, blank is 4. -synthesize\logbackup\run_2024-01-11-18-43-01.log, code is 1395, comment is 0, blank is 140. -synthesize\logbackup\run_2024-01-11-20-39-12.log, code is 174, comment is 0, blank is 33. -synthesize\run.log, code is 152, comment is 0, blank is 4. -synthesize\src_ttl_parser.ccr, code is 155, comment is 0, blank is 69. -synthesize\src_ttl_parser.snr, code is 1, comment is 0, blank is 1. -synthesize\Top.ccr, code is 18, comment is 0, blank is 31. -synthesize\Top.snr, code is 1, comment is 0, blank is 1. -=============================================================================== diff --git a/pin.csv b/pin.csv index bbb031c..e7a329d 100644 --- a/pin.csv +++ b/pin.csv @@ -1,4 +1,4 @@ -camera_light_src_timing_controller_fpga.fdc,, +app.fdc,, B5,ex_clk,INPUT P17,spi_cs_pin ,INPUT L12,spi_clk_pin,INPUT @@ -7,11 +7,6 @@ R18,spi_rx_pin,INPUT L17,uart_tx,OUTPUT L18,uart_rx,INPUT T11,core_board_debug_led,OUTPUT -M16,tmp_contrl_pin[0],OUTPUT -L16,tmp_contrl_pin[1],OUTPUT -J18,tmp_contrl_pin[2],OUTPUT -J17,tmp_contrl_pin[3],OUTPUT -E15,tmp_contrl_pin[4],OUTPUT M18,stm32_output_bus[0],OUTPUT K18,stm32_output_bus[1],OUTPUT K17,stm32_output_bus[2],OUTPUT @@ -44,31 +39,8 @@ A16,debug_bus[12],OUTPUT B16,debug_bus[13],OUTPUT A15,debug_bus[14],OUTPUT B15,debug_bus[15],OUTPUT -N18,optocoupler_out1,OUTPUT -L15,optocoupler_out2,OUTPUT -L14,optocoupler_out3,OUTPUT -M14,optocoupler_out4,OUTPUT -C15,optocoupler_in1,INPUT -D15,optocoupler_in2,INPUT -D13,optocoupler_in3,INPUT -C13,optocoupler_in4,INPUT -M13,diff_out1,OUTPUT -U18,diff_out2,OUTPUT -U17,diff_out3,OUTPUT -T18,diff_out4,OUTPUT -B18,diff_in1,INPUT -B17,diff_in2,INPUT -A17,diff_in3,INPUT -E16,diff_in4,INPUT -T17,lt1_intensity_ctrl,OUTPUT -V16,lt1_en,OUTPUT -A14,lt1_error_sig_in,INPUT -V18,lt2_intensity_ctrl,OUTPUT -T16,lt2_en,OUTPUT -B14,lt2_error_sig_in,INPUT -V17,lt3_intensity_ctrl,OUTPUT -R16,lt3_en,OUTPUT -A12,lt3_error_sig_in,INPUT -U16,lt4_intensity_ctrl,OUTPUT -R15,lt4_en,OUTPUT -B12,lt4_error_sig_in,INPUT +N18,out1,OUTPUT +L15,extOutputEn1,OUTPUT +L14,extOutputEn2,OUTPUT +M16,triSig,INPUT + diff --git a/release/V10/Top.sbit b/release/V10/Top.sbit deleted file mode 100644 index 58297c8..0000000 Binary files a/release/V10/Top.sbit and /dev/null differ diff --git a/release/V10/Top.sfc b/release/V10/Top.sfc deleted file mode 100644 index 91d6e59..0000000 Binary files a/release/V10/Top.sfc and /dev/null differ diff --git a/release/V6/clst_v6.sbit b/release/V6/clst_v6.sbit deleted file mode 100644 index 7130e79..0000000 Binary files a/release/V6/clst_v6.sbit and /dev/null differ diff --git a/release/V6/clst_v6.sfc b/release/V6/clst_v6.sfc deleted file mode 100644 index d4120c0..0000000 Binary files a/release/V6/clst_v6.sfc and /dev/null differ diff --git a/release/V7/Topv7.sbit b/release/V7/Topv7.sbit deleted file mode 100644 index 4c1a344..0000000 Binary files a/release/V7/Topv7.sbit and /dev/null differ diff --git a/release/V7/Topv7.sfc b/release/V7/Topv7.sfc deleted file mode 100644 index c7be026..0000000 Binary files a/release/V7/Topv7.sfc and /dev/null differ diff --git a/release/V9/Top.sbit b/release/V9/Top.sbit deleted file mode 100644 index 0e34dae..0000000 Binary files a/release/V9/Top.sbit and /dev/null differ diff --git a/release/V9/Top.sfc b/release/V9/Top.sfc deleted file mode 100644 index d8907cd..0000000 Binary files a/release/V9/Top.sfc and /dev/null differ diff --git a/release/test01/README.md b/release/test01/README.md deleted file mode 100644 index 6069701..0000000 --- a/release/test01/README.md +++ /dev/null @@ -1,55 +0,0 @@ - -``` -assign diff_out1 = diff_in1; - assign diff_out2 = diff_in2; - assign diff_out3 = diff_in3; - assign diff_out4 = diff_in4; - - - assign optocoupler_out1 = optocoupler_in1; - assign optocoupler_out2 = optocoupler_in2; - assign optocoupler_out3 = optocoupler_in3; - assign optocoupler_out4 = optocoupler_in4; - - - assign uart_tx = uart_rx; - assign stm32_output_bus[0] = stm32_input_bus[0]; - assign stm32_output_bus[1] = stm32_input_bus[1]; - assign stm32_output_bus[2] = stm32_input_bus[2]; - assign stm32_output_bus[3] = stm32_input_bus[3]; - assign stm32_output_bus[4] = stm32_input_bus[4]; - assign stm32_output_bus[5] = stm32_input_bus[5]; - assign stm32_output_bus[6] = stm32_input_bus[6]; - assign stm32_output_bus[7] = stm32_input_bus[7]; - - FPGA引出的测试引脚分别输出 - pwm100hz - pwm101hz - pwm102hz - pwm103hz - pwm104hz - pwm105hz - pwm106hz - pwm107hz - pwm108hz - pwm109hz - pwm110hz - pwm111hz - pwm112hz - pwm113hz - pwm114hz - pwm115hz - - 亮度控制: - .pwm100hz(lt1_en), - .pwm101hz(lt2_en), - .pwm102hz(lt3_en), - .pwm103hz(lt4_en), - .pwm104hz(lt1_intensity_ctrl), - .pwm105hz(lt2_intensity_ctrl), - .pwm106hz(lt3_intensity_ctrl), - .pwm107hz(lt4_intensity_ctrl) - - - -``` \ No newline at end of file diff --git a/release/test01/Top.sbit b/release/test01/Top.sbit deleted file mode 100644 index 57463ca..0000000 Binary files a/release/test01/Top.sbit and /dev/null differ diff --git a/release/v2.0/camera_light_src_timing_controller_fpga_v2.sbit b/release/v2.0/camera_light_src_timing_controller_fpga_v2.sbit deleted file mode 100644 index 07580fe..0000000 Binary files a/release/v2.0/camera_light_src_timing_controller_fpga_v2.sbit and /dev/null differ diff --git a/release/v2.0/camera_light_src_timing_controller_fpga_v2.sfc b/release/v2.0/camera_light_src_timing_controller_fpga_v2.sfc deleted file mode 100644 index 8393537..0000000 Binary files a/release/v2.0/camera_light_src_timing_controller_fpga_v2.sfc and /dev/null differ diff --git a/release/v4/Top.sbit b/release/v4/Top.sbit deleted file mode 100644 index d38ae18..0000000 Binary files a/release/v4/Top.sbit and /dev/null differ diff --git a/release/v4/Top.sfc b/release/v4/Top.sfc deleted file mode 100644 index 65b5ab4..0000000 Binary files a/release/v4/Top.sfc and /dev/null differ diff --git a/release/v5/Top.sbit b/release/v5/Top.sbit deleted file mode 100644 index 650f0c1..0000000 Binary files a/release/v5/Top.sbit and /dev/null differ diff --git a/release/v5/Top.sfc b/release/v5/Top.sfc deleted file mode 100644 index c8132ff..0000000 Binary files a/release/v5/Top.sfc and /dev/null differ diff --git a/source/src/app.v b/source/src/app.v new file mode 100644 index 0000000..28da6ee --- /dev/null +++ b/source/src/app.v @@ -0,0 +1,120 @@ +`include "config.v" +module app #( + parameter REG_START_ADD = `REGADDOFF__APP, + parameter SYS_CLOCK_FREQ = 100000000, + parameter FREQ_DETECT_BIAS = `FREQ_DETECT_BIAS_DEFAULT +) ( + + input clk, //! 时钟输入 + input rst_n, //! 复位输入 + + input [31:0] addr, //! 寄存器地址 + input [31:0] wr_data, //! 写入数据 + input wr_en, //! 写使能 + output wire [31:0] rd_data, //! 读出数据 + + input wire triSig, + output wire out1, + output wire extOutputEn1, + output wire extOutputEn2 +); + + reg [31:0] reg1_src_slect; //!信号源选择 + reg [31:0] reg2_fileter_coefficient; //!滤波系数 + reg [31:0] reg3_freq_detect_bias; //!脉冲频率探测误差 + reg [31:0] reg4_mode; //!0:拷贝模式 1:手动触发模式 2:外部触发模式 + reg [31:0] reg5_trigger_mode_trigger_edge; //!触发边沿 + reg [31:0] reg6_trigger_mode_pluse_num; //!脉冲个数 + reg [31:0] reg7_trigger_mode_pluse_width; //!脉冲宽度 + reg [31:0] reg8_trigger_mode_pluse_freq_num; //!脉冲频率 + wire [31:0] regD_in_signal_freq; //!输入信号频率探测 + wire [31:0] regE_out_signal_freq; //!输出信号频率探测 + reg [31:0] regF_manual_trigger_sig; //!手动触发信号 + + wire [31:0] reg_wr_index; + + zutils_register_advanced #( + .REG_START_ADD(REG_START_ADD) + ) _register ( + .clk (clk), + .rst_n (rst_n), + .addr (addr), + .wr_data(wr_data), + .wr_en (wr_en), + .rd_data(rd_data), + + .reg1(reg1_src_slect), + .reg2(reg2_fileter_coefficient), + .reg3(reg3_freq_detect_bias), + .reg4(reg4_mode), + .reg5(reg5_trigger_mode_trigger_edge), + .reg6(reg6_trigger_mode_pluse_num), + .reg7(reg7_trigger_mode_pluse_width), + .reg8(reg8_trigger_mode_pluse_freq_num), + .regD(regD_in_signal_freq), + .regE(regE_out_signal_freq), + .regF(regF_manual_trigger_sig), + + .reg_wr_sig(reg_wr_sig), + .reg_index (reg_wr_index) + ); + + always @(posedge clk or negedge rst_n) begin + if (!rst_n) begin + reg1_src_slect <= 0; + reg2_fileter_coefficient <= `FREQ_TTL_INPUT_FILTER; + reg3_freq_detect_bias <= `FREQ_DETECT_BIAS_DEFAULT; + reg4_mode <= 0; + reg5_trigger_mode_trigger_edge <= 0; + reg6_trigger_mode_pluse_num <= 0; + reg7_trigger_mode_pluse_width <= 0; + reg8_trigger_mode_pluse_freq_num <= 0; + regF_manual_trigger_sig <= 0; + end else begin + if (reg_wr_sig) begin + case (reg_wr_index) + 32'h1: reg1_src_slect <= wr_data; + 32'h2: reg2_fileter_coefficient <= wr_data; + 32'h3: reg3_freq_detect_bias <= wr_data; + 32'h4: reg4_mode <= wr_data; + 32'h5: reg5_trigger_mode_trigger_edge <= wr_data; + 32'h6: reg6_trigger_mode_pluse_num <= wr_data; + 32'h7: reg7_trigger_mode_pluse_width <= wr_data; + 32'h8: reg8_trigger_mode_pluse_freq_num <= wr_data; + 32'hF: regF_manual_trigger_sig <= wr_data; + default: begin + end + endcase + end + end + end + + wire sig_af_choose_af_filter; + zutils_signal_filter_advance filter ( + .clk (clk), + .rst_n (rst_n), + .filter_delay_count(reg2_fileter_coefficient), + .in (triSig), + .out (sig_af_choose_af_filter) + ); + + + zutils_freq_detector_v2 freq_detector1 ( + .clk (clk), + .rst_n (rst_n), + .freq_detect_bias(reg3_freq_detect_bias), + .pluse_input (sig_af_choose_af_filter), + .pluse_width_cnt (regD_in_signal_freq) + ); + + zutils_freq_detector_v2 freq_detector2 ( + .clk (clk), + .rst_n (rst_n), + .freq_detect_bias(reg3_freq_detect_bias), + .pluse_input (signal_out_final), + .pluse_width_cnt (regE_out_signal_freq) + ); + + + +endmodule diff --git a/source/src/business/record_sig_generator.v b/source/src/business/record_sig_generator.v deleted file mode 100644 index 58d0fbe..0000000 --- a/source/src/business/record_sig_generator.v +++ /dev/null @@ -1,253 +0,0 @@ -module record_sig_generator #( - parameter REG_START_ADD = 0, - parameter SYS_CLOCK_FREQ = 100000000, - parameter TEST = 0 -) ( - input clk, - input rst_n, - - input [31:0] addr, - input [31:0] wr_data, - input wr_en, - output wire [31:0] rd_data, - - input wire ttlin1_sig, - input wire ttlin2_sig, - input wire ttlin3_sig, - input wire ttlin4_sig, - - input wire frame_freq_sig, - input wire sys_timecode_tigger_sig, - input wire [63:0] sys_timecode_data, - - output reg out_record_en_sig, //!录制使能信号 - output reg out_record_exposure_sig //!录制曝光信号 - -); - - - - reg [31:0] reg1_ctrl_control_mode; //! 控制模式选择寄存器 - - reg [31:0] reg2_timecode_start0; //! 时码启动寄存器0 - reg [31:0] reg3_timecode_start1; //! 时码启动寄存器1 - reg [31:0] reg4_timecode_stop0; //! 时码停止寄存器0 - reg [31:0] reg5_timecode_stop1; //! 时码停止寄存器1 - reg [31:0] reg6_timecode_control_flag; //! 使能时码控制启动,使能使能时码控制停止 - - reg [31:0] reg7_ttlin_trigger_sig_source; //! TTL触发信号选择 - reg [31:0] reg8_ttlin_trigger_level; //! TTL输入信号极性反转 - - reg [31:0] reg9_exposure_time; //! 曝光时长 - reg [31:0] regA_exposure_delay; //! 曝光信号延迟 - - reg [31:0] regB_manual_ctrl; //! 手动控制 - localparam REGA_MANUAL_CTRL_REG_INDEX = 32'd11; - - reg [31:0] regD_timecode_snapshot0; //! - reg [31:0] regE_timecode_snapshot1; //! - reg [31:0] regF_record_state; //!工作状态 read only - - wire [31:0] reg_wr_index; - - zutils_register_advanced #( - .REG_START_ADD(REG_START_ADD) - ) _register ( - .clk (clk), - .rst_n (rst_n), - .addr (addr), - .wr_data(wr_data), - .wr_en (wr_en), - .rd_data(rd_data), - - .reg1(reg1_ctrl_control_mode), - .reg2(reg2_timecode_start0), - .reg3(reg3_timecode_start1), - .reg4(reg4_timecode_stop0), - .reg5(reg5_timecode_stop1), - .reg6(reg6_timecode_control_flag), - .reg7(reg7_ttlin_trigger_sig_source), - .reg8(reg8_ttlin_trigger_level), - .reg9(reg9_exposure_time), - .regA(regA_exposure_delay), - - .regB(regB_manual_ctrl), - .regD(regD_timecode_snapshot0), - .regE(regE_timecode_snapshot1), - .regF(regF_record_state), - - .reg_wr_sig(reg_wr_sig), - .reg_index (reg_wr_index) - ); - - always @(posedge clk or negedge rst_n) begin - if (!rst_n) begin - reg1_ctrl_control_mode <= 1; - reg2_timecode_start0 <= 0; - reg3_timecode_start1 <= 0; - reg4_timecode_stop0 <= 0; - reg5_timecode_stop1 <= 0; - reg6_timecode_control_flag <= 32'hFFFF_FFFF; - reg7_ttlin_trigger_sig_source <= 1; - reg8_ttlin_trigger_level <= 1; - reg9_exposure_time <= 32'd1000; //100us - regA_exposure_delay <= 0; - regB_manual_ctrl <= 0; - end else begin - if (reg_wr_sig) begin - case (reg_wr_index) - 1: reg1_ctrl_control_mode <= wr_data; - 2: reg2_timecode_start0 <= wr_data; - 3: reg3_timecode_start1 <= wr_data; - 4: reg4_timecode_stop0 <= wr_data; - 5: reg5_timecode_stop1 <= wr_data; - 6: reg6_timecode_control_flag <= wr_data; - 7: reg7_ttlin_trigger_sig_source <= wr_data; - 8: reg8_ttlin_trigger_level <= wr_data; - 9: reg9_exposure_time <= wr_data; - 10: regA_exposure_delay <= wr_data; - default: begin - end - endcase - end - end - end - - - wire ttl_in_choose; //! 选中的ttl触发信号,(已经经过电平翻转) - wire timecode_start_trigger_sig; //!timecode启动信号 - wire timecode_stop_trigger_sig; //!timecode停止信号 - wire record_exposure_sig; //!曝光信号 - wire frame_freq_sig_rising_edge; - - - zutils_multiplexer_32t1_v2 ttlin_level_trigger_multi ( - .chooseindex(reg7_ttlin_trigger_sig_source), - //in - .in1 (ttlin1_sig ^ (!reg8_ttlin_trigger_level[0])), - .in2 (ttlin2_sig ^ (!reg8_ttlin_trigger_level[0])), - .in3 (ttlin3_sig ^ (!reg8_ttlin_trigger_level[0])), - .in4 (ttlin4_sig ^ (!reg8_ttlin_trigger_level[0])), - //out - .out (ttl_in_choose) - ); - - /******************************************************************************* - * StartSig输出 * - *******************************************************************************/ - - timecode_comparator timecode_comparator_inst0 ( - .timecodeA0(sys_timecode_data[31:0]), - .timecodeA1(sys_timecode_data[63:32]), - .timecodeB0(reg2_timecode_start0), - .timecodeB1(reg3_timecode_start1), - .eq (timecode_start_trigger_sig) - ); - - timecode_comparator timecode_comparator_inst1 ( - .timecodeA0(sys_timecode_data[31:0]), - .timecodeA1(sys_timecode_data[63:32]), - .timecodeB0(reg4_timecode_stop0), - .timecodeB1(reg5_timecode_stop1), - .eq (timecode_stop_trigger_sig) - ); - - - zutils_edge_detecter _signal_in ( - .clk (clk), - .rst_n (rst_n), - .in_signal (frame_freq_sig), - .in_signal_rising_edge(frame_freq_sig_rising_edge) - ); - - zutils_pluse_generator _pluse_generator ( - .clk (clk), - .rst_n (rst_n), - .pluse_width (reg9_exposure_time), - .pluse_delay (regA_exposure_delay), - .trigger (frame_freq_sig_rising_edge), - .output_signal(record_exposure_sig) - ); - - reg en_state; - always @(posedge clk or negedge rst_n) begin - if (!rst_n) begin - en_state <= 0; - end else begin - case (reg1_ctrl_control_mode) - 1: begin - //手动控制触发启动停止 - if (reg_wr_sig && reg_wr_index == REGA_MANUAL_CTRL_REG_INDEX) begin - if (wr_data[0] == 1) begin - en_state <= 1; - end else begin - en_state <= 0; - end - end - - end - 2: begin - //TIMECODE控制启动 - if (timecode_start_trigger_sig && sys_timecode_tigger_sig && reg6_timecode_control_flag[0]) begin - en_state <= 1; - end else if (timecode_stop_trigger_sig && sys_timecode_tigger_sig && reg6_timecode_control_flag[1]) begin - en_state <= 0; - end else if (reg_wr_sig && reg_wr_index == REGA_MANUAL_CTRL_REG_INDEX) begin - if (wr_data[0] == 1) begin - en_state <= 1; - end else begin - en_state <= 0; - end - end - end - - 3: begin - //外部电平控制 - if (ttl_in_choose == 1) begin - en_state <= 1; - end else begin - en_state <= 0; - end - end - default: begin - end - endcase - end - end - - - reg en_state_af_sync; - always @(posedge clk or negedge rst_n) begin - if (!rst_n) begin - en_state_af_sync <= 0; - end else begin - case (en_state) - 0: begin - if (en_state_af_sync != en_state) begin - regD_timecode_snapshot0 <= sys_timecode_data[31:0]; - regE_timecode_snapshot1 <= sys_timecode_data[63:32]; - en_state_af_sync <= 0; - end - end - - 1: begin - if (en_state_af_sync == 0) begin - if (frame_freq_sig_rising_edge) begin - regD_timecode_snapshot0 <= sys_timecode_data[31:0]; - regE_timecode_snapshot1 <= sys_timecode_data[63:32]; - en_state_af_sync <= 1; - end - end - end - endcase - end - end - - - always @(*) begin - regF_record_state[0] <= en_state_af_sync; - out_record_en_sig <= en_state_af_sync; - out_record_exposure_sig <= out_record_en_sig & record_exposure_sig; - end - -endmodule diff --git a/source/src/config.v b/source/src/config.v index 005206a..c882c48 100644 --- a/source/src/config.v +++ b/source/src/config.v @@ -3,68 +3,13 @@ * 寄存器地址分配 * *******************************************************************************/ `define REGADDOFF__FPGA_INFO 16'h1000 -`define REGADDOFF__INTERNAL_CLK 16'h1020 -`define REGADDOFF__INTERNAL_TRIGGER 16'h1040 +`define REGADDOFF__APP 16'h1020 -`define REGADDOFF__TRIGGER_IN1 16'h2000 -`define REGADDOFF__TRIGGER_IN2 16'h2020 -`define REGADDOFF__TRIGGER_IN3 16'h2040 -`define REGADDOFF__TRIGGER_IN4 16'h2060 -`define REGADDOFF__LIGHT_CTROL_MODULE1 16'h3000 -`define REGADDOFF__LIGHT_CTROL_MODULE2 16'h3020 -`define REGADDOFF__LIGHT_CTROL_MODULE3 16'h3040 -`define REGADDOFF__LIGHT_CTROL_MODULE4 16'h3060 - -`define REGADDOFF__TTL_OUTPUT_MODULE1 16'h4000 -`define REGADDOFF__TTL_OUTPUT_MODULE2 16'h4020 -`define REGADDOFF__TTL_OUTPUT_MODULE3 16'h4040 -`define REGADDOFF__TTL_OUTPUT_MODULE4 16'h4060 - /******************************************************************************* * 部分寄存器初始化数值 * *******************************************************************************/ `define FREQ_DETECT_BIAS_DEFAULT 32'd100 `define FREQ_TTL_INPUT_FILTER 32'd10 -/******************************************************************************* - * 公共信号ID * - *******************************************************************************/ -`define SIG_LOGIC0 32'd0 -`define SIG_LOGIC1 32'd1 - -`define SIG_INTERNAL_CLK 32'd2 -`define SIG_INTERNAL_CLK_I1 32'd3 -`define SIG_INTERNAL_CLK_I2 32'd4 -`define SIG_INTERNAL_CLK_I3 32'd5 -`define SIG_INTERNAL_CLK_I4 32'd6 - -`define SIG_EXT_TRIGGER_1 32'd7 -`define SIG_EXT_TRIGGER_1_I1 32'd8 -`define SIG_EXT_TRIGGER_1_I2 32'd9 -`define SIG_EXT_TRIGGER_1_I3 32'd10 -`define SIG_EXT_TRIGGER_1_I4 32'd11 - -`define SIG_EXT_TRIGGER_2 32'd12 -`define SIG_EXT_TRIGGER_2_I1 32'd13 -`define SIG_EXT_TRIGGER_2_I2 32'd14 -`define SIG_EXT_TRIGGER_2_I3 32'd15 -`define SIG_EXT_TRIGGER_2_I4 32'd16 - -`define SIG_EXT_TRIGGER_3 32'd17 -`define SIG_EXT_TRIGGER_3_I1 32'd18 -`define SIG_EXT_TRIGGER_3_I2 32'd19 -`define SIG_EXT_TRIGGER_3_I3 32'd20 -`define SIG_EXT_TRIGGER_3_I4 32'd21 - -`define SIG_EXT_TRIGGER_4 32'd22 -`define SIG_EXT_TRIGGER_4_I1 32'd23 -`define SIG_EXT_TRIGGER_4_I2 32'd24 -`define SIG_EXT_TRIGGER_4_I3 32'd25 -`define SIG_EXT_TRIGGER_4_I4 32'd26 - - -`define SIG_PROCESS_MODE__TRIGGER_MODE 32'd0 -`define SIG_PROCESS_MODE__TRANSPARENT_MODE 32'd1 -`define SIG_PROCESS_MODE__BIND_MODE 32'd2 diff --git a/source/src/internal/internal_clock_generator.v b/source/src/internal/internal_clock_generator.v deleted file mode 100644 index faf7cf6..0000000 --- a/source/src/internal/internal_clock_generator.v +++ /dev/null @@ -1,117 +0,0 @@ -`include "../config.v" -module internal_clock_generator #( - parameter REG_START_ADD = 0, - parameter SYS_CLOCK_FREQ = 100000000 -) ( - - input clk, //! 时钟输入 - input rst_n, //! 复位输入 - - input [31:0] addr, //! 寄存器地址 - input [31:0] wr_data, //! 写入数据 - input wr_en, //! 写使能 - output wire [31:0] rd_data, //! 读出数据 - - output clk_output //! 输出频率 - -); - - reg [31:0] r1_contrl_mode; //! 控制模式,目前未使用 - reg [31:0] r2_en; //!使能控制 - reg [31:0] r3_setting_cnt; //!格式 - wire [31:0] r4_detect_freq; //!输出频率探测 - - wire [31:0] reg_wr_index; - zutils_register_advanced #( - .REG_START_ADD(REG_START_ADD) - ) _register ( - .clk (clk), - .rst_n (rst_n), - .addr (addr), - .wr_data (wr_data), - .wr_en (wr_en), - .rd_data (rd_data), - .reg1 (r1_contrl_mode), - .reg2 (r2_en), - .reg3 (r3_setting_cnt), - .reg4 (r4_detect_freq), - .reg_wr_sig(reg_wr_sig), - .reg_index (reg_wr_index) - ); - - always @(posedge clk or negedge rst_n) begin - if (!rst_n) begin - r1_contrl_mode <= 0; - r2_en <= 1; - r3_setting_cnt <= (32'd1_000_000 - 32'd1); - end else begin - if (reg_wr_sig) begin - case (reg_wr_index) - 1: r1_contrl_mode <= wr_data; - 2: r2_en <= wr_data; - 3: r3_setting_cnt <= wr_data; - default: begin - end - endcase - end - end - end - - - reg state; - reg [31:0] cnt; - reg clk_sig; - always @(posedge clk or negedge rst_n) begin - if (!rst_n) begin - state <= 0; - clk_sig <= 0; - cnt <= 0; - end else begin - case (state) - 0: begin - cnt <= 0; - clk_sig <= 0; - - if (r2_en[0]) begin - state <= 1; - clk_sig <= 1; - end - - end - 1: begin - if (!r2_en[0]) begin - state <= 0; - end else begin - if (cnt < (r3_setting_cnt >> 1)) begin - cnt <= cnt + 1; - clk_sig <= 1; - end else if (cnt >= (r3_setting_cnt >> 1) && cnt < r3_setting_cnt) begin - cnt <= cnt + 1; - clk_sig <= 0; - end else begin - cnt <= 0; - clk_sig <= 1; - end - end - end - endcase - end - end - - - - zutils_freq_detector_v2 freq_detector1 ( - .clk (clk), - .rst_n (rst_n), - .freq_detect_bias(1), - .pluse_input (clk_sig), - .pluse_width_cnt (r4_detect_freq) - ); - - assign clk_output = clk_sig; - - - - - -endmodule diff --git a/source/src/internal/internal_genlock_generator.v b/source/src/internal/internal_genlock_generator.v deleted file mode 100644 index dbd9443..0000000 --- a/source/src/internal/internal_genlock_generator.v +++ /dev/null @@ -1,116 +0,0 @@ -`include "../config.v" -module internal_genlock_generator #( - parameter REG_START_ADD = 0, - parameter SYS_CLOCK_FREQ = 100000000 -) ( - - input clk, //! 时钟输入 - input rst_n, //! 复位输入 - - input [31:0] addr, //! 寄存器地址 - input [31:0] wr_data, //! 写入数据 - input wr_en, //! 写使能 - output wire [31:0] rd_data, //! 读出数据 - - output genlock_freq_signal //! genlock freq signal - -); - - reg [31:0] r1_contrl_mode; //! 控制模式,目前未使用 - reg [31:0] r2_en; //!使能控制 - reg [31:0] r3_format; //!格式 - wire [31:0] r4_detect_freq; //!输出频率探测 - - wire [31:0] reg_wr_index; - zutils_register_advanced #( - .REG_START_ADD(REG_START_ADD) - ) _register ( - .clk (clk), - .rst_n (rst_n), - .addr (addr), - .wr_data (wr_data), - .wr_en (wr_en), - .rd_data (rd_data), - .reg1 (r1_contrl_mode), - .reg2 (r2_en), - .reg3 (r3_format), - .reg4 (r4_detect_freq), - .reg_wr_sig(reg_wr_sig), - .reg_index (reg_wr_index) - ); - - always @(posedge clk or negedge rst_n) begin - if (!rst_n) begin - r1_contrl_mode <= 0; - r2_en <= 1; - r3_format <= 0; - end else begin - if (reg_wr_sig) begin - case (reg_wr_index) - 1: r1_contrl_mode <= wr_data; - 2: r2_en <= wr_data; - 3: r3_format <= wr_data; - default: begin - end - endcase - end - end - end - - wire genlock_fps2397_clk; - wire genlock_fps2398_clk; - wire genlock_fps2400_clk; - wire genlock_fps2500_clk; - wire genlock_fps2997_clk; - wire genlock_fps3000_clk; - wire genlock_fps5000_clk; - wire genlock_fps5994_clk; - wire genlock_fps6000_clk; - wire genlock_sig_output; - - zutils_genlock_clk_generator #( - .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ) - ) genlock ( - .clk (clk), - .rst_n (rst_n), - .ctrl_sig (r2_en[0]), - .genlock_fps2397_clk(genlock_fps2397_clk), - .genlock_fps2398_clk(genlock_fps2398_clk), - .genlock_fps2400_clk(genlock_fps2400_clk), - .genlock_fps2500_clk(genlock_fps2500_clk), - .genlock_fps2997_clk(genlock_fps2997_clk), - .genlock_fps3000_clk(genlock_fps3000_clk), - .genlock_fps5000_clk(genlock_fps5000_clk), - .genlock_fps5994_clk(genlock_fps5994_clk), - .genlock_fps6000_clk(genlock_fps6000_clk) - ); - - zutils_multiplexer_32t1_v2 genlock_clk_output_mult ( - .chooseindex(r3_format), - //in - .in0 (genlock_fps2397_clk), - .in1 (genlock_fps2398_clk), - .in2 (genlock_fps2400_clk), - .in3 (genlock_fps2500_clk), - .in4 (genlock_fps2997_clk), - .in5 (genlock_fps3000_clk), - .in6 (genlock_fps5000_clk), - .in7 (genlock_fps5994_clk), - .in8 (genlock_fps6000_clk), - //out - .out (genlock_sig_output) - ); - - zutils_freq_detector_v2 freq_detector1 ( - .clk (clk), - .rst_n (rst_n), - .freq_detect_bias(1), - .pluse_input (genlock_sig_output), - .pluse_width_cnt (r4_detect_freq) - ); - - - assign genlock_freq_signal = genlock_sig_output; - assign genlock_in_state_led = 1; - -endmodule diff --git a/source/src/internal/internal_timecode_generator.v b/source/src/internal/internal_timecode_generator.v deleted file mode 100644 index f6527f2..0000000 --- a/source/src/internal/internal_timecode_generator.v +++ /dev/null @@ -1,94 +0,0 @@ -module internal_timecode_generator #( - parameter REG_START_ADD = 0, - parameter SYS_CLOCK_FREQ = 100000000, - parameter ID = 1 -) ( - input clk, //clock input - input rst_n, //asynchronous reset input, low active - - //寄存器读写接口 - input [31:0] addr, - input [31:0] wr_data, - input wr_en, - output wire [31:0] rd_data, - - output timecode_tigger_sig, - output [31:0] timecode_format, - output [63:0] timecode_data, - output timecode_serial_data -); - - /******************************************************************************* - * 寄存器列表 * - *******************************************************************************/ - reg [31:0] reg1_timecode_en; //!内部时码使能控制 - reg [31:0] reg2_timecode_format; //!内部时码格式 - wire [31:0] reg3_timecode_data0; //!时码数值0 - wire [31:0] reg4_timecode_data1; //!时码数值1 - - wire [31:0] reg_wr_index; //!寄存器写入时相对地址 - - - //!TTLOUT_寄存器自动赋值选择器 - zutils_register_advanced #( - .REG_START_ADD(REG_START_ADD) - ) _register ( - .clk (clk), - .rst_n (rst_n), - .addr (addr), - .wr_data (wr_data), - .wr_en (wr_en), - .rd_data (rd_data), - .reg1 (reg1_timecode_en), - .reg2 (reg2_timecode_format), - .reg3 (reg3_timecode_data0), - .reg4 (reg4_timecode_data1), - .reg_wr_sig(reg_wr_sig), - .reg_index (reg_wr_index) - ); - - //!寄存器写入逻辑 - always @(posedge clk or negedge rst_n) begin - if (!rst_n) begin - reg1_timecode_en <= 1; - reg2_timecode_format <= 0; - end else begin - if (reg_wr_sig) begin - case (reg_wr_index) - 1: reg1_timecode_en <= wr_data; - 2: reg2_timecode_format <= wr_data; - default: begin - end - endcase - end - end - end - - - timecode_generator #( - .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ) - ) timecode_generator_ist ( - .clk (clk), - .rst_n(rst_n), - - .timecode_format(reg2_timecode_format), - - .timecode0_wen (reg_wr_sig && reg_wr_index == 3), - .timecode0 (wr_data), - .timecode0_export(reg3_timecode_data0), - - .timecode1_wen (reg_wr_sig && reg_wr_index == 4), - .timecode1 (wr_data), - .timecode1_export(reg4_timecode_data1), - - .en(reg1_timecode_en[0]), - - .out_timecode_serial_data(timecode_serial_data), - .out_trigger_sig (timecode_tigger_sig), - .out_timecode0 (timecode_data[31:0]), - .out_timecode1 (timecode_data[63:32]) - ); - - - assign timecode_format = reg2_timecode_format; -endmodule diff --git a/source/src/output/light_src_ctrl.v b/source/src/output/light_src_ctrl.v deleted file mode 100644 index 45b5df5..0000000 --- a/source/src/output/light_src_ctrl.v +++ /dev/null @@ -1,194 +0,0 @@ -`include "../config.v" -module light_src_ctrl #( - parameter REG_START_ADD = 0, - parameter SYS_CLOCK_FREQ = 100000000, - parameter ID = 1 -) ( - input clk, //clock input - input rst_n, //asynchronous reset input, low active - - //寄存器读写接口 - input [31:0] addr, - input [31:0] wr_data, - input wr_en, - output wire [31:0] rd_data, - - input [31:0] signal_in, - - output wire lt_intensity_ctrl, - output wire lt_en, - input wire lt_error_sig_in -); - - /******************************************************************************* - * 寄存器列表 * - *******************************************************************************/ - - reg [31:0] reg1_source_select; - reg [31:0] reg2_en_sig_ctrl_mode; //!0:触发模式 1:转发模式 - reg [31:0] reg3_light_intensity_ctrl_mode; //!0:固定强度 - reg [31:0] reg4_trigger_mode_pluse_num; - reg [31:0] reg5_trigger_mode_pluse_interval; - reg [31:0] reg6_trigger_mode_pluse_width; - reg [31:0] reg7_trigger_mode_first_pluse_offset; - reg [31:0] reg8_trigger_mode_output_polarity; - reg [31:0] reg9_light_intensity_cnt; - reg [31:0] regA_light_driver_freq_cnt; - reg [31:0] regC_freq_detect_bias; - reg [31:0] regD_light_src_error_state; - wire [31:0] regE_in_sig_freq_detect; - wire [31:0] regF_out_sig_freq_detect; - wire [31:0] reg_wr_index; //!寄存器写入时相对地址 - - - - //!TTLOUT_寄存器自动赋值选择器 - zutils_register_advanced #( - .REG_START_ADD(REG_START_ADD) - ) _register ( - .clk (clk), - .rst_n (rst_n), - .addr (addr), - .wr_data(wr_data), - .wr_en (wr_en), - .rd_data(rd_data), - - .reg1(reg1_source_select), - .reg2(reg2_en_sig_ctrl_mode), - .reg3(reg3_light_intensity_ctrl_mode), - .reg4(reg4_trigger_mode_pluse_num), - .reg5(reg5_trigger_mode_pluse_interval), - .reg6(reg6_trigger_mode_pluse_width), - .reg7(reg7_trigger_mode_first_pluse_offset), - .reg8(reg8_trigger_mode_output_polarity), - .reg9(reg9_light_intensity_cnt), - .regA(regA_light_driver_freq_cnt), - .regC(regC_freq_detect_bias), - .regD(regD_light_src_error_state), - .regE(regE_in_sig_freq_detect), - .regF(regF_out_sig_freq_detect), - - .reg_wr_sig(reg_wr_sig), - .reg_index (reg_wr_index) - ); - - //!寄存器写入逻辑 - - localparam pluse_interval_init_val = 1 * (SYS_CLOCK_FREQ / 32'd1000_000); //1us - localparam pluse_width_initval = 30 * (SYS_CLOCK_FREQ / 32'd1000_000); //1us - - always @(posedge clk or negedge rst_n) begin - if (!rst_n) begin - reg1_source_select <= `SIG_INTERNAL_CLK; - reg2_en_sig_ctrl_mode <= 0; - reg3_light_intensity_ctrl_mode <= 0; - reg4_trigger_mode_pluse_num <= 1; - reg5_trigger_mode_pluse_interval <= pluse_interval_init_val; - reg6_trigger_mode_pluse_width <= pluse_width_initval; - reg7_trigger_mode_first_pluse_offset <= pluse_interval_init_val * ID + ((ID - 1) * pluse_width_initval); - reg8_trigger_mode_output_polarity <= 1; - reg9_light_intensity_cnt <= (SYS_CLOCK_FREQ / 30000 / 10); //100k - regA_light_driver_freq_cnt <= (SYS_CLOCK_FREQ / 30000); //100k - regC_freq_detect_bias <= `FREQ_DETECT_BIAS_DEFAULT; - end else begin - if (reg_wr_sig) begin - case (reg_wr_index) - 32'h1: reg1_source_select <= wr_data; - 32'h2: reg2_en_sig_ctrl_mode <= wr_data; - 32'h3: reg3_light_intensity_ctrl_mode <= wr_data; - 32'h4: reg4_trigger_mode_pluse_num <= wr_data; - 32'h5: reg5_trigger_mode_pluse_interval <= wr_data; - 32'h6: reg6_trigger_mode_pluse_width <= wr_data; - 32'h7: reg7_trigger_mode_first_pluse_offset <= wr_data; - 32'h8: reg8_trigger_mode_output_polarity <= wr_data; - 32'h9: reg9_light_intensity_cnt <= wr_data; - 32'hA: regA_light_driver_freq_cnt <= wr_data; - 32'hC: regC_freq_detect_bias <= wr_data; - default: begin - end - endcase - end - end - end - - - wire signal_in_choose; //!选中的信号 - wire signal_in_choose_rsing_edge; //!选中的信号 - wire signal_en_output; //!EN信号输出 - wire signal_lt_intensity; //!光强输出 - - //!信号选择器 - zutils_multiplexer_32t1 signal_in_multiplexer ( - .chooseindex(reg1_source_select), - .signal (signal_in), - .signalout (signal_in_choose) - ); - - zutils_edge_detecter edge_detecter ( - .clk (clk), - .rst_n (rst_n), - .in_signal (signal_in_choose), - .in_signal_rising_edge(signal_in_choose_rsing_edge) - ); - - - zutils_pluse_generator_v2 pluse_generator ( - .clk (clk), - .rst_n(rst_n), - - .pluse_width (reg6_trigger_mode_pluse_width), - .pluse_delay (reg7_trigger_mode_first_pluse_offset), - .trigger (signal_in_choose_rsing_edge), - .output_signal(signal_en_output) - - ); - - - /******************************************************************************* - * 光源亮度信号发生器 * - *******************************************************************************/ - zutils_pwm_generator_v2 signal_lt_intensity_generator ( - .clk (clk), - .rst_n(rst_n), - - .pluse_width_cnt (reg9_light_intensity_cnt), - .pluse_period_cnt(regA_light_driver_freq_cnt), - - .output_signal(signal_lt_intensity) - ); - - /******************************************************************************* - * 异常信号捕获 * - *******************************************************************************/ - always @(posedge clk or negedge rst_n) begin - if (!rst_n) begin - regD_light_src_error_state <= 0; - end else begin - regD_light_src_error_state[0] <= lt_error_sig_in; - end - end - - - zutils_freq_detector_v2 freq_detector1 ( - .clk (clk), - .rst_n (rst_n), - .freq_detect_bias(regC_freq_detect_bias), - .pluse_input (signal_in_choose), - .pluse_width_cnt (regE_in_sig_freq_detect) - ); - - zutils_freq_detector_v2 freq_detector2 ( - .clk (clk), - .rst_n (rst_n), - .freq_detect_bias(regC_freq_detect_bias), - .pluse_input (signal_en_output), - .pluse_width_cnt (regF_out_sig_freq_detect) - ); - - - - assign lt_intensity_ctrl = signal_lt_intensity; - assign lt_en = signal_en_output; - -endmodule - diff --git a/source/src/output/ttl_output_ctrl.v b/source/src/output/ttl_output_ctrl.v deleted file mode 100644 index 4352bcb..0000000 --- a/source/src/output/ttl_output_ctrl.v +++ /dev/null @@ -1,143 +0,0 @@ -`include "../config.v" -module ttl_output_ctrl #( - parameter REG_START_ADD = 0, - parameter SYS_CLOCK_FREQ = 32'd100_000_000, - parameter ID = 1 -) ( - input clk, //clock input - input rst_n, //asynchronous reset input, low active - - //寄存器读写接口 - input [31:0] addr, - input [31:0] wr_data, - input wr_en, - output wire [31:0] rd_data, - - - input wire [ 3:0] lt_en_sig, - input wire [31:0] sys_internal_sig_bus, - - output wire diff_out, - output wire optocoupler_out -); - - /******************************************************************************* - * 寄存器列表 * - *******************************************************************************/ - - reg [31:0] reg1_output_ctrl_mode; //!0:绑定模式 - reg [31:0] reg2_lt_en_bind; //!绑定的光源信号 - reg [31:0] reg3_lt_en_offset; //!快门信号与曝光信号偏移 - reg [31:0] reg4_in_sig_select; //!转发模式下信号选择器 - reg [31:0] reg5_output_polarity_reversal; //!转发模式下信号选择器 - wire [31:0] reg_wr_index; - - //!TTLOUT_寄存器自动赋值选择器 - zutils_register_advanced #( - .REG_START_ADD(REG_START_ADD) - ) _register ( - .clk (clk), - .rst_n (rst_n), - .addr (addr), - .wr_data(wr_data), - .wr_en (wr_en), - .rd_data(rd_data), - - .reg1(reg1_output_ctrl_mode), - .reg2(reg2_lt_en_bind), - .reg3(reg3_lt_en_offset), - .reg4(reg4_in_sig_select), - .reg5(reg5_output_polarity_reversal), - - .reg_wr_sig(reg_wr_sig), - .reg_index (reg_wr_index) - ); - - //!寄存器写入逻辑 - always @(posedge clk or negedge rst_n) begin - if (!rst_n) begin - reg1_output_ctrl_mode <= `SIG_PROCESS_MODE__BIND_MODE; - reg2_lt_en_bind <= 32'hffff_ffff; - reg3_lt_en_offset <= (SYS_CLOCK_FREQ / 32'd1000_000); //1us - reg4_in_sig_select <= 0; - reg5_output_polarity_reversal <= 0; - end else begin - if (reg_wr_sig) begin - case (reg_wr_index) - 32'h1: reg1_output_ctrl_mode <= wr_data; - 32'h2: reg2_lt_en_bind <= wr_data; - 32'h3: reg3_lt_en_offset <= wr_data; - 32'h4: reg4_in_sig_select <= wr_data; - 32'h5: reg5_output_polarity_reversal <= wr_data; - default: begin - end - endcase - end - end - end - - reg trigger_sig; //! 触发信号 - reg [31:0] cnt; //! 计数器 - reg output_sig_0; //!延后的触发信号 - reg output_sig; //!最终输出的信号 - reg [31:0] lt_en_offset_offset; //!延后偏移缓存 - - always @(posedge clk or negedge rst_n) begin - if (!rst_n) begin - trigger_sig <= 0; - end else begin - trigger_sig <= (lt_en_sig[0] & reg2_lt_en_bind[0]) // - | (lt_en_sig[1] & reg2_lt_en_bind[1]) // - | (lt_en_sig[2] & reg2_lt_en_bind[2]) // - | (lt_en_sig[3] & reg2_lt_en_bind[3]); - end - end - - - - always @(posedge clk or negedge rst_n) begin - if (!rst_n) begin - cnt <= 0; - output_sig_0 <= 0; - end else begin - if (trigger_sig) begin - if (cnt == 0) begin - cnt <= cnt + 1; - lt_en_offset_offset <= reg3_lt_en_offset; - output_sig_0 <= 0; - end else begin - if (cnt <= lt_en_offset_offset) begin - cnt <= cnt + 1; - output_sig_0 <= 0; - end else begin - cnt <= cnt; - output_sig_0 <= 1; - end - end - end else begin - cnt <= 0; - output_sig_0 <= 0; - end - end - end - - zutils_multiplexer_32t1 signal_in_multiplexer ( - .chooseindex(reg4_in_sig_select), - .signal (sys_internal_sig_bus), - .signalout (signal_in_choose) - ); - - always @(*) begin - case (reg1_output_ctrl_mode) - `SIG_PROCESS_MODE__BIND_MODE: output_sig <= (output_sig_0 & trigger_sig) ^ (reg5_output_polarity_reversal); - `SIG_PROCESS_MODE__TRANSPARENT_MODE: output_sig <= signal_in_choose ^ reg5_output_polarity_reversal; - default: begin - output_sig <= 0; - end - endcase - end - - assign diff_out = output_sig; - assign optocoupler_out = output_sig; - -endmodule diff --git a/source/src/spi_reg_bus.v b/source/src/spi_reg_bus.v index 8d3a92f..00e676b 100644 --- a/source/src/spi_reg_bus.v +++ b/source/src/spi_reg_bus.v @@ -14,23 +14,7 @@ module spi_reg_bus ( output wire spi_tx_pin, input [31:0] rd_data_fpga_info, - input [31:0] rd_data_internal_trigger, - input [31:0] rd_data_internal_clk, - - input [31:0] rd_data_trigger_in1, - input [31:0] rd_data_trigger_in2, - input [31:0] rd_data_trigger_in3, - input [31:0] rd_data_trigger_in4, - - input [31:0] rd_data_light_ctrol_module1, - input [31:0] rd_data_light_ctrol_module2, - input [31:0] rd_data_light_ctrol_module3, - input [31:0] rd_data_light_ctrol_module4, - - input [31:0] rd_data_ttl_output_module1, - input [31:0] rd_data_ttl_output_module2, - input [31:0] rd_data_ttl_output_module3, - input [31:0] rd_data_ttl_output_module4 + input [31:0] rd_data_app ); reg [31:0] rd_data; spi_reg_reader spi_reg_reader_inst ( @@ -52,29 +36,9 @@ module spi_reg_bus ( always @(*) begin case (addr_group) - `REGADDOFF__FPGA_INFO: rd_data <= rd_data_fpga_info; - `REGADDOFF__INTERNAL_TRIGGER: rd_data <= rd_data_internal_trigger; - `REGADDOFF__INTERNAL_CLK: rd_data <= rd_data_internal_clk; - - `REGADDOFF__TRIGGER_IN1: rd_data <= rd_data_trigger_in1; - `REGADDOFF__TRIGGER_IN2: rd_data <= rd_data_trigger_in2; - `REGADDOFF__TRIGGER_IN3: rd_data <= rd_data_trigger_in3; - `REGADDOFF__TRIGGER_IN4: rd_data <= rd_data_trigger_in4; - - - `REGADDOFF__LIGHT_CTROL_MODULE1: rd_data <= rd_data_light_ctrol_module1; - `REGADDOFF__LIGHT_CTROL_MODULE2: rd_data <= rd_data_light_ctrol_module2; - `REGADDOFF__LIGHT_CTROL_MODULE3: rd_data <= rd_data_light_ctrol_module3; - `REGADDOFF__LIGHT_CTROL_MODULE4: rd_data <= rd_data_light_ctrol_module4; - - - `REGADDOFF__TTL_OUTPUT_MODULE1: rd_data <= rd_data_ttl_output_module1; - `REGADDOFF__TTL_OUTPUT_MODULE2: rd_data <= rd_data_ttl_output_module2; - `REGADDOFF__TTL_OUTPUT_MODULE3: rd_data <= rd_data_ttl_output_module3; - `REGADDOFF__TTL_OUTPUT_MODULE4: rd_data <= rd_data_ttl_output_module4; - - - default: rd_data <= 0; + `REGADDOFF__FPGA_INFO: rd_data <= rd_data_fpga_info; + `REGADDOFF__APP: rd_data <= rd_data_app; + default: rd_data <= 0; endcase end diff --git a/source/src/timecode/timecode_basesig_generator.v b/source/src/timecode/timecode_basesig_generator.v deleted file mode 100644 index ed279a4..0000000 --- a/source/src/timecode/timecode_basesig_generator.v +++ /dev/null @@ -1,161 +0,0 @@ - -module timecode_basesig_generator #( - parameter SYS_CLOCK_FREQ = 100000000 -) ( - - input clk, - input rst_n, - - input [31:0] timecode_format, - - input wire en, - output out_timecode_trigger_sig, - output reg out_first_frame_sig, - - output reg [7:0] out_frame_num, - output reg out_drop_frame -); - - localparam FPS2398Format = 0; - localparam FPS2400Format = 1; - localparam FPS2500Format = 2; - localparam FPS2997Format = 3; - localparam FPS2997DropFormat = 4; - localparam FPS3000Format = 5; - - - /******************************************************************************* - * clk generator * - *******************************************************************************/ - wire fps2398format_clk; - wire fps2400format_clk; - wire fps2500format_clk; - wire fps2997format_clk; - wire fps2997dropformat_clk; - wire fps3000format_clk; - - zutils_pwm_generator_advanced #( - .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ), - .OUTPUT_FREQ_P00(2398) - ) fps2398format ( - .clk(clk), - .rst_n(rst_n), - .ctrl_sig(en), - .output_signal(fps2398format_clk) - ); - - zutils_pwm_generator_advanced #( - .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ), - .OUTPUT_FREQ_P00(2400) - ) fps2400format ( - .clk(clk), - .rst_n(rst_n), - .ctrl_sig(en), - .output_signal(fps2400format_clk) - ); - - zutils_pwm_generator_advanced #( - .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ), - .OUTPUT_FREQ_P00(2500) - ) fps2500format ( - .clk(clk), - .rst_n(rst_n), - .ctrl_sig(en), - .output_signal(fps2500format_clk) - ); - - zutils_pwm_generator_advanced #( - .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ), - .OUTPUT_FREQ_P00(2997) - ) fps2997format ( - .clk(clk), - .rst_n(rst_n), - .ctrl_sig(en), - .output_signal(fps2997format_clk) - ); - - zutils_pwm_generator_advanced #( - .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ), - .OUTPUT_FREQ_P00(2997) - ) fps2997dropformat ( - .clk(clk), - .rst_n(rst_n), - .ctrl_sig(en), - .output_signal(fps2997dropformat_clk) - ); - - zutils_pwm_generator_advanced #( - .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ), - .OUTPUT_FREQ_P00(3000) - ) fps3000format ( - .clk(clk), - .rst_n(rst_n), - .ctrl_sig(en), - .output_signal(fps3000format_clk) - ); - - - zutils_multiplexer_32t1_v2 timecode_clk_output_mult ( - .chooseindex(timecode_format), - //in - .in0(fps2398format_clk), - .in1(fps2400format_clk), - .in2(fps2500format_clk), - .in3(fps2997format_clk), - .in4(fps2997dropformat_clk), - .in5(fps3000format_clk), - //out - .out(out_timecode_sig_clk_pwm) - ); - - zutils_edge_detecter timecode_sig_clk_output_edge_detecter ( - .clk(clk), - .rst_n(rst_n), - .in_signal(out_timecode_sig_clk_pwm), - .in_signal_rising_edge(out_timecode_trigger_sig) - ); - - - always @(posedge clk or negedge rst_n) begin - if (!rst_n || !en) begin - out_first_frame_sig <= 1; - end else begin - if (out_first_frame_sig && out_timecode_trigger_sig) begin - out_first_frame_sig <= 0; - end - end - end - - /******************************************************************************* - * 格式解析 * - *******************************************************************************/ - - always @(*) begin - case (timecode_format) - FPS2398Format: begin - out_frame_num <= 24; - out_drop_frame <= 0; - end - FPS2400Format: begin - out_frame_num <= 24; - out_drop_frame <= 0; - end - FPS2500Format: begin - out_frame_num <= 25; - out_drop_frame <= 0; - end - FPS2997Format: begin - out_frame_num <= 30; - out_drop_frame <= 0; - end - FPS2997DropFormat: begin - out_frame_num <= 30; - out_drop_frame <= 0; - end - default begin - out_frame_num <= 30; - out_drop_frame <= 0; - end - endcase - end -endmodule diff --git a/source/src/timecode/timecode_comparator.v b/source/src/timecode/timecode_comparator.v deleted file mode 100644 index 020a0f7..0000000 --- a/source/src/timecode/timecode_comparator.v +++ /dev/null @@ -1,58 +0,0 @@ -module timecode_comparator ( - input [31:0] timecodeA0, - input [31:0] timecodeA1, - input [31:0] timecodeB0, - input [31:0] timecodeB1, - output eq -); - - wire [7:0] a_frame; - wire [7:0] a_frame10; - wire [7:0] a_sec; - wire [7:0] a_sec10; - wire [7:0] a_min; - wire [7:0] a_min10; - wire [7:0] a_hour; - wire [7:0] a_hour10; - - wire [7:0] b_frame; - wire [7:0] b_frame10; - wire [7:0] b_sec; - wire [7:0] b_sec10; - wire [7:0] b_min; - wire [7:0] b_min10; - wire [7:0] b_hour; - wire [7:0] b_hour10; - - - assign a_frame = timecodeA0[7:0] & 8'b0000_1111; - assign a_frame10 = timecodeA0[15:8] & 8'b0000_0011; - assign a_sec = timecodeA0[23:16] & 8'b0000_1111; - assign a_sec10 = timecodeA0[31:24] & 8'b0000_0111; - assign a_min = timecodeA1[7:0] & 8'b0000_1111; - assign a_min10 = timecodeA1[15:8] & 8'b0000_0111; - assign a_hour = timecodeA1[23:16] & 8'b0000_1111; - assign a_hour10 = timecodeA1[31:24] & 8'b0000_0011; - - - assign b_frame = timecodeB0[7:0] & 8'b0000_1111; - assign b_frame10 = timecodeB0[15:8] & 8'b0000_0011; - assign b_sec = timecodeB0[23:16] & 8'b0000_1111; - assign b_sec10 = timecodeB0[31:24] & 8'b0000_0111; - assign b_min = timecodeB1[7:0] & 8'b0000_1111; - assign b_min10 = timecodeB1[15:8] & 8'b0000_0111; - assign b_hour = timecodeB1[23:16] & 8'b0000_1111; - assign b_hour10 = timecodeB1[31:24] & 8'b0000_0011; - - - - assign eq = a_frame == b_frame && - a_frame10 == b_frame10 && - a_sec == b_sec && - a_sec10 == b_sec10 && - a_min == b_min && - a_min10 == b_min10 && - a_hour == b_hour && - a_hour10 == b_hour10; - -endmodule diff --git a/source/src/timecode/timecode_decoder.v b/source/src/timecode/timecode_decoder.v deleted file mode 100644 index 986afc6..0000000 --- a/source/src/timecode/timecode_decoder.v +++ /dev/null @@ -1,193 +0,0 @@ -module timecode_decoder #( - parameter SYS_CLOCK_FREQ = 100000000 -) ( - input clk, //clock input - input rst_n, //asynchronous reset input, low active - - input timecode_in, - output timecode_in_state, - - - /******************************************************************************* - * TIMECODE输出 * - *******************************************************************************/ - output reg timecode_tigger_sig, - output reg [63:0] timecode_data, - // output [31:0] timecode_format, - output timecode_serial_data -); - - // Rate 1/2Fe 1Fe - // 23.98 F/s 260.7 us 521.4 us - // 24.00 F/s 260.4 us 520.8 us - // 25.00 F/s 250.0 us 500.0 us - // 29.97 F/s 208.5 us 417.1 us - // 30.00 F/s 208.3 us 416.7 us - - // 260->520 -->130 - // 208->416 -->104 - // ---> 117us 351us - // - // 由于TIMECODE的频率范围是固定的,所以这里采用117,和351作为其采样点,这样既可以采样23.98也可以采样30.00 - // 对应的采样频率为1000000/117=8547HZ - // - - // 原始数据输出 - assign timecode_serial_data = timecode_in; - assign timecode_in_state = timecode_in; - - wire timecode_sample_sig_generator_rest_sig; - wire timecode_in_edge; - assign timecode_sample_sig_generator_rest_sig = !timecode_in_edge & rst_n; - zutils_edge_detecter _signal_in ( - .clk(clk), - .rst_n(rst_n), - .in_signal(timecode_in), - .in_signal_edge(timecode_in_edge) - ); - wire sample_sig; - timecode_sample_sig_generator #( - .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ), - .SAMPLE_RATE(854700) - ) timecode_sample_sig_generator ( - .clk(clk), - .rst_n(timecode_sample_sig_generator_rest_sig), - .sample_sig(sample_sig) - ); - - - // 采样+缓存采样数据 - reg [159:0] timecode_data_cache; - always @(posedge clk or negedge rst_n) begin - if (!rst_n) begin - timecode_data_cache <= 0; - end else begin - if (sample_sig) begin - timecode_data_cache <= {timecode_in,timecode_data_cache[159:1]}; - end else begin - timecode_data_cache <= timecode_data_cache; - end - end - end - - //译码 - reg [79:0] timecode_bit_cache; - // integer i; - always @(*) begin - // for (i = 0; i < 79; i = i + 1) begin - // timecode_bit_cache[i] = timecode_data_cache[i*2] & !timecode_data_cache[i*2+1]; - // end - - timecode_bit_cache[0] = timecode_data_cache[0] ^ timecode_data_cache[1]; - timecode_bit_cache[1] = timecode_data_cache[2] ^ timecode_data_cache[3]; - timecode_bit_cache[2] = timecode_data_cache[4] ^ timecode_data_cache[5]; - timecode_bit_cache[3] = timecode_data_cache[6] ^ timecode_data_cache[7]; - timecode_bit_cache[4] = timecode_data_cache[8] ^ timecode_data_cache[9]; - timecode_bit_cache[5] = timecode_data_cache[10] ^ timecode_data_cache[11]; - timecode_bit_cache[6] = timecode_data_cache[12] ^ timecode_data_cache[13]; - timecode_bit_cache[7] = timecode_data_cache[14] ^ timecode_data_cache[15]; - timecode_bit_cache[8] = timecode_data_cache[16] ^ timecode_data_cache[17]; - timecode_bit_cache[9] = timecode_data_cache[18] ^ timecode_data_cache[19]; - timecode_bit_cache[10] = timecode_data_cache[20] ^ timecode_data_cache[21]; - timecode_bit_cache[11] = timecode_data_cache[22] ^ timecode_data_cache[23]; - timecode_bit_cache[12] = timecode_data_cache[24] ^ timecode_data_cache[25]; - timecode_bit_cache[13] = timecode_data_cache[26] ^ timecode_data_cache[27]; - timecode_bit_cache[14] = timecode_data_cache[28] ^ timecode_data_cache[29]; - timecode_bit_cache[15] = timecode_data_cache[30] ^ timecode_data_cache[31]; - timecode_bit_cache[16] = timecode_data_cache[32] ^ timecode_data_cache[33]; - timecode_bit_cache[17] = timecode_data_cache[34] ^ timecode_data_cache[35]; - timecode_bit_cache[18] = timecode_data_cache[36] ^ timecode_data_cache[37]; - timecode_bit_cache[19] = timecode_data_cache[38] ^ timecode_data_cache[39]; - timecode_bit_cache[20] = timecode_data_cache[40] ^ timecode_data_cache[41]; - timecode_bit_cache[21] = timecode_data_cache[42] ^ timecode_data_cache[43]; - timecode_bit_cache[22] = timecode_data_cache[44] ^ timecode_data_cache[45]; - timecode_bit_cache[23] = timecode_data_cache[46] ^ timecode_data_cache[47]; - timecode_bit_cache[24] = timecode_data_cache[48] ^ timecode_data_cache[49]; - timecode_bit_cache[25] = timecode_data_cache[50] ^ timecode_data_cache[51]; - timecode_bit_cache[26] = timecode_data_cache[52] ^ timecode_data_cache[53]; - timecode_bit_cache[27] = timecode_data_cache[54] ^ timecode_data_cache[55]; - timecode_bit_cache[28] = timecode_data_cache[56] ^ timecode_data_cache[57]; - timecode_bit_cache[29] = timecode_data_cache[58] ^ timecode_data_cache[59]; - timecode_bit_cache[30] = timecode_data_cache[60] ^ timecode_data_cache[61]; - timecode_bit_cache[31] = timecode_data_cache[62] ^ timecode_data_cache[63]; - timecode_bit_cache[32] = timecode_data_cache[64] ^ timecode_data_cache[65]; - timecode_bit_cache[33] = timecode_data_cache[66] ^ timecode_data_cache[67]; - timecode_bit_cache[34] = timecode_data_cache[68] ^ timecode_data_cache[69]; - timecode_bit_cache[35] = timecode_data_cache[70] ^ timecode_data_cache[71]; - timecode_bit_cache[36] = timecode_data_cache[72] ^ timecode_data_cache[73]; - timecode_bit_cache[37] = timecode_data_cache[74] ^ timecode_data_cache[75]; - timecode_bit_cache[38] = timecode_data_cache[76] ^ timecode_data_cache[77]; - timecode_bit_cache[39] = timecode_data_cache[78] ^ timecode_data_cache[79]; - timecode_bit_cache[40] = timecode_data_cache[80] ^ timecode_data_cache[81]; - timecode_bit_cache[41] = timecode_data_cache[82] ^ timecode_data_cache[83]; - timecode_bit_cache[42] = timecode_data_cache[84] ^ timecode_data_cache[85]; - timecode_bit_cache[43] = timecode_data_cache[86] ^ timecode_data_cache[87]; - timecode_bit_cache[44] = timecode_data_cache[88] ^ timecode_data_cache[89]; - timecode_bit_cache[45] = timecode_data_cache[90] ^ timecode_data_cache[91]; - timecode_bit_cache[46] = timecode_data_cache[92] ^ timecode_data_cache[93]; - timecode_bit_cache[47] = timecode_data_cache[94] ^ timecode_data_cache[95]; - timecode_bit_cache[48] = timecode_data_cache[96] ^ timecode_data_cache[97]; - timecode_bit_cache[49] = timecode_data_cache[98] ^ timecode_data_cache[99]; - timecode_bit_cache[50] = timecode_data_cache[100] ^ timecode_data_cache[101]; - timecode_bit_cache[51] = timecode_data_cache[102] ^ timecode_data_cache[103]; - timecode_bit_cache[52] = timecode_data_cache[104] ^ timecode_data_cache[105]; - timecode_bit_cache[53] = timecode_data_cache[106] ^ timecode_data_cache[107]; - timecode_bit_cache[54] = timecode_data_cache[108] ^ timecode_data_cache[109]; - timecode_bit_cache[55] = timecode_data_cache[110] ^ timecode_data_cache[111]; - timecode_bit_cache[56] = timecode_data_cache[112] ^ timecode_data_cache[113]; - timecode_bit_cache[57] = timecode_data_cache[114] ^ timecode_data_cache[115]; - timecode_bit_cache[58] = timecode_data_cache[116] ^ timecode_data_cache[117]; - timecode_bit_cache[59] = timecode_data_cache[118] ^ timecode_data_cache[119]; - timecode_bit_cache[60] = timecode_data_cache[120] ^ timecode_data_cache[121]; - timecode_bit_cache[61] = timecode_data_cache[122] ^ timecode_data_cache[123]; - timecode_bit_cache[62] = timecode_data_cache[124] ^ timecode_data_cache[125]; - timecode_bit_cache[63] = timecode_data_cache[126] ^ timecode_data_cache[127]; - timecode_bit_cache[64] = timecode_data_cache[128] ^ timecode_data_cache[129]; - timecode_bit_cache[65] = timecode_data_cache[130] ^ timecode_data_cache[131]; - timecode_bit_cache[66] = timecode_data_cache[132] ^ timecode_data_cache[133]; - timecode_bit_cache[67] = timecode_data_cache[134] ^ timecode_data_cache[135]; - timecode_bit_cache[68] = timecode_data_cache[136] ^ timecode_data_cache[137]; - timecode_bit_cache[69] = timecode_data_cache[138] ^ timecode_data_cache[139]; - timecode_bit_cache[70] = timecode_data_cache[140] ^ timecode_data_cache[141]; - timecode_bit_cache[71] = timecode_data_cache[142] ^ timecode_data_cache[143]; - timecode_bit_cache[72] = timecode_data_cache[144] ^ timecode_data_cache[145]; - timecode_bit_cache[73] = timecode_data_cache[146] ^ timecode_data_cache[147]; - timecode_bit_cache[74] = timecode_data_cache[148] ^ timecode_data_cache[149]; - timecode_bit_cache[75] = timecode_data_cache[150] ^ timecode_data_cache[151]; - timecode_bit_cache[76] = timecode_data_cache[152] ^ timecode_data_cache[153]; - timecode_bit_cache[77] = timecode_data_cache[154] ^ timecode_data_cache[155]; - timecode_bit_cache[78] = timecode_data_cache[156] ^ timecode_data_cache[157]; - timecode_bit_cache[79] = timecode_data_cache[158] ^ timecode_data_cache[159]; - end - - // 识别信号捕获 - wire [15:0] synccode; - assign synccode = timecode_bit_cache[79:64]; - assign detect_sync_code = (synccode == 16'b1011_1111_1111_1100); - - - wire detect_sync_code_sig; - zutils_edge_detecter detect_sync_code_detect ( - .clk(clk), - .rst_n(rst_n), - .in_signal(detect_sync_code), - .in_signal_rising_edge(detect_sync_code_sig) - ); - - //输出时码识别信号 - - always @(posedge clk or negedge rst_n) begin - if (!rst_n) begin - timecode_tigger_sig <= 0; - timecode_data <= 0; - end else begin - if (detect_sync_code_sig) begin - timecode_tigger_sig <= 1; - timecode_data <= timecode_bit_cache[63:0]; - end else begin - timecode_tigger_sig <= 0; - end - end - end - -endmodule diff --git a/source/src/timecode/timecode_generator.v b/source/src/timecode/timecode_generator.v deleted file mode 100644 index f3caf30..0000000 --- a/source/src/timecode/timecode_generator.v +++ /dev/null @@ -1,115 +0,0 @@ - -module timecode_generator #( - parameter SYS_CLOCK_FREQ = 100000000 -) ( - input clk, //clock input - input rst_n, //asynchronous reset input, low active - - input [31:0] timecode_format, //!timecode格式 - - input timecode0_wen, //!timecode[0:31]写信号 - input [31:0] timecode0, //!timecode[0:31]写数据 - output [31:0] timecode0_export, //!timecode[0:31]输出 - input timecode1_wen, //!timecode[32:63]写信号 - input [31:0] timecode1, //!timecode[32:63]写数据 - output [31:0] timecode1_export, //!timecode[32:63]输出 - - input en, //!使能信号,只有在失能的情况才能修改timecode - - output wire out_timecode_serial_data, - output wire out_trigger_sig, - output wire [31:0] out_timecode0, - output wire [31:0] out_timecode1 -); - - // - - - - wire [7:0] out_frame_num; - wire out_drop_frame; - - wire frame_trigger_sig; - wire first_frame_sig; - - - timecode_basesig_generator #( - .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ) - ) basesig_generator ( - .clk (clk), - .rst_n (rst_n), - .timecode_format (timecode_format), - .en (en), - .out_timecode_trigger_sig(frame_trigger_sig), //帧时钟触发信号 - .out_first_frame_sig (first_frame_sig), - .out_frame_num (out_frame_num), - .out_drop_frame (out_drop_frame) - ); - - reg [63:0] timecode; - wire [63:0] timecode_next; - timecode_nextcode nextcode ( - .frame_mum (out_frame_num), - .drop (out_drop_frame), - .timecode (timecode), - .timecode_next(timecode_next) - ); - - reg timecode_trigger_sig; - always @(posedge clk or negedge rst_n) begin - if (!rst_n) begin - timecode <= 0; - timecode_trigger_sig <= 0; - - end else begin - if (!en) begin - if (timecode0_wen || timecode1_wen) begin - if (timecode0_wen) begin - timecode[31:0] <= timecode0; - end - if (timecode1_wen) begin - timecode[63:32] <= timecode1; - end - end - end else begin - if (frame_trigger_sig) begin - if (!first_frame_sig) begin - timecode <= timecode_next; - end - timecode_trigger_sig <= 1; - end else begin - timecode_trigger_sig <= 0; - end - end - - - end - end - - assign timecode0_export = timecode[31:0]; - assign timecode1_export = timecode[63:32]; - - - wire [63:0] out_timecode; - timecode_serialization #( - .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ) - ) serialization ( - .clk (clk), - .rst_n (rst_n), - .timecode_format(timecode_format), - - .trigger_sig(timecode_trigger_sig), - .timecode (timecode), - - .out_timecode_serial_data(out_timecode_serial_data), - .out_trigger_sig (out_trigger_sig), - .out_timecode (out_timecode) - ); - - // out_timecode0 - // out_timecode1 - - assign out_timecode0 = out_timecode[31:0]; - assign out_timecode1 = out_timecode[63:32]; - -endmodule diff --git a/source/src/timecode/timecode_nextcode.v b/source/src/timecode/timecode_nextcode.v deleted file mode 100644 index 957c987..0000000 --- a/source/src/timecode/timecode_nextcode.v +++ /dev/null @@ -1,353 +0,0 @@ -module timecode_nextcode ( - input [63:0] timecode, - input [7:0] frame_mum, - input drop, - output [63:0] timecode_next -); - wire [7:0] now_frame_units; - wire [7:0] frame10; - wire [7:0] sec; - wire [7:0] sec10; - wire [7:0] min; - wire [7:0] min10; - wire [7:0] hour; - wire [7:0] hour10; - - assign now_frame_units = timecode[7:0] & 8'b0000_1111; - assign frame10 = timecode[15:8] & 8'b0000_0011; - assign sec = timecode[23:16]& 8'b0000_1111; - assign sec10 = timecode[31:24]& 8'b0000_0111; - assign min = timecode[39:32]& 8'b0000_1111; - assign min10 = timecode[47:40]& 8'b0000_0111; - assign hour = timecode[55:48]& 8'b0000_1111; - assign hour10 = timecode[63:56]& 8'b0000_0011; - - wire houris23 = (hour10 == 2) && (hour == 3); - wire houris19 = (hour10 == 1) && (hour == 9); - wire houris09 = (hour10 == 0) && (hour == 9); - - wire minis59 = (min10 == 5) && (min == 9); - wire minis49 = (min10 == 4) && (min == 9); - wire minis39 = (min10 == 3) && (min == 9); - wire minis29 = (min10 == 2) && (min == 9); - wire minis19 = (min10 == 1) && (min == 9); - wire minis09 = (min10 == 0) && (min == 9); - - wire secis59 = (sec10 == 5) && (sec == 9); - wire secis49 = (sec10 == 4) && (sec == 9); - wire secis39 = (sec10 == 3) && (sec == 9); - wire secis29 = (sec10 == 2) && (sec == 9); - wire secis19 = (sec10 == 1) && (sec == 9); - wire secis09 = (sec10 == 0) && (sec == 9); - - wire frameisfinal = (frame10 == 2) && (now_frame_units == (frame_mum - 20 - 1)); - wire frameis19 = (frame10 == 1) && (now_frame_units == 9); - wire frameis09 = (frame10 == 0) && (now_frame_units == 9); - - // reg [63:0] next_frame; - - reg [63:0] next_frame; - wire [7:0] n_10hour; - wire [7:0] n_hour; - wire [7:0] n_10min; - wire [7:0] n_min; - wire [7:0] n_10sec; - wire [7:0] n_sec; - wire [7:0] n_10frame; - wire [7:0] n_frame; - assign n_10hour[7:0] = next_frame[63:56]; - assign n_hour[7:0] = next_frame[55:48]; - assign n_10min[7:0] = next_frame[47:40]; - assign n_min[7:0] = next_frame[39:32]; - assign n_10sec[7:0] = next_frame[31:24]; - assign n_sec[7:0] = next_frame[23:16]; - assign n_10frame[7:0] = next_frame[15:8]; - assign n_frame[7:0] = next_frame[7:0]; - - - - function [63:0] assign_timecode; - input [7:0] hour_tens; - input [7:0] hour_units; - input [7:0] min_tens; - input [7:0] min_units; - input [7:0] sec_tens; - input [7:0] sec_units; - input [7:0] frame_tens; - input [7:0] frame_units; - begin - assign_timecode[7:0] = frame_units; - assign_timecode[15:8] = frame_tens; - assign_timecode[23:16] = sec_units; - assign_timecode[31:24] = sec_tens; - assign_timecode[39:32] = min_units; - assign_timecode[47:40] = min_tens; - assign_timecode[55:48] = hour_units; - assign_timecode[63:56] = hour_tens; - end - - endfunction - - - - - always @(*) begin - /******************************************************************************* - * HOUR * - *******************************************************************************/ - if (houris23 && minis59 && secis59 && frameisfinal) begin //23:59:59:29 - next_frame <= assign_timecode(0, 0, 0, 0, 0, 0, 0, 0); - end else if (houris19 && minis59 && secis59 && frameisfinal) begin //19:59:59:29 - next_frame <= assign_timecode(2, 0, 0, 0, 0, 0, 0, 0); - end else if (houris09 && minis59 && secis59 && frameisfinal) begin //09:59:59:29 - next_frame <= assign_timecode(1, 0, 0, 0, 0, 0, 0, 0); - end else if (minis59 && secis59 && frameisfinal) begin //xx:59:59:29 - next_frame <= assign_timecode(hour10, hour + 1, 0, 0, 0, 0, 0, 0); - end - /******************************************************************************* - * MIN * - *******************************************************************************/ - else if (minis49 && secis59 && frameisfinal) begin // xx:49:59:29 - next_frame <= assign_timecode(hour10, hour, 5, 0, 0, 0, 0, 0); - end else if (minis39 && secis59 && frameisfinal) begin // xx:39:59:29 - next_frame <= assign_timecode(hour10, hour, 4, 0, 0, 0, 0, 0); - end else if (minis29 && secis59 && frameisfinal) begin // xx:29:59:29 - next_frame <= assign_timecode(hour10, hour, 3, 0, 0, 0, 0, 0); - end else if (minis19 && secis59 && frameisfinal) begin // xx:19:59:29 - next_frame <= assign_timecode(hour10, hour, 2, 0, 0, 0, 0, 0); - end else if (minis09 && secis59 && frameisfinal) begin // xx:09:59:29 - next_frame <= assign_timecode(hour10, hour, 1, 0, 0, 0, 0, 0); - end else if (secis59 && frameisfinal) begin // xx:xx:59:29 - if (drop) begin - next_frame <= assign_timecode(hour10, hour, min10, min + 1, 0, 0, 0, 2); - end else begin - next_frame <= assign_timecode(hour10, hour, min10, min + 1, 0, 0, 0, 0); - end - end - /******************************************************************************* - * SECOND * - *******************************************************************************/ - else if (secis49 && frameisfinal) begin // xx:xx:49:29 - next_frame <= assign_timecode(hour10, hour, min10, min, 5, 0, 0, 0); - end else if (secis39 && frameisfinal) begin // xx:xx:39:29 - next_frame <= assign_timecode(hour10, hour, min10, min, 4, 0, 0, 0); - end else if (secis29 && frameisfinal) begin // xx:xx:29:29 - next_frame <= assign_timecode(hour10, hour, min10, min, 3, 0, 0, 0); - end else if (secis19 && frameisfinal) begin // xx:xx:19:29 - next_frame <= assign_timecode(hour10, hour, min10, min, 2, 0, 0, 0); - end else if (secis09 && frameisfinal) begin // xx:xx:09:29 - next_frame <= assign_timecode(hour10, hour, min10, min, 1, 0, 0, 0); - end else if (frameisfinal) begin // xx:xx:xx:29 - next_frame <= assign_timecode(hour10, hour, min10, min, sec10, sec + 1, 0, 0); - end - /******************************************************************************* - * FRAME * - *******************************************************************************/ - else if (frameis19) begin // xx:xx:xx:19 - next_frame <= assign_timecode(hour10, hour, min10, min, sec10, sec, 2, 0); - end else if (frameis09) begin // xx:xx:xx:09 - next_frame <= assign_timecode(hour10, hour, min10, min, sec10, sec, 1, 0); - end else begin - next_frame <= - assign_timecode(hour10, hour, min10, min, sec10, sec, frame10, now_frame_units + 1); - end - end - assign timecode_next = next_frame; - - - // always @(*) begin - // /******************************************************************************* - // * HOUR * - // *******************************************************************************/ - // if (houris23 && minis59 && secis59 && frameisfinal) begin //23:59:59:29 - // n_10hour <= 0; - // n_hour <= 0; - // n_10min <= 0; - // n_min <= 0; - // n_10sec <= 0; - // n_sec <= 0; - // n_10frame <= 0; - // n_frame <= 0; - // end else if (houris19 && minis59 && secis59 && frameisfinal) begin //19:59:59:29 - // n_10hour <= 2; - // n_hour <= 0; - // n_10min <= 0; - // n_min <= 0; - // n_10sec <= 0; - // n_sec <= 0; - // n_10frame <= 0; - // n_frame <= 0; - // end else if (houris09 && minis59 && secis59 && frameisfinal) begin //09:59:59:29 - // n_10hour <= 1; - // n_hour <= 0; - // n_10min <= 0; - // n_min <= 0; - // n_10sec <= 0; - // n_sec <= 0; - // n_10frame <= 0; - // n_frame <= 0; - // end else if (minis59 && secis59 && frameisfinal) begin //xx:59:59:29 - // n_10hour <= hour10; - // n_hour <= hour + 1; - // n_10min <= 0; - // n_min <= 0; - // n_10sec <= 0; - // n_sec <= 0; - // n_10frame <= 0; - // n_frame <= 0; - // end /******************************************************************************* - // * MIN * - // *******************************************************************************/ - // else if (minis49 && secis59 && frameisfinal) begin // xx:49:59:29 - // n_10hour <= hour10; - // n_hour <= hour; - // n_10min <= 5; - // n_min <= 0; - // n_10sec <= 0; - // n_sec <= 0; - // n_10frame <= 0; - // n_frame <= 0; - // end else if (minis39 && secis59 && frameisfinal) begin // xx:39:59:29 - // n_10hour <= hour10; - // n_hour <= hour; - // n_10min <= 4; - // n_min <= 0; - // n_10sec <= 0; - // n_sec <= 0; - // n_10frame <= 0; - // n_frame <= 0; - // end else if (minis29 && secis59 && frameisfinal) begin // xx:29:59:29 - // n_10hour <= hour10; - // n_hour <= hour; - // n_10min <= 3; - // n_min <= 0; - // n_10sec <= 0; - // n_sec <= 0; - // n_10frame <= 0; - // n_frame <= 0; - // end else if (minis19 && secis59 && frameisfinal) begin // xx:19:59:29 - // n_10hour <= hour10; - // n_hour <= hour; - // n_10min <= 2; - // n_min <= 0; - // n_10sec <= 0; - // n_sec <= 0; - // n_10frame <= 0; - // n_frame <= 0; - // end else if (minis09 && secis59 && frameisfinal) begin // xx:09:59:29 - // n_10hour <= hour10; - // n_hour <= hour; - // n_10min <= 1; - // n_min <= 0; - // n_10sec <= 0; - // n_sec <= 0; - // n_10frame <= 0; - // n_frame <= 0; - // end /******************************************************************************* - // * SECOND * - // *******************************************************************************/ - // else if (secis49 && frameisfinal) begin // xx:xx:49:29 - // n_10hour <= hour10; - // n_hour <= hour; - // n_10min <= min10; - // n_min <= min; - // n_10sec <= 5; - // n_sec <= 0; - // n_10frame <= 0; - // n_frame <= 0; - // end else if (secis39 && frameisfinal) begin // xx:xx:39:29 - // n_10hour <= hour10; - // n_hour <= hour; - // n_10min <= min10; - // n_min <= min; - // n_10sec <= 4; - // n_sec <= 0; - // n_10frame <= 0; - // n_frame <= 0; - // end else if (secis29 && frameisfinal) begin // xx:xx:29:29 - // n_10hour <= hour10; - // n_hour <= hour; - // n_10min <= min10; - // n_min <= min; - // n_10sec <= 3; - // n_sec <= 0; - // n_10frame <= 0; - // n_frame <= 0; - // end else if (secis19 && frameisfinal) begin // xx:xx:19:29 - // n_10hour <= hour10; - // n_hour <= hour; - // n_10min <= min10; - // n_min <= min; - // n_10sec <= 2; - // n_sec <= 0; - // n_10frame <= 0; - // n_frame <= 0; - // end else if (secis09 && frameisfinal) begin // xx:xx:09:29 - // n_10hour <= hour10; - // n_hour <= hour; - // n_10min <= min10; - // n_min <= min; - // n_10sec <= 1; - // n_sec <= 0; - // n_10frame <= 0; - // n_frame <= 0; - // end else if (frameisfinal) begin // xx:xx:xx:29 - // n_10hour <= hour10; - // n_hour <= hour; - // n_10min <= min10; - // n_min <= min; - // n_10sec <= sec10; - // n_sec <= sec; - // n_10frame <= 0; - // n_frame <= 0; - // end /******************************************************************************* - // * FRAME * - // *******************************************************************************/ - // else if (frameis19) begin // xx:xx:xx:19 - // n_10hour <= hour10; - // n_hour <= hour; - // n_10min <= min10; - // n_min <= min; - // n_10sec <= sec10; - // n_sec <= sec; - // n_10frame <= 2; - // n_frame <= 0; - // end else - // if (frameis09) begin // xx:xx:xx:09 - // n_10hour <= hour10; - // n_hour <= hour; - // n_10min <= min10; - // n_min <= min; - // n_10sec <= sec10; - // n_sec <= sec; - // n_10frame <= 1; - // n_frame <= 0; - // end else begin - // n_10hour <= hour10; - // n_hour <= hour; - // n_10min <= min10; - // n_min <= min; - // n_10sec <= sec10; - // n_sec <= sec; - // n_10frame <= frame10; - // n_frame <= now_frame_units + 1; - // end - // end - // assign timecode_next = next_frame; - - // assign timecode_next[7:0] = n_frame; - // assign timecode_next[15:8] = n_10frame; - // assign timecode_next[23:16] = n_sec; - // assign timecode_next[31:24] = n_10sec; - // assign timecode_next[39:32] = n_min; - // assign timecode_next[47:40] = n_10min; - // assign timecode_next[55:48] = n_hour; - // assign timecode_next[63:56] = n_10hour; - - - // wire [63:0] tmp_timecode_next; - // assign tmp_timecode_next = timecode + 1; - // assign timecode_next = tmp_timecode_next; - - -endmodule diff --git a/source/src/timecode/timecode_sample_sig_generator.v b/source/src/timecode/timecode_sample_sig_generator.v deleted file mode 100644 index c37c6bd..0000000 --- a/source/src/timecode/timecode_sample_sig_generator.v +++ /dev/null @@ -1,53 +0,0 @@ -module timecode_sample_sig_generator #( - parameter SYS_CLOCK_FREQ = 100000000, - parameter SAMPLE_RATE = 8547 -) ( - input clk, //clock input - input rst_n, //asynchronous reset input, low active - - output reg sample_sig -); - - - // - // sampleSig ______|____________|____________|____________| - // - - localparam COUNT = (SYS_CLOCK_FREQ * 100) / SAMPLE_RATE; - reg [31:0] counter; - reg [1:0] sub_counter; - - wire counter_clear; - always @(posedge clk or negedge rst_n) begin - if (!rst_n) begin - counter <= 0; - sub_counter <= 1; - end else begin - - if (counter == COUNT) begin - counter <= 0; - - if (sub_counter == 1) begin - sample_sig <= 1; - sub_counter <= 0; - end else begin - sub_counter <= 1; - end - - end else begin - counter <= counter + 1; - sample_sig <= 0; - end - - end - end - - - - - - - - - -endmodule diff --git a/source/src/timecode/timecode_serialization.v b/source/src/timecode/timecode_serialization.v deleted file mode 100644 index 92136fb..0000000 --- a/source/src/timecode/timecode_serialization.v +++ /dev/null @@ -1,262 +0,0 @@ - -module timecode_serialization #( - parameter SYS_CLOCK_FREQ = 100000000 -) ( - input clk, - input rst_n, - - input [31:0] timecode_format, - - input trigger_sig, - - input [63:0] timecode, - - output reg out_timecode_serial_data, - output reg out_trigger_sig, - output reg [63:0] out_timecode -); - - // Rate 1/2Fe 1Fe - // 23.98 F/s 260.7 us 521.4 us - // 24.00 F/s 260.4 us 520.8 us - // 25.00 F/s 250.0 us 500.0 us - // 29.97 F/s 208.5 us 417.1 us - // 30.00 F/s 208.3 us 416.7 us - - localparam FPS2398Format = 0; - localparam FPS2400Format = 1; - localparam FPS2500Format = 2; - localparam FPS2997Format = 3; - localparam FPS2997DropFormat = 4; - localparam FPS3000Format = 5; - - localparam FPS2398FormatOneHalfFe = (260.7 * 1000) / (1000000000 / SYS_CLOCK_FREQ); - localparam FPS2400FormatOneHalfFe = (260.4 * 1000) / (1000000000 / SYS_CLOCK_FREQ); - localparam FPS2500FormatOneHalfFe = (250.0 * 1000) / (1000000000 / SYS_CLOCK_FREQ); - localparam FPS2997FormatOneHalfFe = (208.5 * 1000) / (1000000000 / SYS_CLOCK_FREQ); - localparam FPS2997DropFormatOneHalfFe = (208.5 * 1000) / (1000000000 / SYS_CLOCK_FREQ); - localparam FPS3000FormatOneHalfFe = (208.3 * 1000) / (1000000000 / SYS_CLOCK_FREQ); - - reg [31:0] timecode_onehalf_bit_count; - always @(*) begin - case (timecode_format) - FPS2398Format: timecode_onehalf_bit_count = FPS2398FormatOneHalfFe; - FPS2400Format: timecode_onehalf_bit_count = FPS2400FormatOneHalfFe; - FPS2500Format: timecode_onehalf_bit_count = FPS2500FormatOneHalfFe; - FPS2997Format: timecode_onehalf_bit_count = FPS2997FormatOneHalfFe; - FPS2997DropFormat: timecode_onehalf_bit_count = FPS2997DropFormatOneHalfFe; - FPS3000Format: timecode_onehalf_bit_count = FPS3000FormatOneHalfFe; - default: timecode_onehalf_bit_count = FPS2398FormatOneHalfFe; - endcase - end - - reg [31:0] oneframe_timeout_count; - always @(*) begin - case (timecode_format) - FPS2398Format: oneframe_timeout_count = FPS2398FormatOneHalfFe * 2 * 80; - FPS2400Format: oneframe_timeout_count = FPS2400FormatOneHalfFe * 2 * 80; - FPS2500Format: oneframe_timeout_count = FPS2500FormatOneHalfFe * 2 * 80; - FPS2997Format: oneframe_timeout_count = FPS2997FormatOneHalfFe * 2 * 80; - FPS2997DropFormat: oneframe_timeout_count = FPS2997DropFormatOneHalfFe * 2 * 80; - FPS3000Format: oneframe_timeout_count = FPS3000FormatOneHalfFe * 2 * 80; - default: oneframe_timeout_count = FPS2398FormatOneHalfFe * 2 * 80; - endcase - end - - /******************************************************************************* - * workflag * - *******************************************************************************/ - - localparam START_CTRL_SIG = 1; - localparam STOP_CTRL_SIG = 2; - localparam RESTART_CTRL_SIG = 3; - localparam NULL_CTRL_SIG = 0; - - reg [31:0] oneframe_timeout_counter; - reg [1:0] internal_ctrl_sig; - reg startflag; - - always @(posedge clk or negedge rst_n) begin - if (!rst_n) begin - oneframe_timeout_counter <= 0; - startflag <= 0; - internal_ctrl_sig <= NULL_CTRL_SIG; - end else begin - if (trigger_sig && startflag) begin // 重启 - oneframe_timeout_counter <= oneframe_timeout_count; - internal_ctrl_sig <= RESTART_CTRL_SIG; - startflag <= 1; - end else if (trigger_sig && !startflag) begin //启动 - oneframe_timeout_counter <= oneframe_timeout_count; - internal_ctrl_sig <= START_CTRL_SIG; - startflag <= 1; - end else if (!trigger_sig && startflag && oneframe_timeout_counter == 0) begin //停止 - internal_ctrl_sig <= STOP_CTRL_SIG; - startflag <= 0; - end else begin - if (oneframe_timeout_counter != 0) begin - oneframe_timeout_counter <= oneframe_timeout_counter - 1; - end - internal_ctrl_sig <= NULL_CTRL_SIG; - end - end - end - - - reg [79:0] in_timecode_cache; - always @(posedge clk or negedge rst_n) begin - if (!rst_n) begin - in_timecode_cache <= 0; - end else begin - case (internal_ctrl_sig) - START_CTRL_SIG, RESTART_CTRL_SIG: begin - in_timecode_cache[63:0] <= timecode; - in_timecode_cache[79:64] <= 16'b1011_1111_1111_1100; - end - STOP_CTRL_SIG: begin - end - default: begin - end - endcase - end - end - - - // - // trigger : | | | | | - // onebitoff: 0000000001111111111000000001111111110000000001 - // bitoff : 0000000000000000000111111111111111112222222222 - // - // - - // bit trigger sig gen - reg [31:0] halfbitcount; - reg bit_tigger_sig; - always @(posedge clk or negedge rst_n) begin - if (!rst_n) begin - halfbitcount <= 0; - bit_tigger_sig <= 0; - end else begin - - case (internal_ctrl_sig) - START_CTRL_SIG, RESTART_CTRL_SIG: begin - halfbitcount <= 0; - bit_tigger_sig <= 0; - end - STOP_CTRL_SIG: begin - halfbitcount <= 0; - bit_tigger_sig <= 0; - end - default: begin - if (halfbitcount == timecode_onehalf_bit_count) begin - halfbitcount <= 0; - bit_tigger_sig <= 1; - end else begin - halfbitcount <= halfbitcount + 1; - bit_tigger_sig <= 0; - end - end - endcase - end - end - - // 偏移 - reg [ 1:0] onebitoff; - reg [31:0] bitoff; - always @(posedge clk or negedge rst_n) begin - if (!rst_n) begin - onebitoff <= 0; - bitoff <= 0; - end else begin - case (internal_ctrl_sig) - START_CTRL_SIG, RESTART_CTRL_SIG: begin - onebitoff <= 0; - bitoff <= 0; - end - STOP_CTRL_SIG: begin - onebitoff <= 0; - bitoff <= 0; - end - default: begin - if (bit_tigger_sig) begin - if (onebitoff == 1) begin - if (bitoff < 79) begin - bitoff <= bitoff + 1; - end - onebitoff <= 0; - end else begin - onebitoff <= 1; - end - end - end - endcase - - end - end - - // 时码输出 - always @(posedge clk or negedge rst_n) begin - if (!rst_n) begin - out_timecode_serial_data <= 0; - end else begin - - case (internal_ctrl_sig) - /******************************************************************************* - * 启动 * - *******************************************************************************/ - START_CTRL_SIG: begin - out_timecode_serial_data <= ~out_timecode_serial_data; - end - /******************************************************************************* - * 重启 * - *******************************************************************************/ - RESTART_CTRL_SIG: begin - out_timecode_serial_data <= ~out_timecode_serial_data; - end - /******************************************************************************* - * 停止 * - *******************************************************************************/ - STOP_CTRL_SIG: begin - out_timecode_serial_data <= out_timecode_serial_data; - - end - default: begin - if (bit_tigger_sig) begin - if (onebitoff == 1) begin - out_timecode_serial_data <= ~out_timecode_serial_data; - end else begin - if (in_timecode_cache[bitoff] == 1) begin - out_timecode_serial_data <= ~out_timecode_serial_data; - end else begin - out_timecode_serial_data <= out_timecode_serial_data; - end - end - end - - end - endcase - end - end - - // out_trigger_sig - // out_timecode - - always @(posedge clk or negedge rst_n) begin - if (!rst_n) begin - out_trigger_sig <= 0; - out_timecode <= 0; - end else begin - case (internal_ctrl_sig) - RESTART_CTRL_SIG, STOP_CTRL_SIG: begin - out_timecode <= in_timecode_cache[63:0]; - out_trigger_sig <= 1; - end - default: begin - out_trigger_sig <= 0; - end - endcase - end - end - - -endmodule diff --git a/source/src/top.bak.v b/source/src/top.bak.v deleted file mode 100644 index ab86177..0000000 --- a/source/src/top.bak.v +++ /dev/null @@ -1,645 +0,0 @@ -`timescale 1ns / 1ns -module Top ( - input ex_clk, - input ex_rst_n, - - /******************************************************************************* - * genlock * - *******************************************************************************/ - input genlock_in_hsync, - input genlock_in_vsync, - input genlock_in_fsync, - output genlock_in_state_led, - - /******************************************************************************* - * GENLOCK_OUTPUT * - *******************************************************************************/ - - output [9:0] genlock_out_dac, - output genlock_out_dac_clk, - output genlock_out_dac_state_led, - - /******************************************************************************* - * TTL_IN * - *******************************************************************************/ - - input sync_ttl_in1, - output sync_ttl_in1_state_led, - - input sync_ttl_in2, - output sync_ttl_in2_state_led, - - input sync_ttl_in3, - output sync_ttl_in3_state_led, - - input sync_ttl_in4, - output sync_ttl_in4_state_led, - - - /******************************************************************************* - * TTL_OUT * - *******************************************************************************/ - - output sync_ttl_out1, - output sync_ttl_out1_state_led, - - output sync_ttl_out2, - output sync_ttl_out2_state_led, - - output sync_ttl_out3, - output sync_ttl_out3_state_led, - - output sync_ttl_out4, - output sync_ttl_out4_state_led, - - /******************************************************************************* - * TIMECODE_IN * - *******************************************************************************/ - input timecode_headphone_in, - output timecode_headphone_in_state_led, - input timecode_bnc_in, - output timecode_bnc_in_state_led, - - /******************************************************************************* - * TIMECODE_OUTPUT * - *******************************************************************************/ - - output timecode_out_bnc, - output timecode_out_bnc_select, - output timecode_out_bnc_state_led, - - output timecode_out_headphone, - output timecode_out_headphone_select, - output timecode_out_headphone_state_led, - - /******************************************************************************* - * STM32_IF * - *******************************************************************************/ - - output stm32if_start_signal_out, - output stm32if_camera_sync_out, - output stm32if_timecode_sync_out, - - //SPI 串行总线1 - input wire spi1_cs_pin, - input wire spi1_clk_pin, - input wire spi1_rx_pin, - output wire spi1_tx_pin, - - //SPI 串行总线2 - input wire spi2_cs_pin, - input wire spi2_clk_pin, - input wire spi2_rx_pin, - output wire spi2_tx_pin, - - /******************************************************************************* - * debug_signal_output * - *******************************************************************************/ - output [15:0] debug_signal_output, - - /******************************************************************************* - * CODE_BOARD * - *******************************************************************************/ - output wire core_board_debug_led -); - - localparam HARDWARE_TEST_MODE = 1; - //STM32寄存器地址 - localparam REG_ADD_OFF_STM32 = 16'h0000; - localparam REG_ADD_OFF_FPGA_TEST = 16'h00020; - //控制中心寄存器地址 - localparam REG_ADD_OFF_XSYNC_INTERNAL_SIG_GENERATOR = 16'h00030; // 48 - //输入组件 - localparam REG_ADD_OFF_TTLIN1 = 16'h0100; - localparam REG_ADD_OFF_TTLIN2 = 16'h0110; - localparam REG_ADD_OFF_TTLIN3 = 16'h0120; - localparam REG_ADD_OFF_TTLIN4 = 16'h0130; - localparam REG_ADD_OFF_TIMECODE_IN = 16'h0140; - localparam REG_ADD_OFF_GENLOCK_IN = 16'h0150; - //输出组件 - localparam REG_ADD_OFF_TTLOUT1 = 16'h0200; - localparam REG_ADD_OFF_TTLOUT2 = 16'h0210; - localparam REG_ADD_OFF_TTLOUT3 = 16'h0220; - localparam REG_ADD_OFF_TTLOUT4 = 16'h0230; - localparam REG_ADD_OFF_TIMECODE_OUT = 16'h0240; - localparam REG_ADD_OFF_GENLOCK_OUT = 16'h0250; - localparam REG_ADD_OFF_CAMERA_SYNC_OUT = 16'h0260; - //调试组件 - localparam REG_ADD_OFF_DEBUGER = 16'h0300; - - SPLL spll ( - .clkin1(ex_clk), // input - .pll_lock(pll_lock), // output - .clkout0(sys_clk_25m), // output - .clkout1(sys_clk_10m), // output - .clkout2(sys_clk_5m) // output - ); - assign sys_clk = sys_clk_10m; - assign sys_rst_n = ex_rst_n & pll_lock; - localparam SYS_CLOCK_FREQ = 10000000; - - // zutils_reset_sig_gen reset_sig_gen_inst ( - // .clk(sys_clk), - // .rst_n(rst_n), - // .rst_n_out(sys_rst_n) - // ); - - - /******************************************************************************* - * DEBUG_LED * - *******************************************************************************/ - // zutils_debug_led #( - // .PERIOD_COUNT(10000000) - // ) core_board_debug_led_inst ( - // .clk(sys_clk), - // .rst_n(sys_rst_n), - // .debug_led(core_board_debug_led) - // ); - - /******************************************************************************* - * SPIREADER * - *******************************************************************************/ - - wire [31:0] reg_reader_bus_addr; - wire [31:0] reg_reader_bus_wr_data; - wire reg_reader_bus_wr_en; - wire [31:0] reg_reader_bus_rd_data; - spi_reg_reader spi_reg_reader_inst ( - .clk (sys_clk), - .rst_n(sys_rst_n), - - .addr(reg_reader_bus_addr), - .wr_data(reg_reader_bus_wr_data), - .wr_en(reg_reader_bus_wr_en), - .rd_data(reg_reader_bus_rd_data), - // - .spi_cs_pin(spi2_cs_pin), - .spi_clk_pin(spi2_clk_pin), - .spi_rx_pin(spi2_rx_pin), - .spi_tx_pin(spi2_tx_pin) - ); - - wire [31:0] stm32_rd_data; // - wire [31:0] fpga_test_rd_data; // - wire [31:0] xsync_internal_sig_generator_rd_data; - wire [31:0] ttlin1_rd_data; - wire [31:0] ttlin2_rd_data; - wire [31:0] ttlin3_rd_data; - wire [31:0] ttlin4_rd_data; - wire [31:0] timecode_in_rd_data; - wire [31:0] genlock_in_rd_data; - wire [31:0] ttlout1_rd_data; - wire [31:0] ttlout2_rd_data; - wire [31:0] ttlout3_rd_data; - wire [31:0] ttlout4_rd_data; - wire [31:0] timecode_out_rd_data; - wire [31:0] genlock_out_rd_data; - wire [31:0] camera_sync_out_rd_data; - wire [31:0] debuger_rd_data; - - // - - - /******************************************************************************* - * TEST_SPI_REG * - *******************************************************************************/ - zutils_register16 #( - .REG_START_ADD(REG_ADD_OFF_FPGA_TEST), - .REG0_INIT(31'h0000_0000_0000_0001), - .REG1_INIT(31'h0000_0000_0000_0010), - .REG2_INIT(31'h0000_0000_0000_0100), - .REG3_INIT(31'h0000_0000_0000_1000), - .REG4_INIT(31'h0000_0000_0001_0000), - .REG5_INIT(31'h0000_0000_0010_0000), - .REG6_INIT(31'h0000_0000_0100_0000), - .REG7_INIT(31'h0000_0000_1000_0000), - .REG8_INIT(31'h0000_0001_0000_0000), - .REG9_INIT(31'h0000_0010_0000_0000), - .REGA_INIT(31'h0000_0100_0000_0000), - .REGB_INIT(31'h0000_1000_0000_0000), - .REGC_INIT(31'h0001_0000_0000_0000), - .REGD_INIT(31'h0010_0000_0000_0000), - .REGE_INIT(31'h0100_0000_0000_0000), - .REGF_INIT(31'h1000_0000_0000_0000) - ) test_reg ( - .clk(sys_clk), - .rst_n(sys_rst_n), - .addr(reg_reader_bus_addr), - .wr_data(reg_reader_bus_wr_data), - .wr_en(reg_reader_bus_wr_en), - .rd_data(fpga_test_rd_data) - ); - - /******************************************************************************* - * 信号源 * - *******************************************************************************/ - wire ISIG_logic0; // 逻辑0 - wire ISIG_logic1; // 逻辑1 - wire ISIG_ttlin1_module_ext; // ttl1输入模块原始信号 - wire ISIG_ttlin1_module_divide; // ttl1输入模块分频信号 - wire ISIG_ttlin2_module_ext; // ttl2输入模块原始信号 - wire ISIG_ttlin2_module_divide; // ttl2输入模块分频信号 - wire ISIG_ttlin3_module_ext; // ttl3输入模块原始信号 - wire ISIG_ttlin3_module_divide; // ttl3输入模块分频信号 - wire ISIG_ttlin4_module_ext; // ttl4输入模块原始信号 - wire ISIG_ttlin4_module_divide; // ttl4输入模块分频信号 - wire ISIG_internal_en_flag; // 内部使能状态信号输出 - wire ISIG_genlock_frame_sync_ext; // 外部genlock帧同步信号 - wire ISIG_genlock_frame_sync_internal; // 内部genlock帧同步信号 - wire ISIG_timecode_frame_sync_ext; // 外部timecode帧同步信号 - wire ISIG_timecode_frame_sync_internal; // 内部timecode帧同步信号 - wire ISIG_timecode_serial_data_ext; // 外部timecode串行数据输入 - wire ISIG_timecode_serial_data_internal; // 内部timecode串行数据输入 - wire ISIG_internal_100hz; // 100hz测试信号 - - wire [63:0] ISIGBUS64_timecode_data_ext; - wire [31:0] ISIGBUS32_timecode_format_ext; - - wire [63:0] ISIGBUS64_timecode_data_internal; - wire [31:0] ISIGBUS32_timecode_format_internal; - - assign ISIG_genlock_frame_sync_ext = genlock_in_vsync; - assign ISIG_logic0 = 0; - assign ISIG_logic1 = 1; - - - /******************************************************************************* - * TTL输出模块信号源分配 * - *******************************************************************************/ - wire [31:0] ttl_output_module_source_sig_af; - assign ttl_output_module_source_sig_af[0] = ISIG_logic0; - assign ttl_output_module_source_sig_af[1] = ISIG_logic1; - assign ttl_output_module_source_sig_af[2] = ISIG_ttlin1_module_ext; - assign ttl_output_module_source_sig_af[3] = ISIG_ttlin1_module_divide; - assign ttl_output_module_source_sig_af[4] = ISIG_ttlin2_module_ext; - assign ttl_output_module_source_sig_af[5] = ISIG_ttlin2_module_divide; - assign ttl_output_module_source_sig_af[6] = ISIG_ttlin3_module_ext; - assign ttl_output_module_source_sig_af[7] = ISIG_ttlin3_module_divide; - assign ttl_output_module_source_sig_af[8] = ISIG_ttlin4_module_ext; - assign ttl_output_module_source_sig_af[9] = ISIG_ttlin4_module_divide; - assign ttl_output_module_source_sig_af[10] = ISIG_internal_en_flag; - assign ttl_output_module_source_sig_af[11] = ISIG_genlock_frame_sync_ext; - assign ttl_output_module_source_sig_af[12] = ISIG_genlock_frame_sync_internal; - assign ttl_output_module_source_sig_af[13] = ISIG_timecode_frame_sync_ext; - assign ttl_output_module_source_sig_af[14] = ISIG_timecode_frame_sync_internal; - assign ttl_output_module_source_sig_af[15] = ISIG_timecode_serial_data_ext; - assign ttl_output_module_source_sig_af[16] = ISIG_timecode_serial_data_internal; - - assign ttl_output_module_source_sig_af[31] = ISIG_internal_100hz; - - - - xsync_internal_generator #( - .REG_START_ADD (REG_ADD_OFF_XSYNC_INTERNAL_SIG_GENERATOR), - .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ) - ) xsync_internal_generator_ins ( - .clk(sys_clk), - .rst_n(sys_rst_n), - .addr(reg_reader_bus_addr), - .wr_data(reg_reader_bus_wr_data), - .wr_en(reg_reader_bus_wr_en), - .rd_data(xsync_internal_sig_generator_rd_data), - - .ext_ttlin1_module_raw_sig(ISIG_ttlin1_module_ext), - .ext_ttlin2_module_raw_sig(ISIG_ttlin2_module_ext), - .ext_ttlin3_module_raw_sig(ISIG_ttlin3_module_ext), - .ext_ttlin4_module_raw_sig(ISIG_ttlin4_module_ext), - .ext_timecode_tigger_sig(ISIG_timecode_frame_sync_ext), - .ext_timecode_data(ISIGBUS64_timecode_data_ext), - .ext_genlock_signal(ISIG_genlock_frame_sync_ext), - - .out_timecode_tirgger_sig(ISIG_timecode_frame_sync_internal), //输出时码译码有效信号 - .out_timecode_sig(ISIGBUS64_timecode_data_internal), //[63:0] 输出时间 - .out_timecode_serial_sig(ISIG_timecode_serial_data_internal), //TIMECODE串行数据输出 - .out_genlock_sig(ISIG_genlock_frame_sync_internal), - .out_en_flag(ISIG_internal_en_flag) - ); - - /******************************************************************************* - * 时码解析器 * - *******************************************************************************/ - timecode_input_parser #( - .REG_START_ADD (REG_ADD_OFF_TIMECODE_IN), - .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ) - ) timecode_input_parser_ins ( - .clk (sys_clk), - .rst_n(sys_rst_n), - - .addr(reg_reader_bus_addr), - .wr_data(reg_reader_bus_wr_data), - .wr_en(reg_reader_bus_wr_en), - .rd_data(timecode_in_rd_data), - - //input - .timecode_bnc_in(timecode_bnc_in), - .timecode_headphone_in(timecode_headphone_in), - - //output - .timecode_tigger_sig(ISIG_timecode_frame_sync_ext), - .timecode_format(ISIGBUS32_timecode_format_ext), //[31:0] - .timecode_data(ISIGBUS64_timecode_data_ext), //[63:0] - .timecode_serial_data(ISIG_timecode_serial_data_ext), - .timecode_headphone_in_state_led(timecode_headphone_in_state_led), - .timecode_bnc_in_state_led(timecode_bnc_in_state_led) - ); - - ttl_input #( - .REG_START_ADD (REG_ADD_OFF_TTLIN1), - .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ) - ) ttl_inputr_ins ( - .clk (sys_clk), - .rst_n(sys_rst_n), - - .addr(reg_reader_bus_addr), - .wr_data(reg_reader_bus_wr_data), - .wr_en(reg_reader_bus_wr_en), - .rd_data(ttlin1_rd_data), - - .ttlin1(sync_ttl_in1), - .ttlin2(sync_ttl_in2), - .ttlin3(sync_ttl_in3), - .ttlin4(!sync_ttl_in4), //in4电路上进行了反向 - - //指示灯 - .ttlin1_state_led(sync_ttl_in1_state_led), - .ttlin2_state_led(sync_ttl_in2_state_led), - .ttlin3_state_led(sync_ttl_in3_state_led), - .ttlin4_state_led(sync_ttl_in4_state_led), - - //原始信号 - .ttlin1_ext(ISIG_ttlin1_module_ext), - .ttlin2_ext(ISIG_ttlin2_module_ext), - .ttlin3_ext(ISIG_ttlin3_module_ext), - .ttlin4_ext(ISIG_ttlin4_module_ext), - - //分频后的信号 - .ttlin1_divide(ISIG_ttlin1_module_divide), - .ttlin2_divide(ISIG_ttlin2_module_divide), - .ttlin3_divide(ISIG_ttlin3_module_divide), - .ttlin4_divide(ISIG_ttlin4_module_divide) - ); - - /******************************************************************************* - * ISIG_internal_100hz信号生成 * - *******************************************************************************/ - zutils_pwm_generator #( - .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ), - .OUTPUT_FREQ(100) - ) pwm100hz_gen ( - .clk(sys_clk), - .rst_n(sys_rst_n), - .output_signal(ISIG_internal_100hz) - ); - - - - - // =========================================================================================================== - // 输出组件 - // =========================================================================================================== - - // - camera_sync_signal_output #( - .REG_START_ADD (REG_ADD_OFF_CAMERA_SYNC_OUT), - .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ) - ) camera_sync_signal_output_ist ( - .clk (sys_clk), - .rst_n(sys_rst_n), - - .addr(reg_reader_bus_addr), - .wr_data(reg_reader_bus_wr_data), - .wr_en(reg_reader_bus_wr_en), - .rd_data(camera_sync_out_rd_data), - - .internal_genlock_sig(ISIG_genlock_frame_sync_internal), - .ext_genlock_sig(ISIG_genlock_frame_sync_ext), - .test_100hz_sig(ISIG_internal_100hz), - - .stm32if_camera_sync_out(stm32if_camera_sync_out) - ); - - - - /******************************************************************************* - * STM32_IF * - *******************************************************************************/ - assign stm32if_start_signal_out = ISIG_internal_en_flag; - - /******************************************************************************* - * timecode_output * - *******************************************************************************/ - timecode_output #( - .REG_START_ADD (REG_ADD_OFF_TIMECODE_OUT), - .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ) - ) timecode_output_inst ( - - .clk (sys_clk), - .rst_n(sys_rst_n), - - .addr(reg_reader_bus_addr), - .wr_data(reg_reader_bus_wr_data), - .wr_en(reg_reader_bus_wr_en), - .rd_data(timecode_out_rd_data), - - .ext_timecode_data(ISIGBUS64_timecode_data_ext), //63:0 - .ext_timecode_format(ISIGBUS32_timecode_format_ext), //31:0 - .ext_timecode_tigger_sig(ISIG_timecode_frame_sync_ext), - .ext_timecode_serial_data(ISIG_timecode_serial_data_ext), - - .internal_timecode_data(ISIGBUS64_timecode_data_internal), //63:0 - .internal_timecode_format(ISIGBUS32_timecode_format_internal), //31:0 - .internal_timecode_tigger_sig(ISIG_timecode_frame_sync_internal), - .internal_timecode_serial_data(ISIG_timecode_serial_data_internal), - - .stm32if_timecode_tigger_sig(stm32if_timecode_sync_out), - - .timecode_out_bnc(timecode_out_bnc), - .timecode_out_bnc_select(timecode_out_bnc_select), - .timecode_out_bnc_state_led(timecode_out_bnc_state_led), - - .timecode_out_headphone(timecode_out_headphone), - .timecode_out_headphone_select(timecode_out_headphone_select), - .timecode_out_headphone_state_led(timecode_out_headphone_state_led) - - ); - - /******************************************************************************* - * TTL_OUTPUT * - *******************************************************************************/ - ttl_output #( - .REG_START_ADD(REG_ADD_OFF_TTLOUT1), - .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ), - .ID(1) - ) ttl_output_1 ( - .clk (sys_clk), - .rst_n(sys_rst_n), - - .addr(reg_reader_bus_addr), - .wr_data(reg_reader_bus_wr_data), - .wr_en(reg_reader_bus_wr_en), - .rd_data(ttlout1_rd_data), - - .signal_in(ttl_output_module_source_sig_af), - - .ttloutput(sync_ttl_out1), - .ttloutput_state_led(sync_ttl_out1_state_led) - ); - - ttl_output #( - .REG_START_ADD(REG_ADD_OFF_TTLOUT2), - .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ), - .ID(2) - ) ttl_output_2 ( - .clk (sys_clk), - .rst_n(sys_rst_n), - - .addr(reg_reader_bus_addr), - .wr_data(reg_reader_bus_wr_data), - .wr_en(reg_reader_bus_wr_en), - .rd_data(ttlout2_rd_data), - - .signal_in(ttl_output_module_source_sig_af), - - .ttloutput(sync_ttl_out2), - .ttloutput_state_led(sync_ttl_out2_state_led) - ); - - ttl_output #( - .REG_START_ADD(REG_ADD_OFF_TTLOUT3), - .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ), - .ID(3) - ) ttl_output_3 ( - .clk (sys_clk), - .rst_n(sys_rst_n), - - .addr(reg_reader_bus_addr), - .wr_data(reg_reader_bus_wr_data), - .wr_en(reg_reader_bus_wr_en), - .rd_data(ttlout3_rd_data), - - .signal_in(ttl_output_module_source_sig_af), - - .ttloutput(sync_ttl_out3), - .ttloutput_state_led(sync_ttl_out3_state_led) - ); - - ttl_output #( - .REG_START_ADD(REG_ADD_OFF_TTLOUT4), - .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ), - .ID(4) - ) ttl_output_4 ( - .clk (sys_clk), - .rst_n(sys_rst_n), - - .addr(reg_reader_bus_addr), - .wr_data(reg_reader_bus_wr_data), - .wr_en(reg_reader_bus_wr_en), - .rd_data(ttlout4_rd_data), - - .signal_in(ttl_output_module_source_sig_af), - - .ttloutput(sync_ttl_out4), - .ttloutput_state_led(sync_ttl_out4_state_led) - ); - - - rd_data_router #( - .REG_ADD_OFF_STM32(REG_ADD_OFF_STM32), - .REG_ADD_OFF_FPGA_TEST(REG_ADD_OFF_FPGA_TEST), - .REG_ADD_OFF_XSYNC_INTERNAL_SIG_GENERATOR(REG_ADD_OFF_XSYNC_INTERNAL_SIG_GENERATOR), - .REG_ADD_OFF_TTLIN1(REG_ADD_OFF_TTLIN1), - .REG_ADD_OFF_TTLIN2(REG_ADD_OFF_TTLIN2), - .REG_ADD_OFF_TTLIN3(REG_ADD_OFF_TTLIN3), - .REG_ADD_OFF_TTLIN4(REG_ADD_OFF_TTLIN4), - .REG_ADD_OFF_TIMECODE_IN(REG_ADD_OFF_TIMECODE_IN), - .REG_ADD_OFF_GENLOCK_IN(REG_ADD_OFF_GENLOCK_IN), - .REG_ADD_OFF_TTLOUT1(REG_ADD_OFF_TTLOUT1), - .REG_ADD_OFF_TTLOUT2(REG_ADD_OFF_TTLOUT2), - .REG_ADD_OFF_TTLOUT3(REG_ADD_OFF_TTLOUT3), - .REG_ADD_OFF_TTLOUT4(REG_ADD_OFF_TTLOUT4), - .REG_ADD_OFF_TIMECODE_OUT(REG_ADD_OFF_TIMECODE_OUT), - .REG_ADD_OFF_GENLOCK_OUT(REG_ADD_OFF_GENLOCK_OUT), - .REG_ADD_OFF_CAMERA_SYNC_OUT(REG_ADD_OFF_CAMERA_SYNC_OUT), - .REG_ADD_OFF_DEBUGER(REG_ADD_OFF_DEBUGER) - - ) rd_data_router_inst ( - .addr(reg_reader_bus_addr), - - .stm32_rd_data(stm32_rd_data), - .fpga_test_rd_data(fpga_test_rd_data), - .xsync_internal_sig_generator_rd_data(xsync_internal_sig_generator_rd_data), - .ttlin1_rd_data(ttlin1_rd_data), - .ttlin2_rd_data(ttlin2_rd_data), - .ttlin3_rd_data(ttlin3_rd_data), - .ttlin4_rd_data(ttlin4_rd_data), - .timecode_in_rd_data(timecode_in_rd_data), - .genlock_in_rd_data(genlock_in_rd_data), - - .ttlout1_rd_data(ttlout1_rd_data), // ok - .ttlout2_rd_data(ttlout2_rd_data), // ok - .ttlout3_rd_data(ttlout3_rd_data), // ok - .ttlout4_rd_data(ttlout4_rd_data), // ok - - .timecode_out_rd_data(timecode_out_rd_data), - .genlock_out_rd_data(genlock_out_rd_data), - .camera_sync_out_rd_data(camera_sync_out_rd_data), - .debuger_rd_data(debuger_rd_data), - - .rd_data_out(reg_reader_bus_rd_data) - ); - // assign reg_reader_bus_rd_data[31:0] = fpga_test_rd_data[31:0]; - - // output reg stm32if_timecode_tigger_sig, - - // output reg timecode_out_bnc, - // output reg timecode_out_bnc_select, // 电平选择 0line,1:mic - // output reg timecode_out_bnc_state_led, - - // output reg timecode_out_headphone, - // output reg timecode_out_headphone_select, // 电平选择 0line,1:mic - // output reg timecode_out_headphone_state_led - - // assign debug_signal_output[0] = sync_ttl_out1; - // assign debug_signal_output[1] = sync_ttl_out2; - // assign debug_signal_output[2] = sync_ttl_out3; - // assign debug_signal_output[3] = sync_ttl_out4; - // assign debug_signal_output[4] = stm32if_timecode_sync_out; - // assign debug_signal_output[5] = timecode_out_bnc; - // assign debug_signal_output[6] = timecode_out_headphone; - // assign debug_signal_output[7] = genlock_in_hsync; - // assign debug_signal_output[8] = genlock_in_vsync; - // assign debug_signal_output[9] = genlock_in_fsync; - // assign debug_signal_output[10] = sync_ttl_in1; - // assign debug_signal_output[11] = sync_ttl_in2; - // assign debug_signal_output[12] = sync_ttl_in3; - // assign debug_signal_output[13] = sync_ttl_in4; - // assign debug_signal_output[14] = timecode_headphone_in; - // assign debug_signal_output[15] = timecode_bnc_in; - - - assign debug_signal_output[0] = sys_clk; - assign debug_signal_output[1] = sync_ttl_in1; - assign debug_signal_output[2] = sync_ttl_in2; - assign debug_signal_output[3] = sync_ttl_in3; - assign debug_signal_output[4] = sync_ttl_in4; - assign debug_signal_output[5] = sync_ttl_out1; - assign debug_signal_output[6] = sync_ttl_out2; - assign debug_signal_output[7] = sync_ttl_out3; - assign debug_signal_output[8] = sync_ttl_out4; - assign debug_signal_output[9] = genlock_in_fsync; - assign debug_signal_output[10] = timecode_headphone_in; - assign debug_signal_output[11] = timecode_bnc_in; - assign debug_signal_output[12] = timecode_out_headphone; - assign debug_signal_output[13] = timecode_out_bnc; - assign debug_signal_output[14] = ISIG_internal_en_flag; - assign debug_signal_output[15] = 0; - - - - - assign core_board_debug_led = 1; - assign genlock_in_state_led = 1; - - assign stm32if_start_signal_out = ISIG_internal_en_flag; - -endmodule diff --git a/source/src/top.v b/source/src/top.v index 8c46ddb..897ef3e 100644 --- a/source/src/top.v +++ b/source/src/top.v @@ -14,7 +14,6 @@ module Top ( input wire uart_rx, - output wire [4:0] tmp_contrl_pin, output wire core_board_debug_led, @@ -25,58 +24,10 @@ module Top ( /******************************************************************************* * 差分输入 * *******************************************************************************/ - input wire diff_in1, - input wire diff_in2, - input wire diff_in3, - input wire diff_in4, - - /******************************************************************************* - * 光耦输入 * - *******************************************************************************/ - - input wire optocoupler_in1, - input wire optocoupler_in2, - input wire optocoupler_in3, - input wire optocoupler_in4, - - /******************************************************************************* - * 差分输出 * - *******************************************************************************/ - - output wire diff_out1, - output wire diff_out2, - output wire diff_out3, - output wire diff_out4, - - /******************************************************************************* - * 光耦输出 * - *******************************************************************************/ - - output wire optocoupler_out1, - output wire optocoupler_out2, - output wire optocoupler_out3, - output wire optocoupler_out4, - - /******************************************************************************* - * 光源控制引脚 * - *******************************************************************************/ - - output wire lt1_intensity_ctrl, - output wire lt1_en, - input wire lt1_error_sig_in, - - output wire lt2_intensity_ctrl, - output wire lt2_en, - input wire lt2_error_sig_in, - - output wire lt3_intensity_ctrl, - output wire lt3_en, - input wire lt3_error_sig_in, - - output wire lt4_intensity_ctrl, - output wire lt4_en, - input wire lt4_error_sig_in - + input wire triSig, + output wire out1, + output wire extOutputEn1, + output wire extOutputEn2 ); wire sys_clk; //! 系统时钟 @@ -100,30 +51,11 @@ module Top ( .clkout3 (sys_clk_100m) ); localparam SYS_CLOCK_FREQ = 100000000; - assign sys_clk = sys_clk_100m; - assign sys_rst_n = stm32_input_bus[0] & pll_lock; - - assign tmp_contrl_pin[0] = !sys_rst_n; - assign tmp_contrl_pin[1] = !sys_rst_n; - assign tmp_contrl_pin[2] = !sys_rst_n; - assign tmp_contrl_pin[3] = !sys_rst_n; - assign tmp_contrl_pin[4] = !sys_rst_n; + assign sys_clk = sys_clk_100m; + assign sys_rst_n = stm32_input_bus[0] & pll_lock; wire [31:0] rd_data_fpga_info; - wire [31:0] rd_data_internal_clk; - wire [31:0] rd_data_internal_trigger; - wire [31:0] rd_data_trigger_in4; - wire [31:0] rd_data_trigger_in1; - wire [31:0] rd_data_trigger_in2; - wire [31:0] rd_data_trigger_in3; - wire [31:0] rd_data_light_ctrol_module4; - wire [31:0] rd_data_light_ctrol_module1; - wire [31:0] rd_data_light_ctrol_module2; - wire [31:0] rd_data_light_ctrol_module3; - wire [31:0] rd_data_ttl_output_module4; - wire [31:0] rd_data_ttl_output_module1; - wire [31:0] rd_data_ttl_output_module2; - wire [31:0] rd_data_ttl_output_module3; + wire [31:0] rd_data_app; spi_reg_bus _spi_reg_bus ( .clk (sys_clk), @@ -136,21 +68,8 @@ module Top ( .spi_rx_pin (spi_rx_pin), .spi_tx_pin (spi_tx_pin), - .rd_data_fpga_info (rd_data_fpga_info), - .rd_data_internal_clk (rd_data_internal_clk), - .rd_data_internal_trigger (rd_data_internal_trigger), - .rd_data_trigger_in4 (rd_data_trigger_in4), - .rd_data_trigger_in1 (rd_data_trigger_in1), - .rd_data_trigger_in2 (rd_data_trigger_in2), - .rd_data_trigger_in3 (rd_data_trigger_in3), - .rd_data_light_ctrol_module4(rd_data_light_ctrol_module4), - .rd_data_light_ctrol_module1(rd_data_light_ctrol_module1), - .rd_data_light_ctrol_module2(rd_data_light_ctrol_module2), - .rd_data_light_ctrol_module3(rd_data_light_ctrol_module3), - .rd_data_ttl_output_module4 (rd_data_ttl_output_module4), - .rd_data_ttl_output_module1 (rd_data_ttl_output_module1), - .rd_data_ttl_output_module2 (rd_data_ttl_output_module2), - .rd_data_ttl_output_module3 (rd_data_ttl_output_module3) + .rd_data_fpga_info(rd_data_fpga_info), + .rd_data_app (rd_data_app) ); /******************************************************************************* @@ -174,7 +93,7 @@ module Top ( .REGD_INIT(14), .REGE_INIT(15), .REGF_INIT(16) - ) test_reg ( + ) fpga_info_reg ( .clk (sys_clk), .rst_n (sys_rst_n), .addr (RegReaderBus_addr), @@ -183,384 +102,11 @@ module Top ( .rd_data(rd_data_fpga_info) ); - wire [31:0] sig_bus; - assign sig_bus[`SIG_LOGIC0] = 0; - assign sig_bus[`SIG_LOGIC1] = 1; - - wire [3:0] lt_en_sig_bus; - assign lt_en_sig_bus[0] = lt1_en; - assign lt_en_sig_bus[1] = lt2_en; - assign lt_en_sig_bus[2] = lt3_en; - assign lt_en_sig_bus[3] = lt4_en; - - - /******************************************************************************* - * INTERNAL_CLK * - *******************************************************************************/ - - internal_trigger_clk #( - .REG_START_ADD (`REGADDOFF__INTERNAL_CLK), - .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ) - ) internal_trigger_clk_ins ( - .clk (sys_clk), - .rst_n(sys_rst_n), - - .addr (RegReaderBus_addr), - .wr_data(RegReaderBus_wr_data), - .wr_en (RegReaderBus_wr_en), - .rd_data(rd_data_internal_clk), - - .output_sig(internal_trigger_clk_ins_output_sig) - ); - - trigger_source_base_module #( - .REG_START_ADD(`REGADDOFF__INTERNAL_TRIGGER), - .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ), - .FREQ_DETECT_BIAS(0) - ) internal_trigger_clk_trigger_source_base_module ( - .clk (sys_clk), - .rst_n(sys_rst_n), - - .addr (RegReaderBus_addr), - .wr_data(RegReaderBus_wr_data), - .wr_en (RegReaderBus_wr_en), - .rd_data(rd_data_internal_trigger), - - .in_sig_0(internal_trigger_clk_ins_output_sig), - .in_sig_1(internal_trigger_clk_ins_output_sig), - - .out_trigger_sig (sig_bus[`SIG_INTERNAL_CLK]), - .out_trigger_sig_index0(sig_bus[`SIG_INTERNAL_CLK_I1]), - .out_trigger_sig_index1(sig_bus[`SIG_INTERNAL_CLK_I2]), - .out_trigger_sig_index2(sig_bus[`SIG_INTERNAL_CLK_I3]), - .out_trigger_sig_index3(sig_bus[`SIG_INTERNAL_CLK_I4]) - ); - - - - - trigger_source_base_module #( - .REG_START_ADD (`REGADDOFF__TRIGGER_IN1), - .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ) - ) trigger_in1 ( - .clk (sys_clk), - .rst_n(sys_rst_n), - - .addr (RegReaderBus_addr), - .wr_data(RegReaderBus_wr_data), - .wr_en (RegReaderBus_wr_en), - .rd_data(rd_data_trigger_in1), - - .in_sig_0 (!optocoupler_in1), - .in_sig_1 (diff_in1), - .in_sig_2 (sig_bus[`SIG_INTERNAL_CLK]), - .in_sig_selected(trigger_in_selected_1), - - .out_trigger_sig (sig_bus[`SIG_EXT_TRIGGER_1]), - .out_trigger_sig_index0(sig_bus[`SIG_EXT_TRIGGER_1_I1]), - .out_trigger_sig_index1(sig_bus[`SIG_EXT_TRIGGER_1_I2]), - .out_trigger_sig_index2(sig_bus[`SIG_EXT_TRIGGER_1_I3]), - .out_trigger_sig_index3(sig_bus[`SIG_EXT_TRIGGER_1_I4]), - - - .debug_sig_0(trigger_1_debug_sig_0), - .debug_sig_1(trigger_1_debug_sig_1), - .debug_sig_2(trigger_1_debug_sig_2) - - ); - - - - trigger_source_base_module #( - .REG_START_ADD (`REGADDOFF__TRIGGER_IN2), - .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ) - ) trigger_in2 ( - .clk (sys_clk), - .rst_n(sys_rst_n), - - .addr (RegReaderBus_addr), - .wr_data(RegReaderBus_wr_data), - .wr_en (RegReaderBus_wr_en), - .rd_data(rd_data_trigger_in2), - - .in_sig_0 (!optocoupler_in2), - .in_sig_1 (diff_in2), - .in_sig_2 (sig_bus[`SIG_INTERNAL_CLK]), - .in_sig_selected(trigger_in_selected_2), - - .out_trigger_sig (sig_bus[`SIG_EXT_TRIGGER_2]), - .out_trigger_sig_index0(sig_bus[`SIG_EXT_TRIGGER_2_I1]), - .out_trigger_sig_index1(sig_bus[`SIG_EXT_TRIGGER_2_I2]), - .out_trigger_sig_index2(sig_bus[`SIG_EXT_TRIGGER_2_I3]), - .out_trigger_sig_index3(sig_bus[`SIG_EXT_TRIGGER_2_I4]) - ); - - trigger_source_base_module #( - .REG_START_ADD (`REGADDOFF__TRIGGER_IN3), - .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ) - ) trigger_in3 ( - .clk (sys_clk), - .rst_n(sys_rst_n), - - .addr (RegReaderBus_addr), - .wr_data(RegReaderBus_wr_data), - .wr_en (RegReaderBus_wr_en), - .rd_data(rd_data_trigger_in3), - - .in_sig_0 (!optocoupler_in3), - .in_sig_1 (diff_in3), - .in_sig_2 (sig_bus[`SIG_INTERNAL_CLK]), - .in_sig_selected(trigger_in_selected_3), - - - .out_trigger_sig (sig_bus[`SIG_EXT_TRIGGER_3]), - .out_trigger_sig_index0(sig_bus[`SIG_EXT_TRIGGER_3_I1]), - .out_trigger_sig_index1(sig_bus[`SIG_EXT_TRIGGER_3_I2]), - .out_trigger_sig_index2(sig_bus[`SIG_EXT_TRIGGER_3_I3]), - .out_trigger_sig_index3(sig_bus[`SIG_EXT_TRIGGER_3_I4]) - ); - - trigger_source_base_module #( - .REG_START_ADD (`REGADDOFF__TRIGGER_IN4), - .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ) - ) trigger_in4 ( - .clk (sys_clk), - .rst_n(sys_rst_n), - - .addr (RegReaderBus_addr), - .wr_data(RegReaderBus_wr_data), - .wr_en (RegReaderBus_wr_en), - .rd_data(rd_data_trigger_in4), - - .in_sig_0 (!optocoupler_in4), - .in_sig_1 (diff_in4), - .in_sig_2 (sig_bus[`SIG_INTERNAL_CLK]), - .in_sig_selected(trigger_in_selected_4), - - .out_trigger_sig (sig_bus[`SIG_EXT_TRIGGER_4]), - .out_trigger_sig_index0(sig_bus[`SIG_EXT_TRIGGER_4_I1]), - .out_trigger_sig_index1(sig_bus[`SIG_EXT_TRIGGER_4_I2]), - .out_trigger_sig_index2(sig_bus[`SIG_EXT_TRIGGER_4_I3]), - .out_trigger_sig_index3(sig_bus[`SIG_EXT_TRIGGER_4_I4]) - ); - - // ttl_output_ctrl - - light_src_ctrl #( - .REG_START_ADD(`REGADDOFF__LIGHT_CTROL_MODULE1), - .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ), - .ID(1) - ) light_src_ctrl_1 ( - .clk (sys_clk), - .rst_n(sys_rst_n), - - .addr (RegReaderBus_addr), - .wr_data(RegReaderBus_wr_data), - .wr_en (RegReaderBus_wr_en), - .rd_data(rd_data_light_ctrol_module1), - - .signal_in(sig_bus), - - .lt_intensity_ctrl(lt1_intensity_ctrl), - .lt_en (lt1_en), - .lt_error_sig_in (lt1_error_sig_in) - ); - - - ttl_output_ctrl #( - .REG_START_ADD (`REGADDOFF__TTL_OUTPUT_MODULE1), - .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ) - ) ttl_output_ctrl_1 ( - .clk (sys_clk), - .rst_n(sys_rst_n), - - .addr (RegReaderBus_addr), - .wr_data(RegReaderBus_wr_data), - .wr_en (RegReaderBus_wr_en), - .rd_data(rd_data_ttl_output_module1), - - .sys_internal_sig_bus(sig_bus), - .lt_en_sig (lt_en_sig_bus), - - .diff_out (diff_out1), - .optocoupler_out(optocoupler_out1) - ); - - light_src_ctrl #( - .REG_START_ADD(`REGADDOFF__LIGHT_CTROL_MODULE2), - .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ), - .ID(2) - ) light_src_ctrl_2 ( - .clk (sys_clk), - .rst_n(sys_rst_n), - - .addr (RegReaderBus_addr), - .wr_data(RegReaderBus_wr_data), - .wr_en (RegReaderBus_wr_en), - .rd_data(rd_data_light_ctrol_module2), - - .signal_in(sig_bus), - - .lt_intensity_ctrl(lt2_intensity_ctrl), - .lt_en (lt2_en), - .lt_error_sig_in (lt2_error_sig_in) - ); - - - ttl_output_ctrl #( - .REG_START_ADD (`REGADDOFF__TTL_OUTPUT_MODULE2), - .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ) - ) ttl_output_ctrl_2 ( - .clk (sys_clk), - .rst_n(sys_rst_n), - - .addr (RegReaderBus_addr), - .wr_data(RegReaderBus_wr_data), - .wr_en (RegReaderBus_wr_en), - .rd_data(rd_data_ttl_output_module2), - - .sys_internal_sig_bus(sig_bus), - .lt_en_sig (lt_en_sig_bus), - - .diff_out (diff_out2), - .optocoupler_out(optocoupler_out2) - ); - - light_src_ctrl #( - .REG_START_ADD(`REGADDOFF__LIGHT_CTROL_MODULE3), - .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ), - .ID(3) - ) light_src_ctrl_3 ( - .clk (sys_clk), - .rst_n(sys_rst_n), - - .addr (RegReaderBus_addr), - .wr_data(RegReaderBus_wr_data), - .wr_en (RegReaderBus_wr_en), - .rd_data(rd_data_light_ctrol_module3), - - .signal_in(sig_bus), - - .lt_intensity_ctrl(lt3_intensity_ctrl), - .lt_en (lt3_en), - .lt_error_sig_in (lt3_error_sig_in) - ); - - - ttl_output_ctrl #( - .REG_START_ADD (`REGADDOFF__TTL_OUTPUT_MODULE3), - .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ) - ) ttl_output_ctrl_3 ( - .clk (sys_clk), - .rst_n(sys_rst_n), - - .addr (RegReaderBus_addr), - .wr_data(RegReaderBus_wr_data), - .wr_en (RegReaderBus_wr_en), - .rd_data(rd_data_ttl_output_module3), - - .sys_internal_sig_bus(sig_bus), - .lt_en_sig (lt_en_sig_bus), - - .diff_out (diff_out3), - .optocoupler_out(optocoupler_out3) - ); - - light_src_ctrl #( - .REG_START_ADD(`REGADDOFF__LIGHT_CTROL_MODULE4), - .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ), - .ID(4) - ) light_src_ctrl_4 ( - .clk (sys_clk), - .rst_n(sys_rst_n), - - .addr (RegReaderBus_addr), - .wr_data(RegReaderBus_wr_data), - .wr_en (RegReaderBus_wr_en), - .rd_data(rd_data_light_ctrol_module4), - - .signal_in(sig_bus), - - .lt_intensity_ctrl(lt4_intensity_ctrl), - .lt_en (lt4_en), - .lt_error_sig_in (lt4_error_sig_in) - ); - - - ttl_output_ctrl #( - .REG_START_ADD (`REGADDOFF__TTL_OUTPUT_MODULE4), - .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ) - ) ttl_output_ctrl_4 ( - .clk (sys_clk), - .rst_n(sys_rst_n), - - .addr (RegReaderBus_addr), - .wr_data(RegReaderBus_wr_data), - .wr_en (RegReaderBus_wr_en), - .rd_data(rd_data_ttl_output_module4), - - .sys_internal_sig_bus(sig_bus), - .lt_en_sig (lt_en_sig_bus), - - .diff_out (diff_out4), - .optocoupler_out(optocoupler_out4) - ); - - - assign debug_bus[0] = trigger_in_selected_1; - assign debug_bus[1] = sig_bus[`SIG_EXT_TRIGGER_1]; - assign debug_bus[2] = trigger_in_selected_2; - assign debug_bus[3] = sig_bus[`SIG_EXT_TRIGGER_2]; - assign debug_bus[4] = trigger_in_selected_3; - assign debug_bus[5] = sig_bus[`SIG_EXT_TRIGGER_3]; - assign debug_bus[6] = trigger_in_selected_4; - assign debug_bus[7] = sig_bus[`SIG_EXT_TRIGGER_4]; - assign debug_bus[8] = lt1_intensity_ctrl; - assign debug_bus[9] = lt2_intensity_ctrl; - assign debug_bus[10] = lt3_intensity_ctrl; - assign debug_bus[11] = lt4_intensity_ctrl; - - - assign debug_bus[12] = diff_out1; - assign debug_bus[13] = diff_out2; - assign debug_bus[14] = diff_out3; - assign debug_bus[15] = diff_out4; - - - - - // assign debug_bus[0] = sys_clk; - // assign optocoupler_out1 = diff_in1; - // assign optocoupler_out2 = diff_in2; - // assign optocoupler_out3 = diff_in3; - // assign optocoupler_out4 = diff_in4; - - // assign diff_out1 = optocoupler_in1; - // assign diff_out2 = optocoupler_in2; - // assign diff_out3 = optocoupler_in3; - // assign diff_out4 = optocoupler_in4; - - - // assign lt1_intensity_ctrl = optocoupler_in1; - // assign lt1_en = optocoupler_in2; - // assign lt2_intensity_ctrl = optocoupler_in1; - // assign lt2_en = optocoupler_in2; - // assign lt3_intensity_ctrl = optocoupler_in1; - // assign lt3_en = optocoupler_in2; - // assign lt4_intensity_ctrl = optocoupler_in1; - // assign lt4_en = optocoupler_in2; - - - // assign uart_tx = uart_rx; - // assign stm32_output_bus[0] = stm32_input_bus[0]; - // assign stm32_output_bus[1] = stm32_input_bus[1]; - // assign stm32_output_bus[2] = stm32_input_bus[2]; - // assign stm32_output_bus[3] = stm32_input_bus[3]; - // assign stm32_output_bus[4] = stm32_input_bus[4]; - // assign stm32_output_bus[5] = stm32_input_bus[5]; - // assign stm32_output_bus[6] = stm32_input_bus[6]; - // assign stm32_output_bus[7] = stm32_input_bus[7]; + // assign debug_bus[12] = diff_out1; + // assign debug_bus[13] = diff_out2; + // assign debug_bus[14] = diff_out3; + // assign debug_bus[15] = diff_out4; endmodule diff --git a/source/src/trigger_source/internal_trigger_clk.v b/source/src/trigger_source/internal_trigger_clk.v deleted file mode 100644 index 57614a1..0000000 --- a/source/src/trigger_source/internal_trigger_clk.v +++ /dev/null @@ -1,91 +0,0 @@ -`include "../config.v" -module internal_trigger_clk #( - parameter REG_START_ADD = 0, - parameter SYS_CLOCK_FREQ = 100000000 -) ( - - input clk, //! 时钟输入 - input rst_n, //! 复位输入 - - input [31:0] addr, //! 寄存器地址 - input [31:0] wr_data, //! 写入数据 - input wr_en, //! 写使能 - output wire [31:0] rd_data, //! 读出数据 - - // - output output_sig -); - - reg [31:0] reg1_ctrl; - reg [31:0] reg2_cfg_freq_cnt; - reg [31:0] reg3_cfg_pluse_cnt; - wire [31:0] regF_output_sig_detect; - - wire [31:0] reg_wr_index; - - zutils_register_advanced #( - .REG_START_ADD(REG_START_ADD) - ) _register ( - .clk (clk), - .rst_n (rst_n), - .addr (addr), - .wr_data(wr_data), - .wr_en (wr_en), - .rd_data(rd_data), - - .reg1(reg1_ctrl), - .reg2(reg2_cfg_freq_cnt), - .reg3(reg3_cfg_pluse_cnt), - .regF(regF_output_sig_detect), - - .reg_wr_sig(reg_wr_sig), - .reg_index (reg_wr_index) - ); - - reg start_sig; - reg stop_sig; - - always @(posedge clk or negedge rst_n) begin - if (!rst_n) begin - reg1_ctrl <= 0; - reg2_cfg_freq_cnt <= SYS_CLOCK_FREQ / 10; //输出频率10hz - reg3_cfg_pluse_cnt <= 32'd0; // - end else begin - if (reg_wr_sig) begin - case (reg_wr_index) - 32'h2: reg2_cfg_freq_cnt <= wr_data; - 32'h3: reg3_cfg_pluse_cnt <= wr_data; - default: begin - end - endcase - end - end - end - - always @(*) begin - start_sig <= (reg_wr_index == 1) & reg_wr_sig & (wr_data == 1); - stop_sig <= (reg_wr_index == 1) & reg_wr_sig & (wr_data == 0); - end - - - zutils_trigger_sig_gen zutils_trigger_sig_gen ( - .clk (clk), - .rst_n(rst_n), - - .start_sig (start_sig), - .stop_sig (stop_sig), - .cfg_freq_cnt (reg2_cfg_freq_cnt), - .cfg_pluse_cnt(reg3_cfg_pluse_cnt), - - .output_signal(output_sig) - ); - - zutils_freq_detector_v2 freq_detector2 ( - .clk (clk), - .rst_n (rst_n), - .freq_detect_bias(1), - .pluse_input (output_sig), - .pluse_width_cnt (regF_output_sig_detect) - ); - -endmodule diff --git a/source/src/trigger_source/trigger_source_base_module.v b/source/src/trigger_source/trigger_source_base_module.v index f031aa3..62048af 100644 --- a/source/src/trigger_source/trigger_source_base_module.v +++ b/source/src/trigger_source/trigger_source_base_module.v @@ -5,13 +5,13 @@ module trigger_source_base_module #( parameter FREQ_DETECT_BIAS = `FREQ_DETECT_BIAS_DEFAULT ) ( - input clk, //! 时钟输入 - input rst_n, //! 复位输入 + input clk, //! ʱ + input rst_n, //! λ - input [31:0] addr, //! 寄存器地址 - input [31:0] wr_data, //! 写入数据 - input wr_en, //! 写使能 - output wire [31:0] rd_data, //! 读出数据 + input [31:0] addr, //! Ĵַ + input [31:0] wr_data, //! д + input wr_en, //! дʹ + output wire [31:0] rd_data, //! // input wire in_sig_0, @@ -35,29 +35,29 @@ module trigger_source_base_module #( // translate // pll // - // 触发模式: + // ģʽ: // sig --> fileter_sig | // simple_pll | // | ---> out_trigger_sig_index - // 转发模式: + // תģʽ: // sig --> filter_sig | // - reg [31:0] reg1_src_slect; //!信号源选择 - reg [31:0] reg2_fileter_coefficient; //!滤波系数 - reg [31:0] reg3_freq_detect_bias; //!脉冲频率探测误差 + reg [31:0] reg1_src_slect; //!źԴѡ + reg [31:0] reg2_fileter_coefficient; //!˲ϵ + reg [31:0] reg3_freq_detect_bias; //!Ƶ̽ - reg [31:0] reg4_mode; //!0:触发模式 1:转发模式 + reg [31:0] reg4_mode; //!0:ģʽ 1:תģʽ - reg [31:0] reg5_trigger_mode_trigger_edge; //!触发边沿 - reg [31:0] reg6_trigger_mode_freq_division; //!频率分频 - reg [31:0] reg7_trigger_mode_freq_multiplication; //!频率倍频 + reg [31:0] reg5_trigger_mode_trigger_edge; //! + reg [31:0] reg6_trigger_mode_freq_division; //!ƵʷƵ + reg [31:0] reg7_trigger_mode_freq_multiplication; //!ƵʱƵ - reg [31:0] regA_sequential_control_pluse_cnt_max; //!顺序控制脉冲最大计数 + reg [31:0] regA_sequential_control_pluse_cnt_max; //!˳ - wire [31:0] regE_in_signal_freq; //!输入脉冲频率 - wire [31:0] regF_out_signal_freq; //!输出脉冲频率 + wire [31:0] regE_in_signal_freq; //!Ƶ + wire [31:0] regF_out_signal_freq; //!Ƶ wire [31:0] reg_wr_index; @@ -121,10 +121,10 @@ module trigger_source_base_module #( assign in_sig[3] = !in_sig_0; assign in_sig[4] = !in_sig_1; - reg sig_af_choose; //!选择后的触发信号 - wire sig_af_choose_af_filter; //!滤波后的脉冲 - wire sig_af_choose_af_filter_af_pll; //!PLL后的脉冲 - reg signal_out_final; //!最终输出的信号 + reg sig_af_choose; //!ѡĴź + wire sig_af_choose_af_filter; //!˲ + wire sig_af_choose_af_filter_af_pll; //!PLL + reg signal_out_final; //!ź assign in_sig_selected = sig_af_choose; diff --git a/source/src/trigger_source/ttl_trigger_source.v b/source/src/trigger_source/ttl_trigger_source.v deleted file mode 100644 index e69de29..0000000 diff --git a/camera_light_src_timing_controller_fpga.pds b/syncbox16ch.pds similarity index 74% rename from camera_light_src_timing_controller_fpga.pds rename to syncbox16ch.pds index 162fdd2..9312fa9 100644 --- a/camera_light_src_timing_controller_fpga.pds +++ b/syncbox16ch.pds @@ -1,5 +1,5 @@ (_flow fab_demo "2021.1-SP7" - (_comment "Generated by Fabric Compiler (version on 2021.1-SP7) at Fri May 10 16:41:06 2024") + (_comment "Generated by Fabric Compiler (version on 2021.1-SP7) at Mon Aug 5 13:54:18 2024") (_version "1.0.5") (_status "initial") (_project @@ -19,7 +19,7 @@ (_input (_file "source/src/top.v" + "Top:" (_format verilog) - (_timespec "2024-05-10T15:22:54") + (_timespec "2024-08-05T13:53:15") ) (_file "source/src/spi_reg_reader.v" (_format verilog) @@ -101,30 +101,6 @@ (_format verilog) (_timespec "2024-03-10T18:52:01") ) - (_file "source/src/timecode/timecode_nextcode.v" - (_format verilog) - (_timespec "2024-03-08T21:15:01") - ) - (_file "source/src/timecode/timecode_basesig_generator.v" - (_format verilog) - (_timespec "2024-03-10T18:52:01") - ) - (_file "source/src/timecode/timecode_serialization.v" - (_format verilog) - (_timespec "2024-03-10T18:52:01") - ) - (_file "source/src/timecode/timecode_generator.v" - (_format verilog) - (_timespec "2024-03-10T18:52:01") - ) - (_file "source/src/timecode/timecode_decoder.v" - (_format verilog) - (_timespec "2024-03-10T18:52:01") - ) - (_file "source/src/timecode/timecode_sample_sig_generator.v" - (_format verilog) - (_timespec "2024-03-10T18:52:01") - ) (_file "source/src/zutils/ztuils_sig_devide.v" (_format verilog) (_timespec "2024-03-08T21:15:01") @@ -133,10 +109,6 @@ (_format verilog) (_timespec "2024-03-08T21:15:01") ) - (_file "source/src/timecode/timecode_comparator.v" - (_format verilog) - (_timespec "2024-03-08T21:15:01") - ) (_file "source/src/zutils/zutils_freq_detector.v" (_format verilog) (_timespec "2024-03-08T21:15:01") @@ -155,48 +127,16 @@ ) (_file "source/src/spi_reg_bus.v" (_format verilog) - (_timespec "2024-03-10T18:37:55") - ) - (_file "source/src/internal/internal_timecode_generator.v" - (_format verilog) - (_timespec "2024-03-10T18:52:01") - ) - (_file "source/src/internal/internal_clock_generator.v" - (_format verilog) - (_timespec "2024-05-10T16:08:28") - ) - (_file "source/src/internal/internal_genlock_generator.v" - (_format verilog) - (_timespec "2024-03-10T18:52:01") - ) - (_file "source/src/business/record_sig_generator.v" - (_format verilog) - (_timespec "2024-03-10T18:52:01") + (_timespec "2024-08-05T13:25:16") ) (_file "source/src/zutils/zutils_debug_pwm_generator.v" (_format verilog) (_timespec "2024-03-10T18:52:01") ) - (_file "source/src/trigger_source/internal_trigger_clk.v" - (_format verilog) - (_timespec "2024-03-11T00:09:16") - ) (_file "source/src/zutils/zutils_trigger_sig_gen.v" (_format verilog) (_timespec "2024-03-10T17:37:01") ) - (_file "source/src/trigger_source/trigger_source_base_module.v" - (_format verilog) - (_timespec "2024-05-10T15:21:17") - ) - (_file "source/src/output/light_src_ctrl.v" - (_format verilog) - (_timespec "2024-03-11T09:38:33") - ) - (_file "source/src/output/ttl_output_ctrl.v" - (_format verilog) - (_timespec "2024-03-11T15:57:40") - ) (_file "source/src/zutils/zutils_pluse_generator_v2.v" (_format verilog) (_timespec "2024-03-10T14:04:31") @@ -219,16 +159,13 @@ (_timespec "2024-03-10T18:50:53") ) ) - (_ip "ipcore/genlock_sig_gen_pll/genlock_sig_gen_pll.idf" - (_timespec "2024-03-08T21:15:01") - ) ) ) (_widget wgt_import_logic_con_file (_input - (_file "camera_light_src_timing_controller_fpga.fdc" + (_file "app.fdc" (_format fdc) - (_timespec "2024-04-25T16:32:20") + (_timespec "2024-08-05T13:52:36") ) ) ) @@ -279,17 +216,17 @@ (_db_output (_file "compile/Top_comp.adf" (_format adif) - (_timespec "2024-05-10T16:39:23") + (_timespec "2024-08-05T13:53:32") ) ) (_output (_file "compile/Top.cmr" (_format verilog) - (_timespec "2024-05-10T16:39:21") + (_timespec "2024-08-05T13:53:32") ) (_file "compile/cmr.db" (_format text) - (_timespec "2024-05-10T16:39:23") + (_timespec "2024-08-05T13:53:32") ) ) ) @@ -305,21 +242,21 @@ (_db_output (_file "synthesize/Top_syn.adf" (_format adif) - (_timespec "2024-05-10T16:39:41") + (_timespec "2024-08-05T13:53:35") ) ) (_output (_file "synthesize/Top_syn.vm" (_format structural_verilog) - (_timespec "2024-05-10T16:39:43") + (_timespec "2024-08-05T13:53:36") ) (_file "synthesize/Top.snr" (_format text) - (_timespec "2024-05-10T16:39:44") + (_timespec "2024-08-05T13:53:36") ) (_file "synthesize/snr.db" (_format text) - (_timespec "2024-05-10T16:39:44") + (_timespec "2024-08-05T13:53:37") ) ) ) @@ -340,30 +277,30 @@ (_db_output (_file "device_map/Top_map.adf" (_format adif) - (_timespec "2024-05-10T16:39:48") + (_timespec "2024-08-05T13:53:39") ) ) (_output (_file "device_map/Top_dmr.prt" (_format text) - (_timespec "2024-05-10T16:39:46") + (_timespec "2024-08-05T13:53:39") ) (_file "device_map/Top.dmr" (_format text) - (_timespec "2024-05-10T16:39:48") + (_timespec "2024-08-05T13:53:39") ) (_file "device_map/dmr.db" (_format text) - (_timespec "2024-05-10T16:39:48") + (_timespec "2024-08-05T13:53:39") ) ) ) (_widget wgt_edit_placement_cons (_attribute _click_to_run (_switch ON)) (_input - (_file "device_map/camera_light_src_timing_controller_fpga.pcf" + (_file "device_map/xsyncbox16ch.pcf" (_format pcf) - (_timespec "2024-05-10T16:39:48") + (_timespec "2024-08-05T13:53:39") ) ) ) @@ -378,33 +315,33 @@ (_db_output (_file "place_route/Top_pnr.adf" (_format adif) - (_timespec "2024-05-10T16:40:24") + (_timespec "2024-08-05T13:53:57") ) ) (_output (_file "place_route/Top.prr" (_format text) - (_timespec "2024-05-10T16:40:24") + (_timespec "2024-08-05T13:53:57") ) (_file "place_route/Top_prr.prt" (_format text) - (_timespec "2024-05-10T16:40:24") + (_timespec "2024-08-05T13:53:57") ) (_file "place_route/clock_utilization.txt" (_format text) - (_timespec "2024-05-10T16:40:24") + (_timespec "2024-08-05T13:53:57") ) (_file "place_route/Top_plc.adf" (_format adif) - (_timespec "2024-05-10T16:39:59") + (_timespec "2024-08-05T13:53:47") ) (_file "place_route/Top_pnr.netlist" (_format text) - (_timespec "2024-05-10T16:40:24") + (_timespec "2024-08-05T13:53:57") ) (_file "place_route/prr.db" (_format text) - (_timespec "2024-05-10T16:40:24") + (_timespec "2024-08-05T13:53:58") ) ) ) @@ -439,19 +376,19 @@ (_output (_file "generate_bitstream/Top.sbit" (_format text) - (_timespec "2024-05-10T16:41:05") + (_timespec "2024-08-05T13:54:12") ) (_file "generate_bitstream/Top.smsk" (_format text) - (_timespec "2024-05-10T16:41:05") + (_timespec "2024-08-05T13:54:12") ) (_file "generate_bitstream/Top.bgr" (_format text) - (_timespec "2024-05-10T16:41:05") + (_timespec "2024-08-05T13:54:12") ) (_file "generate_bitstream/bgr.db" (_format text) - (_timespec "2024-05-10T16:41:06") + (_timespec "2024-08-05T13:54:14") ) ) )