From 9a5ead9812334b2ddd01420826b09d660e3b5235 Mon Sep 17 00:00:00 2001 From: zhaohe Date: Sun, 10 Mar 2024 20:16:13 +0800 Subject: [PATCH] update --- camera_light_src_timing_controller_fpga.fdc | 4 +- camera_light_src_timing_controller_fpga.pds | 114 ++++++++++++-- pin.csv | 4 +- source/src/output/light_src_ctrl.v | 18 ++- source/src/top.v | 223 +++++++++++++++++++++++++++- 5 files changed, 340 insertions(+), 23 deletions(-) diff --git a/camera_light_src_timing_controller_fpga.fdc b/camera_light_src_timing_controller_fpga.fdc index 1b941bf..06b1a44 100644 --- a/camera_light_src_timing_controller_fpga.fdc +++ b/camera_light_src_timing_controller_fpga.fdc @@ -197,13 +197,13 @@ define_attribute {p:debug_bus[9]} {PAP_IO_STANDARD} {LVCMOS33} define_attribute {p:debug_bus[9]} {PAP_IO_DRIVE} {4} define_attribute {p:debug_bus[9]} {PAP_IO_SLEW} {SLOW} define_attribute {p:debug_bus[10]} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:debug_bus[10]} {PAP_IO_LOC} {D17} +define_attribute {p:debug_bus[10]} {PAP_IO_LOC} {D18} define_attribute {p:debug_bus[10]} {PAP_IO_VCCIO} {3.3} define_attribute {p:debug_bus[10]} {PAP_IO_STANDARD} {LVCMOS33} define_attribute {p:debug_bus[10]} {PAP_IO_DRIVE} {4} define_attribute {p:debug_bus[10]} {PAP_IO_SLEW} {SLOW} define_attribute {p:debug_bus[11]} {PAP_IO_DIRECTION} {OUTPUT} -define_attribute {p:debug_bus[11]} {PAP_IO_LOC} {D18} +define_attribute {p:debug_bus[11]} {PAP_IO_LOC} {D17} define_attribute {p:debug_bus[11]} {PAP_IO_VCCIO} {3.3} define_attribute {p:debug_bus[11]} {PAP_IO_STANDARD} {LVCMOS33} define_attribute {p:debug_bus[11]} {PAP_IO_DRIVE} {4} diff --git a/camera_light_src_timing_controller_fpga.pds b/camera_light_src_timing_controller_fpga.pds index 95f690d..3513e93 100644 --- a/camera_light_src_timing_controller_fpga.pds +++ b/camera_light_src_timing_controller_fpga.pds @@ -1,5 +1,5 @@ (_flow fab_demo "2021.1-SP7" - (_comment "Generated by Fabric Compiler (version on 2021.1-SP7) at Sun Mar 10 19:15:07 2024") + (_comment "Generated by Fabric Compiler (version on 2021.1-SP7) at Sun Mar 10 19:57:45 2024") (_version "1.0.5") (_status "initial") (_project @@ -19,7 +19,7 @@ (_input (_file "source/src/top.v" + "Top:" (_format verilog) - (_timespec "2024-03-10T18:51:24") + (_timespec "2024-03-10T19:56:30") ) (_file "source/src/spi_reg_reader.v" (_format verilog) @@ -195,7 +195,7 @@ ) (_file "source/src/output/light_src_ctrl.v" (_format verilog) - (_timespec "2024-03-10T19:06:04") + (_timespec "2024-03-10T19:37:57") ) (_file "source/src/output/ttl_output_ctrl.v" (_format verilog) @@ -228,7 +228,7 @@ (_input (_file "camera_light_src_timing_controller_fpga.fdc" (_format fdc) - (_timespec "2024-03-10T12:30:51") + (_timespec "2024-03-10T19:50:39") ) ) ) @@ -279,17 +279,17 @@ (_db_output (_file "compile/Top_comp.adf" (_format adif) - (_timespec "2024-03-10T19:15:06") + (_timespec "2024-03-10T19:56:56") ) ) (_output (_file "compile/Top.cmr" (_format verilog) - (_timespec "2024-03-10T19:15:05") + (_timespec "2024-03-10T19:56:55") ) (_file "compile/cmr.db" (_format text) - (_timespec "2024-03-10T19:15:06") + (_timespec "2024-03-10T19:56:57") ) ) ) @@ -299,9 +299,29 @@ ) (_task tsk_synthesis (_command cmd_synthesize - (_gci_state (_integer 0)) + (_gci_state (_integer 2)) (_option ads (_switch ON)) (_option selected_syn_tool_opt (_integer 2)) + (_db_output + (_file "synthesize/Top_syn.adf" + (_format adif) + (_timespec "2024-03-10T19:57:12") + ) + ) + (_output + (_file "synthesize/Top_syn.vm" + (_format structural_verilog) + (_timespec "2024-03-10T19:57:12") + ) + (_file "synthesize/Top.snr" + (_format text) + (_timespec "2024-03-10T19:57:13") + ) + (_file "synthesize/snr.db" + (_format text) + (_timespec "2024-03-10T19:57:13") + ) + ) ) (_widget wgt_tech_view (_attribute _click_to_run (_switch ON)) @@ -316,14 +336,34 @@ ) (_task tsk_devmap (_command cmd_devmap - (_gci_state (_integer 0)) + (_gci_state (_integer 2)) + (_db_output + (_file "device_map/Top_map.adf" + (_format adif) + (_timespec "2024-03-10T19:57:16") + ) + ) + (_output + (_file "device_map/Top_dmr.prt" + (_format text) + (_timespec "2024-03-10T19:57:15") + ) + (_file "device_map/Top.dmr" + (_format text) + (_timespec "2024-03-10T19:57:16") + ) + (_file "device_map/dmr.db" + (_format text) + (_timespec "2024-03-10T19:57:16") + ) + ) ) (_widget wgt_edit_placement_cons (_attribute _click_to_run (_switch ON)) (_input (_file "device_map/camera_light_src_timing_controller_fpga.pcf" (_format pcf) - (_timespec "2024-03-10T19:13:18") + (_timespec "2024-03-10T19:57:16") ) ) ) @@ -333,8 +373,40 @@ ) (_task tsk_pnr (_command cmd_pnr - (_gci_state (_integer 0)) + (_gci_state (_integer 2)) (_option mode (_string "fast")) + (_db_output + (_file "place_route/Top_pnr.adf" + (_format adif) + (_timespec "2024-03-10T19:57:33") + ) + ) + (_output + (_file "place_route/Top.prr" + (_format text) + (_timespec "2024-03-10T19:57:33") + ) + (_file "place_route/Top_prr.prt" + (_format text) + (_timespec "2024-03-10T19:57:33") + ) + (_file "place_route/clock_utilization.txt" + (_format text) + (_timespec "2024-03-10T19:57:33") + ) + (_file "place_route/Top_plc.adf" + (_format adif) + (_timespec "2024-03-10T19:57:23") + ) + (_file "place_route/Top_pnr.netlist" + (_format text) + (_timespec "2024-03-10T19:57:33") + ) + (_file "place_route/prr.db" + (_format text) + (_timespec "2024-03-10T19:57:34") + ) + ) ) (_widget wgt_power_calculator (_attribute _click_to_run (_switch ON)) @@ -363,7 +435,25 @@ ) (_task tsk_gen_bitstream (_command cmd_gen_bitstream - (_gci_state (_integer 0)) + (_gci_state (_integer 2)) + (_output + (_file "generate_bitstream/Top.sbit" + (_format text) + (_timespec "2024-03-10T19:57:45") + ) + (_file "generate_bitstream/Top.smsk" + (_format text) + (_timespec "2024-03-10T19:57:45") + ) + (_file "generate_bitstream/Top.bgr" + (_format text) + (_timespec "2024-03-10T19:57:45") + ) + (_file "generate_bitstream/bgr.db" + (_format text) + (_timespec "2024-03-10T19:57:45") + ) + ) ) ) ) diff --git a/pin.csv b/pin.csv index 87ee38d..160e125 100644 --- a/pin.csv +++ b/pin.csv @@ -38,8 +38,8 @@ H14,debug_bus[6],OUTPUT H13,debug_bus[7],OUTPUT E17,debug_bus[8],OUTPUT E18,debug_bus[9],OUTPUT -D17,debug_bus[10],OUTPUT -D18,debug_bus[11],OUTPUT +D18,debug_bus[10],OUTPUT +D17,debug_bus[11],OUTPUT A16,debug_bus[12],OUTPUT B16,debug_bus[13],OUTPUT A15,debug_bus[14],OUTPUT diff --git a/source/src/output/light_src_ctrl.v b/source/src/output/light_src_ctrl.v index 16a3307..14f5b77 100644 --- a/source/src/output/light_src_ctrl.v +++ b/source/src/output/light_src_ctrl.v @@ -74,8 +74,8 @@ module light_src_ctrl #( //!寄存器写入逻辑 - localparam pluse_interval_init_val = 1 * (SYS_CLOCK_FREQ / 1000000); //1us - localparam pluse_width_initval = 30 * (SYS_CLOCK_FREQ / 1000000); //1us + localparam pluse_interval_init_val = 1 * (SYS_CLOCK_FREQ / 32'd1000_000); //1us + localparam pluse_width_initval = 30 * (SYS_CLOCK_FREQ / 32'd1000_000); //1us always @(posedge clk or negedge rst_n) begin if (!rst_n) begin @@ -87,8 +87,8 @@ module light_src_ctrl #( reg6_trigger_mode_pluse_width <= pluse_width_initval; reg7_trigger_mode_first_pluse_offset <= pluse_interval_init_val * ID + ((ID - 1) * pluse_width_initval); reg8_trigger_mode_output_polarity <= 1; - reg9_light_intensity_cnt <= (SYS_CLOCK_FREQ / 100000 / 2); //100k - regA_light_driver_freq_cnt <= (SYS_CLOCK_FREQ / 100000); //100k + reg9_light_intensity_cnt <= (SYS_CLOCK_FREQ / 30000 / 10); //100k + regA_light_driver_freq_cnt <= (SYS_CLOCK_FREQ / 30000); //100k regC_freq_detect_bias <= `FREQ_DETECT_BIAS_DEFAULT; end else begin if (reg_wr_sig) begin @@ -113,6 +113,7 @@ module light_src_ctrl #( wire signal_in_choose; //!选中的信号 + wire signal_in_choose_rsing_edge; //!选中的信号 wire signal_en_output; //!EN信号输出 wire signal_lt_intensity; //!光强输出 @@ -123,6 +124,13 @@ module light_src_ctrl #( .signalout (signal_in_choose) ); + zutils_edge_detecter edge_detecter ( + .clk (clk), + .rst_n (rst_n), + .in_signal (signal_in_choose), + .in_signal_rising_edge(signal_in_choose_rsing_edge) + ); + zutils_pluse_generator_v2 pluse_generator ( .clk (clk), @@ -130,7 +138,7 @@ module light_src_ctrl #( .pluse_width (reg6_trigger_mode_pluse_width), .pluse_delay (reg7_trigger_mode_first_pluse_offset), - .trigger (signal_in_choose), + .trigger (signal_in_choose_rsing_edge), .output_signal(signal_en_output) ); diff --git a/source/src/top.v b/source/src/top.v index 1dc73a8..096e706 100644 --- a/source/src/top.v +++ b/source/src/top.v @@ -230,6 +230,99 @@ module Top ( .out_trigger_sig_index3(sig_bus[`SIG_INTERNAL_CLK_I4]) ); + + + + trigger_source_base_module #( + .REG_START_ADD (`REGADDOFF__TRIGGER_IN1), + .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ) + ) trigger_in1 ( + .clk (sys_clk), + .rst_n(sys_rst_n), + + .addr (RegReaderBus_addr), + .wr_data(RegReaderBus_wr_data), + .wr_en (RegReaderBus_wr_en), + .rd_data(rd_data_trigger_in1), + + .in_sig_0(optocoupler_in1), + .in_sig_1(diff_in1), + + .out_trigger_sig (sig_bus[`SIG_EXT_TRIGGER_1]), + .out_trigger_sig_index0(sig_bus[`SIG_EXT_TRIGGER_1_I1]), + .out_trigger_sig_index1(sig_bus[`SIG_EXT_TRIGGER_1_I2]), + .out_trigger_sig_index2(sig_bus[`SIG_EXT_TRIGGER_1_I3]), + .out_trigger_sig_index3(sig_bus[`SIG_EXT_TRIGGER_1_I4]) + ); + + + + trigger_source_base_module #( + .REG_START_ADD (`REGADDOFF__TRIGGER_IN1), + .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ) + ) trigger_in2 ( + .clk (sys_clk), + .rst_n(sys_rst_n), + + .addr (RegReaderBus_addr), + .wr_data(RegReaderBus_wr_data), + .wr_en (RegReaderBus_wr_en), + .rd_data(rd_data_trigger_in2), + + .in_sig_0(optocoupler_in2), + .in_sig_1(diff_in2), + + .out_trigger_sig (sig_bus[`SIG_EXT_TRIGGER_2]), + .out_trigger_sig_index0(sig_bus[`SIG_EXT_TRIGGER_2_I1]), + .out_trigger_sig_index1(sig_bus[`SIG_EXT_TRIGGER_2_I2]), + .out_trigger_sig_index2(sig_bus[`SIG_EXT_TRIGGER_2_I3]), + .out_trigger_sig_index3(sig_bus[`SIG_EXT_TRIGGER_2_I4]) + ); + + trigger_source_base_module #( + .REG_START_ADD (`REGADDOFF__TRIGGER_IN1), + .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ) + ) trigger_in3 ( + .clk (sys_clk), + .rst_n(sys_rst_n), + + .addr (RegReaderBus_addr), + .wr_data(RegReaderBus_wr_data), + .wr_en (RegReaderBus_wr_en), + .rd_data(rd_data_trigger_in3), + + .in_sig_0(optocoupler_in3), + .in_sig_1(diff_in3), + + .out_trigger_sig (sig_bus[`SIG_EXT_TRIGGER_3]), + .out_trigger_sig_index0(sig_bus[`SIG_EXT_TRIGGER_3_I1]), + .out_trigger_sig_index1(sig_bus[`SIG_EXT_TRIGGER_3_I2]), + .out_trigger_sig_index2(sig_bus[`SIG_EXT_TRIGGER_3_I3]), + .out_trigger_sig_index3(sig_bus[`SIG_EXT_TRIGGER_3_I4]) + ); + + trigger_source_base_module #( + .REG_START_ADD (`REGADDOFF__TRIGGER_IN1), + .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ) + ) trigger_in4 ( + .clk (sys_clk), + .rst_n(sys_rst_n), + + .addr (RegReaderBus_addr), + .wr_data(RegReaderBus_wr_data), + .wr_en (RegReaderBus_wr_en), + .rd_data(rd_data_trigger_in4), + + .in_sig_0(optocoupler_in4), + .in_sig_1(diff_in4), + + .out_trigger_sig (sig_bus[`SIG_EXT_TRIGGER_4]), + .out_trigger_sig_index0(sig_bus[`SIG_EXT_TRIGGER_4_I1]), + .out_trigger_sig_index1(sig_bus[`SIG_EXT_TRIGGER_4_I2]), + .out_trigger_sig_index2(sig_bus[`SIG_EXT_TRIGGER_4_I3]), + .out_trigger_sig_index3(sig_bus[`SIG_EXT_TRIGGER_4_I4]) + ); + // ttl_output_ctrl light_src_ctrl #( @@ -243,7 +336,7 @@ module Top ( .addr (RegReaderBus_addr), .wr_data(RegReaderBus_wr_data), .wr_en (RegReaderBus_wr_en), - .rd_data(rd_data_light_ctrol_module4), + .rd_data(rd_data_light_ctrol_module1), .signal_in(sig_bus), @@ -263,7 +356,7 @@ module Top ( .addr (RegReaderBus_addr), .wr_data(RegReaderBus_wr_data), .wr_en (RegReaderBus_wr_en), - .rd_data(rd_data_ttl_output_module4), + .rd_data(rd_data_ttl_output_module1), .sys_internal_sig_bus(sig_bus), .lt_en_sig (lt_en_sig_bus), @@ -272,6 +365,126 @@ module Top ( .optocoupler_out(optocoupler_out1) ); + light_src_ctrl #( + .REG_START_ADD(`REGADDOFF__LIGHT_CTROL_MODULE1), + .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ), + .ID(2) + ) light_src_ctrl_2 ( + .clk (sys_clk), + .rst_n(sys_rst_n), + + .addr (RegReaderBus_addr), + .wr_data(RegReaderBus_wr_data), + .wr_en (RegReaderBus_wr_en), + .rd_data(rd_data_light_ctrol_module2), + + .signal_in(sig_bus), + + .lt_intensity_ctrl(lt2_intensity_ctrl), + .lt_en (lt2_en), + .lt_error_sig_in (lt2_error_sig_in) + ); + + + ttl_output_ctrl #( + .REG_START_ADD (`REGADDOFF__TTL_OUTPUT_MODULE2), + .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ) + ) ttl_output_ctrl_2 ( + .clk (sys_clk), + .rst_n(sys_rst_n), + + .addr (RegReaderBus_addr), + .wr_data(RegReaderBus_wr_data), + .wr_en (RegReaderBus_wr_en), + .rd_data(rd_data_ttl_output_module2), + + .sys_internal_sig_bus(sig_bus), + .lt_en_sig (lt_en_sig_bus), + + .diff_out (diff_out2), + .optocoupler_out(optocoupler_out2) + ); + + light_src_ctrl #( + .REG_START_ADD(`REGADDOFF__LIGHT_CTROL_MODULE1), + .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ), + .ID(3) + ) light_src_ctrl_3 ( + .clk (sys_clk), + .rst_n(sys_rst_n), + + .addr (RegReaderBus_addr), + .wr_data(RegReaderBus_wr_data), + .wr_en (RegReaderBus_wr_en), + .rd_data(rd_data_light_ctrol_module3), + + .signal_in(sig_bus), + + .lt_intensity_ctrl(lt3_intensity_ctrl), + .lt_en (lt3_en), + .lt_error_sig_in (lt3_error_sig_in) + ); + + + ttl_output_ctrl #( + .REG_START_ADD (`REGADDOFF__TTL_OUTPUT_MODULE3), + .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ) + ) ttl_output_ctrl_3 ( + .clk (sys_clk), + .rst_n(sys_rst_n), + + .addr (RegReaderBus_addr), + .wr_data(RegReaderBus_wr_data), + .wr_en (RegReaderBus_wr_en), + .rd_data(rd_data_ttl_output_module3), + + .sys_internal_sig_bus(sig_bus), + .lt_en_sig (lt_en_sig_bus), + + .diff_out (diff_out3), + .optocoupler_out(optocoupler_out3) + ); + + light_src_ctrl #( + .REG_START_ADD(`REGADDOFF__LIGHT_CTROL_MODULE1), + .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ), + .ID(4) + ) light_src_ctrl_4 ( + .clk (sys_clk), + .rst_n(sys_rst_n), + + .addr (RegReaderBus_addr), + .wr_data(RegReaderBus_wr_data), + .wr_en (RegReaderBus_wr_en), + .rd_data(rd_data_light_ctrol_module4), + + .signal_in(sig_bus), + + .lt_intensity_ctrl(lt4_intensity_ctrl), + .lt_en (lt4_en), + .lt_error_sig_in (lt4_error_sig_in) + ); + + + ttl_output_ctrl #( + .REG_START_ADD (`REGADDOFF__TTL_OUTPUT_MODULE4), + .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ) + ) ttl_output_ctrl_4 ( + .clk (sys_clk), + .rst_n(sys_rst_n), + + .addr (RegReaderBus_addr), + .wr_data(RegReaderBus_wr_data), + .wr_en (RegReaderBus_wr_en), + .rd_data(rd_data_ttl_output_module4), + + .sys_internal_sig_bus(sig_bus), + .lt_en_sig (lt_en_sig_bus), + + .diff_out (diff_out4), + .optocoupler_out(optocoupler_out4) + ); + assign debug_bus[0] = internal_trigger_clk_ins_output_sig; assign debug_bus[1] = sig_bus[`SIG_INTERNAL_CLK]; @@ -286,6 +499,12 @@ module Top ( assign debug_bus[9] = optocoupler_out1; assign debug_bus[10] = diff_out1; + assign debug_bus[11] = lt1_en; + assign debug_bus[12] = lt2_en; + assign debug_bus[13] = lt3_en; + assign debug_bus[14] = lt4_en; + + // assign debug_bus[0] = sys_clk; // assign optocoupler_out1 = diff_in1;