26 changed files with 443 additions and 1151 deletions
-
2led_test.fdc
-
180led_test.pds
-
0source/src/input/src_genlock.v
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0source/src/input/src_timecode.v
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0source/src/input/src_ttl_parser.v
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18source/src/monitor_line.v
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4source/src/rd_data_router.v
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16source/src/spi_reg_reader.v
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76source/src/transmitter.v
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157source/src/uart_reg_reader.v
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172source/src/uart_rx.v
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161source/src/uart_tx.v
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0source/src/zutils/baud_rate_gen.v
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8source/src/zutils/zutils_clk_parser.v
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2source/src/zutils/zutils_debug_led.v
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24source/src/zutils/zutils_edge_detecter.v
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4source/src/zutils/zutils_multiplexer_16t1.v
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4source/src/zutils/zutils_multiplexer_4t1.v
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6source/src/zutils/zutils_pluse_generator.v
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8source/src/zutils/zutils_pwm_generator.v
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7source/src/zutils/zutils_register.v
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5source/src/zutils/zutils_signal_filter.v
@ -1,18 +0,0 @@ |
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/* |
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* Hacky baud rate generator to divide a 50MHz clock into a 115200 baud |
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* rx/tx pair where the rx clcken oversamples by 16x. |
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*/ |
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module monitor_line ( |
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input wire clk_50m, |
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input wire rst_n, |
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input wire in, |
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output reg out |
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); |
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|
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|
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always @(posedge clk_50m or negedge rst_n) begin |
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if (!rst_n) out <= 1'b0; |
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else out <= in; |
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end |
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|
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endmodule |
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@ -1,76 +0,0 @@ |
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module transmitter ( |
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input wire [7:0] din, |
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input wire wr_en, |
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input wire clk_50m, |
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input wire clken, |
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input wire rest_n, |
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output reg tx, |
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output wire tx_busy, |
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output wire [1:0] t_state, |
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output wire [2:0] t_bitpos, |
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output wire t_worksignal |
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); |
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parameter STATE_IDLE = 2'b00; |
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parameter STATE_START = 2'b01; |
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parameter STATE_DATA = 2'b10; |
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parameter STATE_STOP = 2'b11; |
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initial begin |
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tx = 1'b1; |
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end |
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|
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|
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reg [7:0] data = 8'h00; |
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reg [2:0] bitpos = 3'h0; |
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reg [1:0] state = STATE_IDLE; |
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reg worksignal = 0; |
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|
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assign workflag = (state != STATE_IDLE); |
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|
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always @(posedge clken, posedge wr_en) begin |
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if (wr_en) begin |
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worksignal <= 1'b1; |
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data <= din; |
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end else begin |
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if (!workflag) worksignal <= 1'b0; |
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end |
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end |
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|
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|
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always @(posedge clken or negedge rest_n) begin |
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if (!rest_n) begin |
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state <= STATE_IDLE; |
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end else begin |
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case (state) |
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STATE_IDLE: begin |
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tx <= 1'b1; |
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if (worksignal) begin |
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state <= STATE_START; |
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bitpos <= 0; |
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end |
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end |
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STATE_START: begin |
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tx <= 1'b0; |
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state <= STATE_DATA; |
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end |
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STATE_DATA: begin |
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if (bitpos == 3'h7) state <= STATE_STOP; |
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else bitpos <= bitpos + 3'h1; |
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tx <= data[bitpos]; |
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end |
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STATE_STOP: begin |
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tx <= 1'b1; |
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state <= STATE_IDLE; |
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end |
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default begin |
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tx <= 1'b1; |
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state <= STATE_IDLE; |
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end |
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endcase |
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end |
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end |
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|
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assign tx_busy = (state != STATE_IDLE); |
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assign t_state = state; |
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assign t_bitpos = bitpos; |
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assign t_worksignal = worksignal; |
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endmodule |
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@ -1,157 +0,0 @@ |
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module uart_reg_reader #( |
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parameter CLK_FRE = 50, //clock frequency(Mhz) |
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parameter BAUD_RATE = 115200 //serial baud rate |
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) ( |
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input clk, //clock input |
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input rst_n, //asynchronous reset input, low active |
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input wire [31:0] reg_data, //received serial data |
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output reg [31:0] reg_add, |
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output reg reg_add_valid, |
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input wire uart_rx_pin, |
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output wire uart_tx_pin |
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); |
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// |
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// overtime |
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// |----------------------^ |
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// v | |
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// IDLE ---------------> READ REG ADD ---------------> READ_REG ---------------> SEND_REG_DATA |
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// ^ | |
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// |------------------------------------------------------------------------------------v |
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// |
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// |
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// |
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// |
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parameter STATE_IDLE = 0; |
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parameter STATE_READ_REG_ADD = 1; |
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parameter STATE_READ_REG = 2; |
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parameter STATE_SEND_REG_DATA = 3; |
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parameter STATE_WAIT_SEND_END = 4; |
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|
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wire [7:0] rx_data; |
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wire rx_data_valid; |
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wire rx_data_ready; |
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|
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wire tx_data_ready; |
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reg [7:0] tx_data = 0; |
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reg tx_data_valid = 0; |
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|
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reg [7:0] state = 0; |
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reg [7:0] rxpacket_num = 0; |
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reg [7:0] txpacket_num = 0; |
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reg [7:0] rxdatacache = 0; //接收数据buffer |
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|
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uart_rx #( |
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.CLK_FRE (CLK_FRE), |
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.BAUD_RATE(BAUD_RATE) |
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) uart_rx_impl ( |
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.clk (clk), // input |
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.rst_n (rst_n), // input |
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.rx_data (rx_data), // output |
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.rx_data_valid(rx_data_valid), // output |
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.rx_data_ready(rx_data_ready), // input |
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.rx_pin (uart_rx_pin) // input |
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); |
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|
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uart_tx #( |
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.CLK_FRE (CLK_FRE), |
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.BAUD_RATE(BAUD_RATE) |
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) uart_tx_impl ( |
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.clk (clk), // input |
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.rst_n (rst_n), // input |
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.tx_data (tx_data), // input |
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.tx_data_valid(tx_data_valid), // input |
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.tx_data_ready(tx_data_ready), // output |
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.tx_pin (uart_tx_pin) // output |
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); |
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|
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|
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assign rx_data_ready = 1'b1; |
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reg [ 7:0] substep = 0; |
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reg [31:0] reg_data_cache = 0; |
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|
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|
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always @(posedge clk or negedge rst_n) begin |
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if (!rst_n) begin |
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state <= STATE_IDLE; |
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rxpacket_num <= 0; |
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txpacket_num <= 0; |
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substep <= 0; |
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reg_add <= 0; |
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reg_add_valid <= 0; |
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end else begin |
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case (state) |
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STATE_IDLE: begin |
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rxpacket_num <= 0; |
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txpacket_num <= 0; |
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substep <= 0; |
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state <= STATE_READ_REG_ADD; |
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end |
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STATE_READ_REG_ADD: begin |
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if (rxpacket_num == 1) begin |
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state <= STATE_READ_REG; |
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end else if (rx_data_valid) begin |
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rxdatacache <= rx_data; |
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rxpacket_num <= rxpacket_num + 1; |
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end |
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end |
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STATE_READ_REG: begin |
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case (substep) |
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0: begin |
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reg_add_valid <= 1; |
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reg_add[7:0] <= rxdatacache; |
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substep <= 1; |
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end |
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1: begin |
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tx_data_valid <= 0; |
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substep <= 0; |
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state <= STATE_SEND_REG_DATA; |
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end |
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endcase |
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end |
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STATE_SEND_REG_DATA: begin |
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case (substep) |
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0: begin |
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case (txpacket_num) |
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0: begin |
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tx_data[7:0] <= reg_data_cache[7:0]; |
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end |
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1: begin |
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tx_data[7:0] <= reg_data_cache[15:8]; |
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end |
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2: begin |
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tx_data[7:0] <= reg_data_cache[23:16]; |
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end |
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3: begin |
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tx_data[7:0] <= reg_data_cache[31:24]; |
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end |
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default: begin |
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tx_data[7:0] <= 0; |
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end |
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endcase |
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tx_data_valid <= 1; |
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txpacket_num <= txpacket_num + 1; |
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substep <= 1; |
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end |
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1: begin |
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tx_data_valid <= 0; |
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substep <= 2; |
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end |
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2: begin |
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if (tx_data_ready) begin |
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if (txpacket_num != 4) begin |
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substep <= 0; |
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end else begin |
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substep <= 0; |
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state <= STATE_IDLE; |
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end |
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end |
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end |
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endcase |
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end |
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default begin |
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state <= STATE_IDLE; |
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end |
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endcase |
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end |
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end |
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endmodule |
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@ -1,172 +0,0 @@ |
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////////////////////////////////////////////////////////////////////////////////// |
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// // |
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// // |
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// Author: meisq // |
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// msq@qq.com // |
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// ALINX(shanghai) Technology Co.,Ltd // |
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// heijin // |
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// WEB: http://www.alinx.cn/ // |
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// BBS: http://www.heijin.org/ // |
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// // |
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////////////////////////////////////////////////////////////////////////////////// |
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// // |
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// Copyright (c) 2017,ALINX(shanghai) Technology Co.,Ltd // |
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// All rights reserved // |
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// // |
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// This source file may be used and distributed without restriction provided // |
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// that this copyright statement is not removed from the file and that any // |
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// derivative work contains the original copyright notice and the associated // |
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// disclaimer. // |
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// // |
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////////////////////////////////////////////////////////////////////////////////// |
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|
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//================================================================================ |
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// Revision History: |
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// Date By Revision Change Description |
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//-------------------------------------------------------------------------------- |
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//2017/8/1 1.0 Original |
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//*******************************************************************************/ |
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module uart_rx |
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#( |
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parameter CLK_FRE = 50, //clock frequency(Mhz) |
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parameter BAUD_RATE = 115200 //serial baud rate |
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) |
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( |
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input clk, //clock input |
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input rst_n, //asynchronous reset input, low active |
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output reg[7:0] rx_data, //received serial data |
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output reg rx_data_valid, //received serial data is valid |
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input rx_data_ready, //data receiver module ready |
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input rx_pin //serial data input |
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); |
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//calculates the clock cycle for baud rate |
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localparam CYCLE = CLK_FRE * 1000000 / BAUD_RATE; |
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//state machine code |
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localparam S_IDLE = 1; |
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localparam S_START = 2; //start bit |
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localparam S_REC_BYTE = 3; //data bits |
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localparam S_STOP = 4; //stop bit |
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localparam S_DATA = 5; |
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|
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reg[2:0] state; |
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reg[2:0] next_state; |
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reg rx_d0; //delay 1 clock for rx_pin |
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reg rx_d1; //delay 1 clock for rx_d0 |
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wire rx_negedge; //negedge of rx_pin |
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reg[7:0] rx_bits; //temporary storage of received data |
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reg[15:0] cycle_cnt; //baud counter |
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reg[2:0] bit_cnt; //bit counter |
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|
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assign |
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rx_negedge = rx_d1 && ~rx_d0; |
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|
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always@(posedge clk or negedge rst_n) |
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begin |
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if(rst_n == 1'b0) |
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begin |
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rx_d0 <= 1'b0; |
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rx_d1 <= 1'b0; |
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end |
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else |
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begin |
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rx_d0 <= rx_pin; |
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rx_d1 <= rx_d0; |
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end |
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end |
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|
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|
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always@(posedge clk or negedge rst_n) |
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begin |
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if(rst_n == 1'b0) |
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state <= S_IDLE; |
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else |
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state <= next_state; |
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end |
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|
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always@(*) |
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begin |
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case(state) |
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S_IDLE: |
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if(rx_negedge) |
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next_state <= S_START; |
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else |
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next_state <= S_IDLE; |
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S_START: |
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if(cycle_cnt == CYCLE - 1)//one data cycle |
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next_state <= S_REC_BYTE; |
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else |
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next_state <= S_START; |
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S_REC_BYTE: |
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if(cycle_cnt == CYCLE - 1 && bit_cnt == 3'd7) //receive 8bit data |
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next_state <= S_STOP; |
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else |
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next_state <= S_REC_BYTE; |
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S_STOP: |
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if(cycle_cnt == CYCLE/2 - 1)//half bit cycle,to avoid missing the next byte receiver |
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next_state <= S_DATA; |
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else |
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next_state <= S_STOP; |
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S_DATA: |
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if(rx_data_ready) //data receive complete |
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next_state <= S_IDLE; |
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else |
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next_state <= S_DATA; |
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default: |
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next_state <= S_IDLE; |
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endcase |
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end |
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|
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always@(posedge clk or negedge rst_n) |
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begin |
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if(rst_n == 1'b0) |
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rx_data_valid <= 1'b0; |
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else if(state == S_STOP && next_state != state) |
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rx_data_valid <= 1'b1; |
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else if(state == S_DATA && rx_data_ready) |
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rx_data_valid <= 1'b0; |
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end |
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|
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always@(posedge clk or negedge rst_n) |
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begin |
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if(rst_n == 1'b0) |
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rx_data <= 8'd0; |
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else if(state == S_STOP && next_state != state) |
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rx_data <= rx_bits;//latch received data |
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end |
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|
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always@(posedge clk or negedge rst_n) |
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begin |
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if(rst_n == 1'b0) |
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begin |
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bit_cnt <= 3'd0; |
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end |
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else if(state == S_REC_BYTE) |
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if(cycle_cnt == CYCLE - 1) |
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bit_cnt <= bit_cnt + 3'd1; |
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else |
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bit_cnt <= bit_cnt; |
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else |
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bit_cnt <= 3'd0; |
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end |
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|
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|
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always@(posedge clk or negedge rst_n) |
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begin |
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if(rst_n == 1'b0) |
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cycle_cnt <= 16'd0; |
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else if((state == S_REC_BYTE && cycle_cnt == CYCLE - 1) || next_state != state) |
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cycle_cnt <= 16'd0; |
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else |
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cycle_cnt <= cycle_cnt + 16'd1; |
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end |
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//receive serial data bit data |
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always@(posedge clk or negedge rst_n) |
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begin |
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if(rst_n == 1'b0) |
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rx_bits <= 8'd0; |
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else if(state == S_REC_BYTE && cycle_cnt == CYCLE/2 - 1) |
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rx_bits[bit_cnt] <= rx_pin; |
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else |
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rx_bits <= rx_bits; |
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end |
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endmodule |
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@ -1,161 +0,0 @@ |
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////////////////////////////////////////////////////////////////////////////////// |
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// // |
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// // |
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// Author: meisq // |
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// msq@qq.com // |
|||
// ALINX(shanghai) Technology Co.,Ltd // |
|||
// heijin // |
|||
// WEB: http://www.alinx.cn/ // |
|||
// BBS: http://www.heijin.org/ // |
|||
// // |
|||
////////////////////////////////////////////////////////////////////////////////// |
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// // |
|||
// Copyright (c) 2017,ALINX(shanghai) Technology Co.,Ltd // |
|||
// All rights reserved // |
|||
// // |
|||
// This source file may be used and distributed without restriction provided // |
|||
// that this copyright statement is not removed from the file and that any // |
|||
// derivative work contains the original copyright notice and the associated // |
|||
// disclaimer. // |
|||
// // |
|||
////////////////////////////////////////////////////////////////////////////////// |
|||
|
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//================================================================================ |
|||
// Revision History: |
|||
// Date By Revision Change Description |
|||
//-------------------------------------------------------------------------------- |
|||
//2017/8/1 1.0 Original |
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//*******************************************************************************/ |
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module uart_tx |
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#( |
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parameter CLK_FRE = 50, //clock frequency(Mhz) |
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parameter BAUD_RATE = 115200 //serial baud rate |
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) |
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( |
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input clk, //clock input |
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input rst_n, //asynchronous reset input, low active |
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input[7:0] tx_data, //data to send |
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input tx_data_valid, //data to be sent is valid |
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output reg tx_data_ready, //send ready |
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output tx_pin //serial data output |
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); |
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//calculates the clock cycle for baud rate |
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localparam CYCLE = CLK_FRE * 1000000 / BAUD_RATE; |
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//state machine code |
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localparam S_IDLE = 1; |
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localparam S_START = 2;//start bit |
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localparam S_SEND_BYTE = 3;//data bits |
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localparam S_STOP = 4;//stop bit |
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reg[2:0] state; |
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reg[2:0] next_state; |
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reg[15:0] cycle_cnt; //baud counter |
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reg[2:0] bit_cnt;//bit counter |
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reg[7:0] tx_data_latch; //latch data to send |
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reg tx_reg; //serial data output |
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assign tx_pin = tx_reg; |
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always@(posedge clk or negedge rst_n) |
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begin |
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if(rst_n == 1'b0) |
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state <= S_IDLE; |
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else |
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state <= next_state; |
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end |
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|
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always@(*) |
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begin |
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case(state) |
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S_IDLE: |
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if(tx_data_valid == 1'b1) |
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next_state <= S_START; |
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else |
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next_state <= S_IDLE; |
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S_START: |
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if(cycle_cnt == CYCLE - 1) |
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next_state <= S_SEND_BYTE; |
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else |
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next_state <= S_START; |
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S_SEND_BYTE: |
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if(cycle_cnt == CYCLE - 1 && bit_cnt == 3'd7) |
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next_state <= S_STOP; |
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else |
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next_state <= S_SEND_BYTE; |
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S_STOP: |
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if(cycle_cnt == CYCLE - 1) |
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next_state <= S_IDLE; |
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else |
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next_state <= S_STOP; |
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default: |
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next_state <= S_IDLE; |
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endcase |
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end |
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always@(posedge clk or negedge rst_n) |
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begin |
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if(rst_n == 1'b0) |
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begin |
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tx_data_ready <= 1'b0; |
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end |
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else if(state == S_IDLE) |
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if(tx_data_valid == 1'b1) |
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tx_data_ready <= 1'b0; |
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else |
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tx_data_ready <= 1'b1; |
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else if(state == S_STOP && cycle_cnt == CYCLE - 1) |
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tx_data_ready <= 1'b1; |
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end |
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|
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|
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always@(posedge clk or negedge rst_n) |
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begin |
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if(rst_n == 1'b0) |
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begin |
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tx_data_latch <= 8'd0; |
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end |
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else if(state == S_IDLE && tx_data_valid == 1'b1) |
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tx_data_latch <= tx_data; |
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|
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end |
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|
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always@(posedge clk or negedge rst_n) |
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begin |
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if(rst_n == 1'b0) |
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begin |
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bit_cnt <= 3'd0; |
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end |
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else if(state == S_SEND_BYTE) |
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if(cycle_cnt == CYCLE - 1) |
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bit_cnt <= bit_cnt + 3'd1; |
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else |
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bit_cnt <= bit_cnt; |
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else |
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bit_cnt <= 3'd0; |
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end |
|||
|
|||
|
|||
always@(posedge clk or negedge rst_n) |
|||
begin |
|||
if(rst_n == 1'b0) |
|||
cycle_cnt <= 16'd0; |
|||
else if((state == S_SEND_BYTE && cycle_cnt == CYCLE - 1) || next_state != state) |
|||
cycle_cnt <= 16'd0; |
|||
else |
|||
cycle_cnt <= cycle_cnt + 16'd1; |
|||
end |
|||
|
|||
always@(posedge clk or negedge rst_n) |
|||
begin |
|||
if(rst_n == 1'b0) |
|||
tx_reg <= 1'b1; |
|||
else |
|||
case(state) |
|||
S_IDLE,S_STOP: |
|||
tx_reg <= 1'b1; |
|||
S_START: |
|||
tx_reg <= 1'b0; |
|||
S_SEND_BYTE: |
|||
tx_reg <= tx_data_latch[bit_cnt]; |
|||
default: |
|||
tx_reg <= 1'b1; |
|||
endcase |
|||
end |
|||
|
|||
endmodule |
|||
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