diff --git a/led_test.pds b/led_test.pds index 7fc7a7c..0faf20a 100644 --- a/led_test.pds +++ b/led_test.pds @@ -1,5 +1,5 @@ (_flow fab_demo "2021.1-SP7" - (_comment "Generated by Fabric Compiler (version on 2021.1-SP7) at Tue Mar 5 23:58:26 2024") + (_comment "Generated by Fabric Compiler (version on 2021.1-SP7) at Wed Mar 6 00:21:26 2024") (_version "1.0.5") (_status "initial") (_project @@ -211,7 +211,7 @@ ) (_file "source/src/business/record_sig_generator.v" (_format verilog) - (_timespec "2024-03-05T23:58:23") + (_timespec "2024-03-06T00:10:36") ) ) ) @@ -279,21 +279,21 @@ ) (_task tsk_compile (_command cmd_compile - (_gci_state (_integer 3)) + (_gci_state (_integer 2)) (_db_output (_file "compile/Top_comp.adf" (_format adif) - (_timespec "2024-03-05T23:56:26") + (_timespec "2024-03-06T00:17:50") ) ) (_output (_file "compile/Top.cmr" (_format verilog) - (_timespec "2024-03-05T23:56:23") + (_timespec "2024-03-06T00:17:48") ) (_file "compile/cmr.db" (_format text) - (_timespec "2024-03-05T23:56:26") + (_timespec "2024-03-06T00:17:50") ) ) ) @@ -303,27 +303,27 @@ ) (_task tsk_synthesis (_command cmd_synthesize - (_gci_state (_integer 3)) + (_gci_state (_integer 2)) (_option ads (_switch ON)) (_option selected_syn_tool_opt (_integer 2)) (_db_output (_file "synthesize/Top_syn.adf" (_format adif) - (_timespec "2024-03-05T23:58:05") + (_timespec "2024-03-06T00:19:28") ) ) (_output (_file "synthesize/Top_syn.vm" (_format structural_verilog) - (_timespec "2024-03-05T23:58:14") + (_timespec "2024-03-06T00:19:37") ) (_file "synthesize/Top.snr" (_format text) - (_timespec "2024-03-05T23:58:20") + (_timespec "2024-03-06T00:19:42") ) (_file "synthesize/snr.db" (_format text) - (_timespec "2024-03-05T23:58:20") + (_timespec "2024-03-06T00:19:42") ) ) ) @@ -340,25 +340,25 @@ ) (_task tsk_devmap (_command cmd_devmap - (_gci_state (_integer 3)) + (_gci_state (_integer 2)) (_db_output (_file "device_map/Top_map.adf" (_format adif) - (_timespec "2024-03-05T23:58:26") + (_timespec "2024-03-06T00:19:47") ) ) (_output (_file "device_map/Top_dmr.prt" (_format text) - (_timespec "2024-03-05T23:58:23") + (_timespec "2024-03-06T00:19:45") ) (_file "device_map/Top.dmr" (_format text) - (_timespec "2024-03-05T23:58:26") + (_timespec "2024-03-06T00:19:47") ) (_file "device_map/dmr.db" (_format text) - (_timespec "2024-03-05T23:58:26") + (_timespec "2024-03-06T00:19:47") ) ) ) @@ -367,7 +367,7 @@ (_input (_file "device_map/led_test.pcf" (_format pcf) - (_timespec "2024-03-05T23:58:26") + (_timespec "2024-03-06T00:19:47") ) ) ) @@ -377,8 +377,40 @@ ) (_task tsk_pnr (_command cmd_pnr - (_gci_state (_integer 0)) + (_gci_state (_integer 2)) (_option mode (_string "fast")) + (_db_output + (_file "place_route/Top_pnr.adf" + (_format adif) + (_timespec "2024-03-06T00:21:07") + ) + ) + (_output + (_file "place_route/Top.prr" + (_format text) + (_timespec "2024-03-06T00:21:07") + ) + (_file "place_route/Top_prr.prt" + (_format text) + (_timespec "2024-03-06T00:21:07") + ) + (_file "place_route/clock_utilization.txt" + (_format text) + (_timespec "2024-03-06T00:21:07") + ) + (_file "place_route/Top_plc.adf" + (_format adif) + (_timespec "2024-03-06T00:20:03") + ) + (_file "place_route/Top_pnr.netlist" + (_format text) + (_timespec "2024-03-06T00:21:07") + ) + (_file "place_route/prr.db" + (_format text) + (_timespec "2024-03-06T00:21:08") + ) + ) ) (_widget wgt_power_calculator (_attribute _click_to_run (_switch ON)) @@ -407,7 +439,25 @@ ) (_task tsk_gen_bitstream (_command cmd_gen_bitstream - (_gci_state (_integer 0)) + (_gci_state (_integer 2)) + (_output + (_file "generate_bitstream/Top.sbit" + (_format text) + (_timespec "2024-03-06T00:21:26") + ) + (_file "generate_bitstream/Top.smsk" + (_format text) + (_timespec "2024-03-06T00:21:26") + ) + (_file "generate_bitstream/Top.bgr" + (_format text) + (_timespec "2024-03-06T00:21:26") + ) + (_file "generate_bitstream/bgr.db" + (_format text) + (_timespec "2024-03-06T00:21:26") + ) + ) ) ) ) diff --git a/source/src/business/record_sig_generator.v b/source/src/business/record_sig_generator.v index d312f98..825b35c 100644 --- a/source/src/business/record_sig_generator.v +++ b/source/src/business/record_sig_generator.v @@ -44,8 +44,8 @@ module record_sig_generator #( reg [31:0] regB_manual_ctrl; //! 手动控制 localparam REGA_MANUAL_CTRL_REG_INDEX = 32'd11; - reg [31:0] regD_start_timecode_snapshot0; //! - reg [31:0] regE_start_timecode_snapshot1; //! + reg [31:0] regD_timecode_snapshot0; //! + reg [31:0] regE_timecode_snapshot1; //! reg [31:0] regF_record_state; //!工作状态 read only wire [31:0] reg_wr_index; @@ -72,8 +72,8 @@ module record_sig_generator #( .regA(regA_exposure_delay), .regB(regB_manual_ctrl), - .regD(regD_start_timecode_snapshot0), - .regE(regE_start_timecode_snapshot1), + .regD(regD_timecode_snapshot0), + .regE(regE_timecode_snapshot1), .regF(regF_record_state), .reg_wr_sig(reg_wr_sig), @@ -224,16 +224,18 @@ module record_sig_generator #( case (en_state) 0: begin if (en_state_af_sync != en_state) begin - en_state_af_sync <= 0; + regD_timecode_snapshot0 <= sys_timecode_data[31:0]; + regE_timecode_snapshot1 <= sys_timecode_data[63:32]; + en_state_af_sync <= 0; end end 1: begin if (en_state_af_sync == 0) begin if (frame_freq_sig_rising_edge) begin - regD_start_timecode_snapshot0 <= sys_timecode_data[31:0]; - regE_start_timecode_snapshot1 <= sys_timecode_data[63:32]; - en_state_af_sync <= 1; + regD_timecode_snapshot0 <= sys_timecode_data[31:0]; + regE_timecode_snapshot1 <= sys_timecode_data[63:32]; + en_state_af_sync <= 1; end end end