8 changed files with 109 additions and 237 deletions
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68camera_light_src_timing_controller_fpga.pds
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55release/test01/README.md
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BINrelease/test01/Top.sbit
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BINrelease/v2.0/xsync_fpage_v2.sbit
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BINrelease/v2.0/xsync_fpage_v2.sfc
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83source/src/output/camera_sync_signal_output.v
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114source/src/output/timecode_output.v
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26source/src/top.v
@ -0,0 +1,55 @@ |
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``` |
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assign diff_out1 = diff_in1; |
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assign diff_out2 = diff_in2; |
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assign diff_out3 = diff_in3; |
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assign diff_out4 = diff_in4; |
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|
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assign optocoupler_out1 = optocoupler_in1; |
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assign optocoupler_out2 = optocoupler_in2; |
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assign optocoupler_out3 = optocoupler_in3; |
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assign optocoupler_out4 = optocoupler_in4; |
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assign uart_tx = uart_rx; |
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assign stm32_output_bus[0] = stm32_input_bus[0]; |
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assign stm32_output_bus[1] = stm32_input_bus[1]; |
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assign stm32_output_bus[2] = stm32_input_bus[2]; |
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assign stm32_output_bus[3] = stm32_input_bus[3]; |
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assign stm32_output_bus[4] = stm32_input_bus[4]; |
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assign stm32_output_bus[5] = stm32_input_bus[5]; |
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assign stm32_output_bus[6] = stm32_input_bus[6]; |
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assign stm32_output_bus[7] = stm32_input_bus[7]; |
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FPGA引出的测试引脚分别输出 |
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pwm100hz |
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pwm101hz |
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pwm102hz |
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pwm103hz |
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pwm104hz |
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pwm105hz |
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pwm106hz |
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pwm107hz |
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pwm108hz |
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pwm109hz |
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pwm110hz |
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pwm111hz |
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pwm112hz |
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pwm113hz |
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pwm114hz |
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pwm115hz |
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亮度控制: |
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.pwm100hz(lt1_en), |
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.pwm101hz(lt2_en), |
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.pwm102hz(lt3_en), |
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.pwm103hz(lt4_en), |
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.pwm104hz(lt1_intensity_ctrl), |
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.pwm105hz(lt2_intensity_ctrl), |
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.pwm106hz(lt3_intensity_ctrl), |
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.pwm107hz(lt4_intensity_ctrl) |
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``` |
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@ -1,83 +0,0 @@ |
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module camera_sync_signal_output #( |
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parameter REG_START_ADD = 0, |
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parameter SYS_CLOCK_FREQ = 10000000 |
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) ( |
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input clk, //clock input |
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input rst_n, //asynchronous reset input, low active |
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//寄存器读写接口 |
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input [31:0] addr, |
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input [31:0] wr_data, |
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input wr_en, |
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output wire [31:0] rd_data, |
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|
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input frame_sig, |
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input record_en_sig, |
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output stm32if_camera_sync_out, //ttl输出信号 |
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output stm32if_record_sync_out // |
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); |
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/******************************************************************************* |
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* 寄存器列表 * |
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*******************************************************************************/ |
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reg [31:0] reg1_pulse_mode_valid_len; |
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wire [31:0] reg_wr_index; |
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|
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zutils_register_advanced #( |
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.REG_START_ADD(REG_START_ADD) |
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) _register ( |
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.clk (clk), |
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.rst_n (rst_n), |
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.addr (addr), |
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.wr_data (wr_data), |
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.wr_en (wr_en), |
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.rd_data (rd_data), |
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.reg1 (reg1_pulse_mode_valid_len), |
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.reg_wr_sig(reg_wr_sig), |
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.reg_index (reg_wr_index) |
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); |
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always @(posedge clk or negedge rst_n) begin |
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if (!rst_n) begin |
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reg1_pulse_mode_valid_len <= SYS_CLOCK_FREQ / 1000; |
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end else begin |
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if (reg_wr_sig) begin |
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case (reg_wr_index) |
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1: reg1_pulse_mode_valid_len <= wr_data; |
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default: begin |
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end |
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endcase |
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end |
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end |
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end |
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|
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/******************************************************************************* |
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* 内部信号 * |
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*******************************************************************************/ |
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wire frame_sig_rising_edge; |
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wire frame_sig_fa_process; |
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// 边沿检测 |
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zutils_edge_detecter _signal_in ( |
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.clk (clk), |
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.rst_n (rst_n), |
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.in_signal (frame_sig), |
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.in_signal_rising_edge(frame_sig_rising_edge) |
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); |
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// 短脉冲，触发生成，长脉冲 |
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zutils_pluse_generator _pluse_generator ( |
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.clk (clk), |
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.rst_n (rst_n), |
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.pluse_width (reg1_pulse_mode_valid_len), //100us |
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.pluse_delay (0), |
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.trigger (frame_sig_rising_edge), |
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.output_signal(frame_sig_fa_process) |
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); |
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assign stm32if_camera_sync_out = frame_sig_fa_process; |
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assign stm32if_record_sync_out = record_en_sig; |
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endmodule |
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@ -1,114 +0,0 @@ |
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module timecode_output #( |
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parameter REG_START_ADD = 0, |
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parameter SYS_CLOCK_FREQ = 10000000 |
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) ( |
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input clk, //clock input |
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input rst_n, //asynchronous reset input, low active |
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input [31:0] addr, |
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input [31:0] wr_data, |
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input wr_en, |
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output wire [31:0] rd_data, |
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/******************************************************************************* |
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* TIMECODE输出 * |
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*******************************************************************************/ |
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input in_timecode_tigger_sig, |
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input [31:0] in_timecode_format, |
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input [63:0] in_timecode_data, |
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input in_timecode_serial_data, |
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/******************************************************************************* |
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* 输出接口 * |
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*******************************************************************************/ |
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output stm32if_timecode_tigger_sig, |
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output reg timecode_out_bnc, |
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output reg timecode_out_bnc_select, // 电平选择 0line,1:mic |
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output reg timecode_out_bnc_state_led, |
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output reg timecode_out_headphone, |
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output reg timecode_out_headphone_select, // 电平选择 0line,1:mic |
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output reg timecode_out_headphone_state_led |
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); |
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// 1ms |
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wire [31:0] r1_timecode0; //时码原始码0 //注意这个数据要比ext_timecode_serial_data晚一帧 |
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wire [31:0] r2_timecode1; //时码原始码1 //注意这个数据要比ext_timecode_serial_data晚一帧 |
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wire [31:0] r3_timecode_format; // |
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reg [31:0] r4_bnc_outut_level_select; // 0:line, 1:mic |
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reg [31:0] r5_headphone_outut_level_select; // 0:line, 1:mic |
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wire [31:0] reg_wr_index; |
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|
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zutils_register_advanced #( |
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.REG_START_ADD(REG_START_ADD) |
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) _register ( |
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.clk (clk), |
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.rst_n (rst_n), |
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.addr (addr), |
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.wr_data(wr_data), |
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.wr_en (wr_en), |
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.rd_data(rd_data), |
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.reg1(r1_timecode0), |
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.reg2(r2_timecode1), |
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.reg3(r3_timecode_format), |
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.reg4(r4_bnc_outut_level_select), |
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.reg5(r5_headphone_outut_level_select), |
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.reg_wr_sig(reg_wr_sig), |
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.reg_index (reg_wr_index) |
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); |
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always @(posedge clk or negedge rst_n) begin |
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if (!rst_n) begin |
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r4_bnc_outut_level_select <= 0; |
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r5_headphone_outut_level_select <= 0; |
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end else begin |
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if (reg_wr_sig) begin |
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case (reg_wr_index) |
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31'h4: r4_bnc_outut_level_select <= wr_data; |
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31'h5: r5_headphone_outut_level_select <= wr_data; |
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default: begin |
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end |
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endcase |
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end |
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end |
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end |
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assign r1_timecode0 = in_timecode_data[31:0]; |
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assign r2_timecode1 = in_timecode_data[63:32]; |
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assign r3_timecode_format = in_timecode_format; |
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assign out_timecode_serial_data = in_timecode_serial_data; |
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assign timecode_tigger_sig = in_timecode_tigger_sig; |
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zutils_pluse_generator _pluse_generator ( |
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.clk (clk), |
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.rst_n (rst_n), |
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.pluse_width (1000), //1ms |
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.pluse_delay (32'd0), |
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.trigger (timecode_tigger_sig), |
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.output_signal(stm32if_timecode_tigger_sig) |
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); |
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always @(*) begin |
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timecode_out_bnc <= out_timecode_serial_data; |
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timecode_out_bnc_select <= r4_bnc_outut_level_select[0]; |
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timecode_out_bnc_state_led <= 1; |
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timecode_out_headphone <= out_timecode_serial_data; |
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timecode_out_headphone_select <= r5_headphone_outut_level_select[0]; |
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timecode_out_headphone_state_led <= 1; |
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end |
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endmodule |
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