diff --git a/camera_light_src_timing_controller_fpga.pds b/camera_light_src_timing_controller_fpga.pds
index f3f83ff..2c5b497 100644
--- a/camera_light_src_timing_controller_fpga.pds
+++ b/camera_light_src_timing_controller_fpga.pds
@@ -1,5 +1,5 @@
 (_flow fab_demo "2021.1-SP7"
-    (_comment "Generated by Fabric Compiler (version on 2021.1-SP7<build 86875>) at Mon Mar 11 15:28:46 2024")
+    (_comment "Generated by Fabric Compiler (version on 2021.1-SP7<build 86875>) at Mon Mar 11 15:59:04 2024")
     (_version "1.0.5")
     (_status "initial")
     (_project 
@@ -199,7 +199,7 @@
                 )
                 (_file "source/src/output/ttl_output_ctrl.v"
                     (_format verilog)
-                    (_timespec "2024-03-11T15:28:29")
+                    (_timespec "2024-03-11T15:57:40")
                 )
                 (_file "source/src/zutils/zutils_pluse_generator_v2.v"
                     (_format verilog)
@@ -279,17 +279,17 @@
             (_db_output
                 (_file "compile/Top_comp.adf"
                     (_format adif)
-                    (_timespec "2024-03-11T15:28:45")
+                    (_timespec "2024-03-11T15:57:46")
                 )
             )
             (_output
                 (_file "compile/Top.cmr"
                     (_format verilog)
-                    (_timespec "2024-03-11T15:28:43")
+                    (_timespec "2024-03-11T15:57:43")
                 )
                 (_file "compile/cmr.db"
                     (_format text)
-                    (_timespec "2024-03-11T15:28:45")
+                    (_timespec "2024-03-11T15:57:46")
                 )
             )
         )
@@ -299,9 +299,29 @@
     )
     (_task tsk_synthesis
         (_command cmd_synthesize
-            (_gci_state (_integer 0))
+            (_gci_state (_integer 2))
             (_option ads (_switch ON))
             (_option selected_syn_tool_opt (_integer 2))
+            (_db_output
+                (_file "synthesize/Top_syn.adf"
+                    (_format adif)
+                    (_timespec "2024-03-11T15:58:42")
+                )
+            )
+            (_output
+                (_file "synthesize/Top_syn.vm"
+                    (_format structural_verilog)
+                    (_timespec "2024-03-11T15:58:50")
+                )
+                (_file "synthesize/Top.snr"
+                    (_format text)
+                    (_timespec "2024-03-11T15:58:57")
+                )
+                (_file "synthesize/snr.db"
+                    (_format text)
+                    (_timespec "2024-03-11T15:58:58")
+                )
+            )
         )
         (_widget wgt_tech_view
             (_attribute _click_to_run (_switch ON))
@@ -316,14 +336,34 @@
     )
     (_task tsk_devmap
         (_command cmd_devmap
-            (_gci_state (_integer 0))
+            (_gci_state (_integer 2))
+            (_db_output
+                (_file "device_map/Top_map.adf"
+                    (_format adif)
+                    (_timespec "2024-03-11T15:59:04")
+                )
+            )
+            (_output
+                (_file "device_map/Top_dmr.prt"
+                    (_format text)
+                    (_timespec "2024-03-11T15:59:01")
+                )
+                (_file "device_map/Top.dmr"
+                    (_format text)
+                    (_timespec "2024-03-11T15:59:04")
+                )
+                (_file "device_map/dmr.db"
+                    (_format text)
+                    (_timespec "2024-03-11T15:59:04")
+                )
+            )
         )
         (_widget wgt_edit_placement_cons
             (_attribute _click_to_run (_switch ON))
             (_input
                 (_file "device_map/camera_light_src_timing_controller_fpga.pcf"
                     (_format pcf)
-                    (_timespec "2024-03-11T14:25:50")
+                    (_timespec "2024-03-11T15:59:04")
                 )
             )
         )
diff --git a/source/src/output/ttl_output_ctrl.v b/source/src/output/ttl_output_ctrl.v
index 6112f3e..4352bcb 100644
--- a/source/src/output/ttl_output_ctrl.v
+++ b/source/src/output/ttl_output_ctrl.v
@@ -29,7 +29,7 @@ module ttl_output_ctrl #(
   reg  [31:0] reg2_lt_en_bind;  //!绑定的光源信号
   reg  [31:0] reg3_lt_en_offset;  //!快门信号与曝光信号偏移
   reg  [31:0] reg4_in_sig_select;  //!转发模式下信号选择器
-  reg  [31:0] reg5_bind_mode_output_polarity_reversal;  //!转发模式下信号选择器
+  reg  [31:0] reg5_output_polarity_reversal;  //!转发模式下信号选择器
   wire [31:0] reg_wr_index;
 
   //!TTLOUT_寄存器自动赋值选择器
@@ -47,6 +47,7 @@ module ttl_output_ctrl #(
       .reg2(reg2_lt_en_bind),
       .reg3(reg3_lt_en_offset),
       .reg4(reg4_in_sig_select),
+      .reg5(reg5_output_polarity_reversal),
 
       .reg_wr_sig(reg_wr_sig),
       .reg_index (reg_wr_index)
@@ -55,11 +56,11 @@ module ttl_output_ctrl #(
   //!寄存器写入逻辑
   always @(posedge clk or negedge rst_n) begin
     if (!rst_n) begin
-      reg1_output_ctrl_mode                   <= `SIG_PROCESS_MODE__BIND_MODE;
-      reg2_lt_en_bind                         <= 32'hffff_ffff;
-      reg3_lt_en_offset                       <= (SYS_CLOCK_FREQ / 32'd1000_000);  //1us
-      reg4_in_sig_select                      <= 0;
-      reg5_bind_mode_output_polarity_reversal <= 0;
+      reg1_output_ctrl_mode         <= `SIG_PROCESS_MODE__BIND_MODE;
+      reg2_lt_en_bind               <= 32'hffff_ffff;
+      reg3_lt_en_offset             <= (SYS_CLOCK_FREQ / 32'd1000_000);  //1us
+      reg4_in_sig_select            <= 0;
+      reg5_output_polarity_reversal <= 0;
     end else begin
       if (reg_wr_sig) begin
         case (reg_wr_index)
@@ -67,7 +68,7 @@ module ttl_output_ctrl #(
           32'h2: reg2_lt_en_bind <= wr_data;
           32'h3: reg3_lt_en_offset <= wr_data;
           32'h4: reg4_in_sig_select <= wr_data;
-          32'h5: reg5_bind_mode_output_polarity_reversal <= wr_data;
+          32'h5: reg5_output_polarity_reversal <= wr_data;
           default: begin
           end
         endcase
@@ -128,8 +129,8 @@ module ttl_output_ctrl #(
 
   always @(*) begin
     case (reg1_output_ctrl_mode)
-      `SIG_PROCESS_MODE__BIND_MODE:        output_sig <= (output_sig_0 & trigger_sig) ^ (reg5_bind_mode_output_polarity_reversal);
-      `SIG_PROCESS_MODE__TRANSPARENT_MODE: output_sig <= signal_in_choose;
+      `SIG_PROCESS_MODE__BIND_MODE:        output_sig <= (output_sig_0 & trigger_sig) ^ (reg5_output_polarity_reversal);
+      `SIG_PROCESS_MODE__TRANSPARENT_MODE: output_sig <= signal_in_choose ^ reg5_output_polarity_reversal;
       default: begin
         output_sig <= 0;
       end