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@ -29,7 +29,7 @@ module ttl_output_ctrl #( |
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reg [31:0] reg2_lt_en_bind; //!绑定的光源信号 |
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reg [31:0] reg2_lt_en_bind; //!绑定的光源信号 |
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reg [31:0] reg3_lt_en_offset; //!快门信号与曝光信号偏移 |
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reg [31:0] reg3_lt_en_offset; //!快门信号与曝光信号偏移 |
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reg [31:0] reg4_in_sig_select; //!转发模式下信号选择器 |
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reg [31:0] reg4_in_sig_select; //!转发模式下信号选择器 |
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reg [31:0] reg5_bind_mode_output_polarity_reversal; //!转发模式下信号选择器 |
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reg [31:0] reg5_output_polarity_reversal; //!转发模式下信号选择器 |
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wire [31:0] reg_wr_index; |
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wire [31:0] reg_wr_index; |
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//!TTLOUT_寄存器自动赋值选择器 |
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//!TTLOUT_寄存器自动赋值选择器 |
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@ -47,6 +47,7 @@ module ttl_output_ctrl #( |
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.reg2(reg2_lt_en_bind), |
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.reg2(reg2_lt_en_bind), |
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.reg3(reg3_lt_en_offset), |
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.reg3(reg3_lt_en_offset), |
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.reg4(reg4_in_sig_select), |
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.reg4(reg4_in_sig_select), |
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.reg5(reg5_output_polarity_reversal), |
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.reg_wr_sig(reg_wr_sig), |
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.reg_wr_sig(reg_wr_sig), |
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.reg_index (reg_wr_index) |
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.reg_index (reg_wr_index) |
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@ -55,11 +56,11 @@ module ttl_output_ctrl #( |
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//!寄存器写入逻辑 |
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//!寄存器写入逻辑 |
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always @(posedge clk or negedge rst_n) begin |
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always @(posedge clk or negedge rst_n) begin |
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if (!rst_n) begin |
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if (!rst_n) begin |
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reg1_output_ctrl_mode <= `SIG_PROCESS_MODE__BIND_MODE; |
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reg2_lt_en_bind <= 32'hffff_ffff; |
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reg3_lt_en_offset <= (SYS_CLOCK_FREQ / 32'd1000_000); //1us |
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reg4_in_sig_select <= 0; |
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reg5_bind_mode_output_polarity_reversal <= 0; |
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reg1_output_ctrl_mode <= `SIG_PROCESS_MODE__BIND_MODE; |
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reg2_lt_en_bind <= 32'hffff_ffff; |
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reg3_lt_en_offset <= (SYS_CLOCK_FREQ / 32'd1000_000); //1us |
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reg4_in_sig_select <= 0; |
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reg5_output_polarity_reversal <= 0; |
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end else begin |
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end else begin |
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if (reg_wr_sig) begin |
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if (reg_wr_sig) begin |
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case (reg_wr_index) |
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case (reg_wr_index) |
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@ -67,7 +68,7 @@ module ttl_output_ctrl #( |
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32'h2: reg2_lt_en_bind <= wr_data; |
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32'h2: reg2_lt_en_bind <= wr_data; |
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32'h3: reg3_lt_en_offset <= wr_data; |
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32'h3: reg3_lt_en_offset <= wr_data; |
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32'h4: reg4_in_sig_select <= wr_data; |
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32'h4: reg4_in_sig_select <= wr_data; |
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32'h5: reg5_bind_mode_output_polarity_reversal <= wr_data; |
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32'h5: reg5_output_polarity_reversal <= wr_data; |
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default: begin |
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default: begin |
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end |
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end |
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endcase |
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endcase |
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@ -128,8 +129,8 @@ module ttl_output_ctrl #( |
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always @(*) begin |
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always @(*) begin |
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case (reg1_output_ctrl_mode) |
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case (reg1_output_ctrl_mode) |
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`SIG_PROCESS_MODE__BIND_MODE: output_sig <= (output_sig_0 & trigger_sig) ^ (reg5_bind_mode_output_polarity_reversal); |
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`SIG_PROCESS_MODE__TRANSPARENT_MODE: output_sig <= signal_in_choose; |
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`SIG_PROCESS_MODE__BIND_MODE: output_sig <= (output_sig_0 & trigger_sig) ^ (reg5_output_polarity_reversal); |
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`SIG_PROCESS_MODE__TRANSPARENT_MODE: output_sig <= signal_in_choose ^ reg5_output_polarity_reversal; |
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default: begin |
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default: begin |
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output_sig <= 0; |
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output_sig <= 0; |
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end |
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end |
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