diff --git a/README.md b/README.md
index 8162ccc..42d893c 100644
--- a/README.md
+++ b/README.md
@@ -5,5 +5,8 @@
 ```
 
 ```
+V1.0
+    1.支持指定脉冲数量发生
+    2.支持脉冲拷贝功能
 
 ```
\ No newline at end of file
diff --git a/release/v1.0/Top.sbit b/release/v1.0/Top.sbit
new file mode 100644
index 0000000..86c4278
Binary files /dev/null and b/release/v1.0/Top.sbit differ
diff --git a/release/v1.0/Top.sfc b/release/v1.0/Top.sfc
new file mode 100644
index 0000000..b60eaed
Binary files /dev/null and b/release/v1.0/Top.sfc differ
diff --git a/source/bak/internal_timecode_generator.v b/source/bak/internal_timecode_generator.v
deleted file mode 100644
index bf5cbf1..0000000
--- a/source/bak/internal_timecode_generator.v
+++ /dev/null
@@ -1,152 +0,0 @@
-
-// module internal_timecode_generator #(
-//     parameter SYS_CLOCK_FREQ = 100000000
-// ) (
-//     input clk,   //clock input
-//     input rst_n, //asynchronous reset input, low active
-
-//     input ctrl_sig,
-
-//     input [31:0] timecode_format,
-
-//     input             timecode_tc_wr_en,
-//     input      [31:0] timecode_tc_wr_data,
-//     output reg [31:0] out_timecode_uc_reg,
-
-//     input             timecode_uc_wr_en,
-//     input      [31:0] timecode_uc_wr_data,
-//     output reg [31:0] out_timecode_tc_reg,
-
-//     output reg out_timecode_tirgger_sig
-// );
-
-//   localparam FPS2398Format = 0;
-//   localparam FPS2400Format = 1;
-//   localparam FPS2500Format = 2;
-//   localparam FPS2997Format = 3;
-//   localparam FPS2997DropFormat = 4;
-//   localparam FPS3000Format = 5;
-
-//   /*******************************************************************************
-//    *                        smpte_timecode_clk_generator                         *
-//    *******************************************************************************/
-
-//   wire timecode_sig_clk_output;
-//   zutils_smpte_timecode_clk_generator #(
-//       .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ)
-//   ) smpte_timecode_clk_generator (
-//       .clk(clk),
-//       .rst_n(rst_n),
-//       .ctrl_sig(ctrl_sig),
-//       .fps2398format_clk(fps2398format_clk),
-//       .fps2400format_clk(fps2400format_clk),
-//       .fps2500format_clk(fps2500format_clk),
-//       .fps2997format_clk(fps2997format_clk),
-//       .fps2997dropformat_clk(fps2997dropformat_clk),
-//       .fps3000format_clk(fps3000format_clk)
-//   );
-
-//   zutils_multiplexer_32t1_v2 timecode_clk_output_mult (
-//       .chooseindex(timecode_format),
-//       //in
-//       .in0(fps2398format_clk),
-//       .in1(fps2400format_clk),
-//       .in2(fps2500format_clk),
-//       .in3(fps2997format_clk),
-//       .in4(fps2997dropformat_clk),
-//       .in5(fps3000format_clk),
-//       //out
-//       .out(timecode_sig_clk_output)
-//   );
-
-//   zutils_edge_detecter timecode_sig_clk_output_edge_detecter (
-//       .clk(clk),
-//       .rst_n(rst_n),
-//       .in_signal(timecode_sig_clk_output),
-//       .in_signal_rising_edge(timecode_sig_clk_output_rising_edge)
-//   );
-
-//   reg [7:0] frameNum;
-//   reg timecode_drop_frame;
-//   wire [31:0] timecode_next;
-
-//   always @(*) begin
-//     case (timecode_format)
-//       FPS2398Format: begin
-//         frameNum <= 24;
-//         timecode_drop_frame <= 0;
-//       end
-//       FPS2400Format: begin
-//         frameNum <= 24;
-//         timecode_drop_frame <= 0;
-//       end
-//       FPS2500Format: begin
-//         frameNum <= 25;
-//         timecode_drop_frame <= 0;
-//       end
-//       FPS2997Format: begin
-//         frameNum <= 30;
-//         timecode_drop_frame <= 0;
-//       end
-//       FPS2997DropFormat: begin
-//         frameNum <= 30;
-//         timecode_drop_frame <= 0;
-//       end
-//       default begin
-//         frameNum <= 30;
-//         timecode_drop_frame <= 0;
-//       end
-//     endcase
-//   end
-
-//   ztutils_timecode_next_code ztutils_timecode_next_code_inst (
-//       .timecode(out_timecode_tc_reg),
-//       .frameNum(frameNum),
-//       .drop(timecode_drop_frame),
-//       .timecode_next(timecode_next)
-//   );
-
-//   reg n_first_timecode_sig;
-
-//   always @(posedge clk or negedge rst_n) begin
-//     if (!rst_n || !ctrl_sig) begin
-//       n_first_timecode_sig <= 0;
-//     end else begin
-//       if (!n_first_timecode_sig && timecode_sig_clk_output_rising_edge) begin
-//         n_first_timecode_sig <= 1;
-//       end
-//     end
-//   end
-
-//   // always @(posedge clk or negedge rst_n) begin
-//   //   if (!rst_n) begin
-//   //     out_timecode_tc_reg  <= 0;
-//   //     out_timecode_uc_reg  <= 0;
-//   //   end else begin
-
-//   //     if (timecode_tc_wr_en) begin
-//   //       //外都写入时间码
-//   //       out_timecode_tc_reg <= timecode_tc_wr_data;
-//   //     end else if (timecode_uc_wr_en) begin
-//   //       //外都写入时间码-用户码
-//   //       out_timecode_uc_reg <= timecode_uc_wr_data;
-//   //     end else begin
-
-//   //       if (timecode_sig_clk_output_rising_edge) begin
-//   //         //第一次触发，不改变时间码
-//   //         if (!n_first_timecode_sig) begin
-//   //           out_timecode_tc_reg  <= out_timecode_tc_reg;
-//   //         end else begin
-//   //           out_timecode_tc_reg <= timecode_next;
-//   //         end
-//   //         out_timecode_tirgger_sig <= 1;
-//   //       end else begin
-//   //         out_timecode_tirgger_sig <= 0;
-//   //       end
-//   //     end
-//   //   end
-//   // end
-
-
-
-// endmodule
diff --git a/source/src/app.v b/source/src/app.v
index 28da6ee..12f519f 100644
--- a/source/src/app.v
+++ b/source/src/app.v
@@ -14,9 +14,9 @@ module app #(
     output wire [31:0] rd_data,  //! 读出数据
 
     input  wire triSig,
-    output wire out1,
-    output wire extOutputEn1,
-    output wire extOutputEn2
+    output reg  out1,
+    output reg  extOutputEn1,
+    output reg  extOutputEn2
 );
 
   reg  [31:0] reg1_src_slect;  //!信号源选择
@@ -26,7 +26,7 @@ module app #(
   reg  [31:0] reg5_trigger_mode_trigger_edge;  //!触发边沿
   reg  [31:0] reg6_trigger_mode_pluse_num;  //!脉冲个数
   reg  [31:0] reg7_trigger_mode_pluse_width;  //!脉冲宽度
-  reg  [31:0] reg8_trigger_mode_pluse_freq_num;  //!脉冲频率
+  reg  [31:0] reg8_trigger_mode_pluse_period;  //!脉冲频率
   wire [31:0] regD_in_signal_freq;  //!输入信号频率探测
   wire [31:0] regE_out_signal_freq;  //!输出信号频率探测
   reg  [31:0] regF_manual_trigger_sig;  //!手动触发信号
@@ -50,7 +50,7 @@ module app #(
       .reg5(reg5_trigger_mode_trigger_edge),
       .reg6(reg6_trigger_mode_pluse_num),
       .reg7(reg7_trigger_mode_pluse_width),
-      .reg8(reg8_trigger_mode_pluse_freq_num),
+      .reg8(reg8_trigger_mode_pluse_period),
       .regD(regD_in_signal_freq),
       .regE(regE_out_signal_freq),
       .regF(regF_manual_trigger_sig),
@@ -61,15 +61,15 @@ module app #(
 
   always @(posedge clk or negedge rst_n) begin
     if (!rst_n) begin
-      reg1_src_slect                   <= 0;
-      reg2_fileter_coefficient         <= `FREQ_TTL_INPUT_FILTER;
-      reg3_freq_detect_bias            <= `FREQ_DETECT_BIAS_DEFAULT;
-      reg4_mode                        <= 0;
-      reg5_trigger_mode_trigger_edge   <= 0;
-      reg6_trigger_mode_pluse_num      <= 0;
-      reg7_trigger_mode_pluse_width    <= 0;
-      reg8_trigger_mode_pluse_freq_num <= 0;
-      regF_manual_trigger_sig          <= 0;
+      reg1_src_slect                 <= 0;
+      reg2_fileter_coefficient       <= `FREQ_TTL_INPUT_FILTER;
+      reg3_freq_detect_bias          <= `FREQ_DETECT_BIAS_DEFAULT;
+      reg4_mode                      <= 0;
+      reg5_trigger_mode_trigger_edge <= 0;
+      reg6_trigger_mode_pluse_num    <= 0;
+      reg7_trigger_mode_pluse_width  <= 0;
+      reg8_trigger_mode_pluse_period <= 0;
+      regF_manual_trigger_sig        <= 0;
     end else begin
       if (reg_wr_sig) begin
         case (reg_wr_index)
@@ -80,7 +80,7 @@ module app #(
           32'h5: reg5_trigger_mode_trigger_edge <= wr_data;
           32'h6: reg6_trigger_mode_pluse_num <= wr_data;
           32'h7: reg7_trigger_mode_pluse_width <= wr_data;
-          32'h8: reg8_trigger_mode_pluse_freq_num <= wr_data;
+          32'h8: reg8_trigger_mode_pluse_period <= wr_data;
           32'hF: regF_manual_trigger_sig <= wr_data;
           default: begin
           end
@@ -89,31 +89,90 @@ module app #(
     end
   end
 
-  wire sig_af_choose_af_filter;
-  zutils_signal_filter_advance filter (
-      .clk               (clk),
-      .rst_n             (rst_n),
-      .filter_delay_count(reg2_fileter_coefficient),
-      .in                (triSig),
-      .out               (sig_af_choose_af_filter)
-  );
+  assign trigger_sig = regF_manual_trigger_sig[0];
+  wire trigger_sig_edge;
 
 
-  zutils_freq_detector_v2 freq_detector1 (
-      .clk             (clk),
-      .rst_n           (rst_n),
-      .freq_detect_bias(reg3_freq_detect_bias),
-      .pluse_input     (sig_af_choose_af_filter),
-      .pluse_width_cnt (regD_in_signal_freq)
+  zutils_edge_detecter cs_edge_detecter (
+      .clk                   (clk),
+      .rst_n                 (rst_n),
+      .in_signal             (trigger_sig),
+      .in_signal_falling_edge(trigger_sig_edge)
   );
 
-  zutils_freq_detector_v2 freq_detector2 (
-      .clk             (clk),
-      .rst_n           (rst_n),
-      .freq_detect_bias(reg3_freq_detect_bias),
-      .pluse_input     (signal_out_final),
-      .pluse_width_cnt (regE_out_signal_freq)
-  );
+  reg        state;
+  reg [31:0] cnt;
+  reg [31:0] pluseCnt;
+  reg        autoRestart;
+
+  always @(posedge clk or negedge rst_n) begin
+    if (!rst_n) begin
+      state       <= 0;
+      cnt         <= 0;
+      pluseCnt    <= 0;
+      autoRestart <= 0;
+
+      out1        <= 0;
+    end else begin
+      case (state)
+        0: begin
+          out1        <= 0;
+          cnt         <= 0;
+          pluseCnt    <= 0;
+          autoRestart <= 0;
+          if (trigger_sig_edge || autoRestart) begin
+            state <= 1;
+          end
+        end
+        1: begin
+          //复位
+          if (trigger_sig_edge) begin
+            state       <= 0;
+            autoRestart <= 1;
+          end
+
+          if (cnt <= reg7_trigger_mode_pluse_width) begin
+            out1 <= 1;
+            cnt  <= cnt + 1;
+          end else begin
+            out1 <= 0;
+            if (cnt < reg8_trigger_mode_pluse_period) begin
+              cnt <= cnt + 1;
+            end else begin
+              cnt      <= 0;
+              pluseCnt <= pluseCnt + 1;
+              if (reg6_trigger_mode_pluse_num != 0 && pluseCnt + 1 >= reg6_trigger_mode_pluse_num) state <= 0;
+            end
+          end
+
+        end
+        default: begin
+        end
+      endcase
+    end
+  end
+
+
+
+
+  always @(*) begin
+    case (reg4_mode)
+      1: begin
+        extOutputEn1 <= 0;
+        extOutputEn2 <= 1;
+      end
+      default: begin
+        extOutputEn1 <= 1;
+        extOutputEn2 <= 0;
+      end
+    endcase
+  end
+
+  // zutils_pwm_generator pwmgen (
+  //     .clk          (clk),
+  //     .rst_n        (rst_n),
+  //     .output_signal(out1)
+  // );
 
 
 
diff --git a/source/src/config.v b/source/src/config.v
index c882c48..85e0afa 100644
--- a/source/src/config.v
+++ b/source/src/config.v
@@ -1,4 +1,6 @@
-`define REGADDOFF__FPGA_VERSION 32'd10
+//VERSION 01    00   00
+//        main  sub  fix
+`define REGADDOFF__FPGA_VERSION 32'h010102
 /*******************************************************************************
  *                               寄存器地址分配                                *
  *******************************************************************************/
@@ -6,7 +8,6 @@
 `define REGADDOFF__APP 16'h1020
 
 
-
 /*******************************************************************************
  *                            部分寄存器初始化数值                             *
  *******************************************************************************/
diff --git a/source/src/top.v b/source/src/top.v
index 897ef3e..99d46fe 100644
--- a/source/src/top.v
+++ b/source/src/top.v
@@ -102,11 +102,32 @@ module Top (
       .rd_data(rd_data_fpga_info)
   );
 
+    app #(
+        .REG_START_ADD(`REGADDOFF__APP),
+        .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ),
+        .FREQ_DETECT_BIAS(`FREQ_DETECT_BIAS_DEFAULT)
+    ) app_ins (
+        .clk          (sys_clk),
+        .rst_n        (sys_rst_n),
+        .addr         (RegReaderBus_addr),
+        .wr_data      (RegReaderBus_wr_data),
+        .wr_en        (RegReaderBus_wr_en),
+        .rd_data      (rd_data_app),
+    
+        .triSig       (triSig),
+        .out1         (out1),
+        .extOutputEn1 (extOutputEn1),
+        .extOutputEn2 (extOutputEn2)
+    );
+
+    zutils_debug_led #(
+        .PERIOD_COUNT(10000000)
+    ) core_board_debug_led_inst (
+        .clk(sys_clk),
+        .rst_n(sys_rst_n),
+        .debug_led(core_board_debug_led)
+    );
 
-  //   assign debug_bus[12] = diff_out1;
-  //   assign debug_bus[13] = diff_out2;
-  //   assign debug_bus[14] = diff_out3;
-  //   assign debug_bus[15] = diff_out4;
 
 
 endmodule
diff --git a/syncbox16ch.pds b/syncbox16ch.pds
index 9312fa9..fc929ff 100644
--- a/syncbox16ch.pds
+++ b/syncbox16ch.pds
@@ -1,5 +1,5 @@
 (_flow fab_demo "2021.1-SP7"
-    (_comment "Generated by Fabric Compiler (version on 2021.1-SP7<build 86875>) at Mon Aug  5 13:54:18 2024")
+    (_comment "Generated by Fabric Compiler (version on 2021.1-SP7<build 86875>) at Tue Aug  6 09:45:29 2024")
     (_version "1.0.5")
     (_status "initial")
     (_project 
@@ -19,7 +19,7 @@
             (_input
                 (_file "source/src/top.v" + "Top:"
                     (_format verilog)
-                    (_timespec "2024-08-05T13:53:15")
+                    (_timespec "2024-08-05T14:18:46")
                 )
                 (_file "source/src/spi_reg_reader.v"
                     (_format verilog)
@@ -43,7 +43,7 @@
                 )
                 (_file "source/src/zutils/zutils_debug_led.v"
                     (_format verilog)
-                    (_timespec "2024-03-08T21:15:01")
+                    (_timespec "2024-08-05T13:59:51")
                 )
                 (_file "source/src/zutils/zutils_signal_filter.v"
                     (_format verilog)
@@ -149,6 +149,10 @@
                     (_format verilog)
                     (_timespec "2024-05-10T14:03:35")
                 )
+                (_file "source/src/app.v"
+                    (_format verilog)
+                    (_timespec "2024-08-06T09:43:36")
+                )
             )
         )
         (_widget wgt_my_ips_src
@@ -216,17 +220,17 @@
             (_db_output
                 (_file "compile/Top_comp.adf"
                     (_format adif)
-                    (_timespec "2024-08-05T13:53:32")
+                    (_timespec "2024-08-06T09:44:18")
                 )
             )
             (_output
                 (_file "compile/Top.cmr"
                     (_format verilog)
-                    (_timespec "2024-08-05T13:53:32")
+                    (_timespec "2024-08-06T09:44:18")
                 )
                 (_file "compile/cmr.db"
                     (_format text)
-                    (_timespec "2024-08-05T13:53:32")
+                    (_timespec "2024-08-06T09:44:18")
                 )
             )
         )
@@ -242,21 +246,21 @@
             (_db_output
                 (_file "synthesize/Top_syn.adf"
                     (_format adif)
-                    (_timespec "2024-08-05T13:53:35")
+                    (_timespec "2024-08-06T09:44:31")
                 )
             )
             (_output
                 (_file "synthesize/Top_syn.vm"
                     (_format structural_verilog)
-                    (_timespec "2024-08-05T13:53:36")
+                    (_timespec "2024-08-06T09:44:32")
                 )
                 (_file "synthesize/Top.snr"
                     (_format text)
-                    (_timespec "2024-08-05T13:53:36")
+                    (_timespec "2024-08-06T09:44:33")
                 )
                 (_file "synthesize/snr.db"
                     (_format text)
-                    (_timespec "2024-08-05T13:53:37")
+                    (_timespec "2024-08-06T09:44:33")
                 )
             )
         )
@@ -277,21 +281,21 @@
             (_db_output
                 (_file "device_map/Top_map.adf"
                     (_format adif)
-                    (_timespec "2024-08-05T13:53:39")
+                    (_timespec "2024-08-06T09:44:41")
                 )
             )
             (_output
                 (_file "device_map/Top_dmr.prt"
                     (_format text)
-                    (_timespec "2024-08-05T13:53:39")
+                    (_timespec "2024-08-06T09:44:39")
                 )
                 (_file "device_map/Top.dmr"
                     (_format text)
-                    (_timespec "2024-08-05T13:53:39")
+                    (_timespec "2024-08-06T09:44:41")
                 )
                 (_file "device_map/dmr.db"
                     (_format text)
-                    (_timespec "2024-08-05T13:53:39")
+                    (_timespec "2024-08-06T09:44:41")
                 )
             )
         )
@@ -300,7 +304,7 @@
             (_input
                 (_file "device_map/xsyncbox16ch.pcf"
                     (_format pcf)
-                    (_timespec "2024-08-05T13:53:39")
+                    (_timespec "2024-08-06T09:44:41")
                 )
             )
         )
@@ -315,33 +319,33 @@
             (_db_output
                 (_file "place_route/Top_pnr.adf"
                     (_format adif)
-                    (_timespec "2024-08-05T13:53:57")
+                    (_timespec "2024-08-06T09:45:07")
                 )
             )
             (_output
                 (_file "place_route/Top.prr"
                     (_format text)
-                    (_timespec "2024-08-05T13:53:57")
+                    (_timespec "2024-08-06T09:45:07")
                 )
                 (_file "place_route/Top_prr.prt"
                     (_format text)
-                    (_timespec "2024-08-05T13:53:57")
+                    (_timespec "2024-08-06T09:45:07")
                 )
                 (_file "place_route/clock_utilization.txt"
                     (_format text)
-                    (_timespec "2024-08-05T13:53:57")
+                    (_timespec "2024-08-06T09:45:07")
                 )
                 (_file "place_route/Top_plc.adf"
                     (_format adif)
-                    (_timespec "2024-08-05T13:53:47")
+                    (_timespec "2024-08-06T09:44:51")
                 )
                 (_file "place_route/Top_pnr.netlist"
                     (_format text)
-                    (_timespec "2024-08-05T13:53:57")
+                    (_timespec "2024-08-06T09:45:07")
                 )
                 (_file "place_route/prr.db"
                     (_format text)
-                    (_timespec "2024-08-05T13:53:58")
+                    (_timespec "2024-08-06T09:45:08")
                 )
             )
         )
@@ -376,19 +380,19 @@
             (_output
                 (_file "generate_bitstream/Top.sbit"
                     (_format text)
-                    (_timespec "2024-08-05T13:54:12")
+                    (_timespec "2024-08-06T09:45:27")
                 )
                 (_file "generate_bitstream/Top.smsk"
                     (_format text)
-                    (_timespec "2024-08-05T13:54:12")
+                    (_timespec "2024-08-06T09:45:27")
                 )
                 (_file "generate_bitstream/Top.bgr"
                     (_format text)
-                    (_timespec "2024-08-05T13:54:12")
+                    (_timespec "2024-08-06T09:45:27")
                 )
                 (_file "generate_bitstream/bgr.db"
                     (_format text)
-                    (_timespec "2024-08-05T13:54:14")
+                    (_timespec "2024-08-06T09:45:29")
                 )
             )
         )