diff --git a/README.md b/README.md index e69de29..918ac32 100644 --- a/README.md +++ b/README.md @@ -0,0 +1 @@ +cfg_gen_sfc -device_name W25Q128Q -opcode 107 -sbit_start_address 0 -sbit generate_bitstream/Top.sbit diff --git a/camera_light_src_timing_controller_fpga.fdc b/camera_light_src_timing_controller_fpga.fdc index 06b1a44..0d3fc3c 100644 --- a/camera_light_src_timing_controller_fpga.fdc +++ b/camera_light_src_timing_controller_fpga.fdc @@ -36,26 +36,36 @@ define_attribute {p:core_board_debug_led} {PAP_IO_VCCIO} {3.3} define_attribute {p:core_board_debug_led} {PAP_IO_STANDARD} {LVCMOS33} define_attribute {p:core_board_debug_led} {PAP_IO_DRIVE} {4} define_attribute {p:core_board_debug_led} {PAP_IO_SLEW} {SLOW} -define_attribute {p:id[0]} {PAP_IO_DIRECTION} {INPUT} -define_attribute {p:id[0]} {PAP_IO_LOC} {M16} -define_attribute {p:id[0]} {PAP_IO_VCCIO} {3.3} -define_attribute {p:id[0]} {PAP_IO_STANDARD} {LVTTL33} -define_attribute {p:id[1]} {PAP_IO_DIRECTION} {INPUT} -define_attribute {p:id[1]} {PAP_IO_LOC} {L16} -define_attribute {p:id[1]} {PAP_IO_VCCIO} {3.3} -define_attribute {p:id[1]} {PAP_IO_STANDARD} {LVTTL33} -define_attribute {p:id[2]} {PAP_IO_DIRECTION} {INPUT} -define_attribute {p:id[2]} {PAP_IO_LOC} {J18} -define_attribute {p:id[2]} {PAP_IO_VCCIO} {3.3} -define_attribute {p:id[2]} {PAP_IO_STANDARD} {LVTTL33} -define_attribute {p:id[3]} {PAP_IO_DIRECTION} {INPUT} -define_attribute {p:id[3]} {PAP_IO_LOC} {J17} -define_attribute {p:id[3]} {PAP_IO_VCCIO} {3.3} -define_attribute {p:id[3]} {PAP_IO_STANDARD} {LVTTL33} -define_attribute {p:id[4]} {PAP_IO_DIRECTION} {INPUT} -define_attribute {p:id[4]} {PAP_IO_LOC} {E15} -define_attribute {p:id[4]} {PAP_IO_VCCIO} {3.3} -define_attribute {p:id[4]} {PAP_IO_STANDARD} {LVTTL33} +define_attribute {p:tmp_contrl_pin[0]} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:tmp_contrl_pin[0]} {PAP_IO_LOC} {M16} +define_attribute {p:tmp_contrl_pin[0]} {PAP_IO_VCCIO} {3.3} +define_attribute {p:tmp_contrl_pin[0]} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:tmp_contrl_pin[0]} {PAP_IO_DRIVE} {4} +define_attribute {p:tmp_contrl_pin[0]} {PAP_IO_SLEW} {SLOW} +define_attribute {p:tmp_contrl_pin[1]} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:tmp_contrl_pin[1]} {PAP_IO_LOC} {L16} +define_attribute {p:tmp_contrl_pin[1]} {PAP_IO_VCCIO} {3.3} +define_attribute {p:tmp_contrl_pin[1]} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:tmp_contrl_pin[1]} {PAP_IO_DRIVE} {4} +define_attribute {p:tmp_contrl_pin[1]} {PAP_IO_SLEW} {SLOW} +define_attribute {p:tmp_contrl_pin[2]} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:tmp_contrl_pin[2]} {PAP_IO_LOC} {J18} +define_attribute {p:tmp_contrl_pin[2]} {PAP_IO_VCCIO} {3.3} +define_attribute {p:tmp_contrl_pin[2]} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:tmp_contrl_pin[2]} {PAP_IO_DRIVE} {4} +define_attribute {p:tmp_contrl_pin[2]} {PAP_IO_SLEW} {SLOW} +define_attribute {p:tmp_contrl_pin[3]} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:tmp_contrl_pin[3]} {PAP_IO_LOC} {J17} +define_attribute {p:tmp_contrl_pin[3]} {PAP_IO_VCCIO} {3.3} +define_attribute {p:tmp_contrl_pin[3]} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:tmp_contrl_pin[3]} {PAP_IO_DRIVE} {4} +define_attribute {p:tmp_contrl_pin[3]} {PAP_IO_SLEW} {SLOW} +define_attribute {p:tmp_contrl_pin[4]} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:tmp_contrl_pin[4]} {PAP_IO_LOC} {E15} +define_attribute {p:tmp_contrl_pin[4]} {PAP_IO_VCCIO} {3.3} +define_attribute {p:tmp_contrl_pin[4]} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:tmp_contrl_pin[4]} {PAP_IO_DRIVE} {4} +define_attribute {p:tmp_contrl_pin[4]} {PAP_IO_SLEW} {SLOW} define_attribute {p:stm32_output_bus[0]} {PAP_IO_DIRECTION} {OUTPUT} define_attribute {p:stm32_output_bus[0]} {PAP_IO_LOC} {M18} define_attribute {p:stm32_output_bus[0]} {PAP_IO_VCCIO} {3.3} diff --git a/camera_light_src_timing_controller_fpga.pds b/camera_light_src_timing_controller_fpga.pds index a39a789..7a91fe7 100644 --- a/camera_light_src_timing_controller_fpga.pds +++ b/camera_light_src_timing_controller_fpga.pds @@ -1,5 +1,5 @@ (_flow fab_demo "2021.1-SP7" - (_comment "Generated by Fabric Compiler (version on 2021.1-SP7) at Tue Apr 23 19:57:55 2024") + (_comment "Generated by Fabric Compiler (version on 2021.1-SP7) at Thu Apr 25 16:42:04 2024") (_version "1.0.5") (_status "initial") (_project @@ -19,7 +19,7 @@ (_input (_file "source/src/top.v" + "Top:" (_format verilog) - (_timespec "2024-03-11T14:22:56") + (_timespec "2024-04-25T16:35:18") ) (_file "source/src/spi_reg_reader.v" (_format verilog) @@ -228,7 +228,7 @@ (_input (_file "camera_light_src_timing_controller_fpga.fdc" (_format fdc) - (_timespec "2024-03-10T19:50:39") + (_timespec "2024-04-25T16:32:20") ) ) ) @@ -279,17 +279,17 @@ (_db_output (_file "compile/Top_comp.adf" (_format adif) - (_timespec "2024-04-23T19:51:24") + (_timespec "2024-04-25T16:38:12") ) ) (_output (_file "compile/Top.cmr" (_format verilog) - (_timespec "2024-04-23T19:51:22") + (_timespec "2024-04-25T16:38:10") ) (_file "compile/cmr.db" (_format text) - (_timespec "2024-04-23T19:51:24") + (_timespec "2024-04-25T16:38:12") ) ) ) @@ -305,21 +305,21 @@ (_db_output (_file "synthesize/Top_syn.adf" (_format adif) - (_timespec "2024-04-23T19:52:50") + (_timespec "2024-04-25T16:38:30") ) ) (_output (_file "synthesize/Top_syn.vm" (_format structural_verilog) - (_timespec "2024-04-23T19:52:57") + (_timespec "2024-04-25T16:38:31") ) (_file "synthesize/Top.snr" (_format text) - (_timespec "2024-04-23T19:53:04") + (_timespec "2024-04-25T16:38:32") ) (_file "synthesize/snr.db" (_format text) - (_timespec "2024-04-23T19:53:05") + (_timespec "2024-04-25T16:38:32") ) ) ) @@ -340,21 +340,21 @@ (_db_output (_file "device_map/Top_map.adf" (_format adif) - (_timespec "2024-04-23T19:53:15") + (_timespec "2024-04-25T16:38:36") ) ) (_output (_file "device_map/Top_dmr.prt" (_format text) - (_timespec "2024-04-23T19:53:08") + (_timespec "2024-04-25T16:38:35") ) (_file "device_map/Top.dmr" (_format text) - (_timespec "2024-04-23T19:53:15") + (_timespec "2024-04-25T16:38:36") ) (_file "device_map/dmr.db" (_format text) - (_timespec "2024-04-23T19:53:16") + (_timespec "2024-04-25T16:38:37") ) ) ) @@ -363,7 +363,7 @@ (_input (_file "device_map/camera_light_src_timing_controller_fpga.pcf" (_format pcf) - (_timespec "2024-04-23T19:53:15") + (_timespec "2024-04-25T16:38:36") ) ) ) @@ -378,33 +378,33 @@ (_db_output (_file "place_route/Top_pnr.adf" (_format adif) - (_timespec "2024-04-23T19:56:41") + (_timespec "2024-04-25T16:41:20") ) ) (_output (_file "place_route/Top.prr" (_format text) - (_timespec "2024-04-23T19:56:41") + (_timespec "2024-04-25T16:41:20") ) (_file "place_route/Top_prr.prt" (_format text) - (_timespec "2024-04-23T19:56:39") + (_timespec "2024-04-25T16:41:18") ) (_file "place_route/clock_utilization.txt" (_format text) - (_timespec "2024-04-23T19:56:40") + (_timespec "2024-04-25T16:41:18") ) (_file "place_route/Top_plc.adf" (_format adif) - (_timespec "2024-04-23T19:54:03") + (_timespec "2024-04-25T16:39:01") ) (_file "place_route/Top_pnr.netlist" (_format text) - (_timespec "2024-04-23T19:56:41") + (_timespec "2024-04-25T16:41:20") ) (_file "place_route/prr.db" (_format text) - (_timespec "2024-04-23T19:56:42") + (_timespec "2024-04-25T16:41:21") ) ) ) @@ -439,19 +439,19 @@ (_output (_file "generate_bitstream/Top.sbit" (_format text) - (_timespec "2024-04-23T19:57:53") + (_timespec "2024-04-25T16:42:03") ) (_file "generate_bitstream/Top.smsk" (_format text) - (_timespec "2024-04-23T19:57:53") + (_timespec "2024-04-25T16:42:03") ) (_file "generate_bitstream/Top.bgr" (_format text) - (_timespec "2024-04-23T19:57:53") + (_timespec "2024-04-25T16:42:03") ) (_file "generate_bitstream/bgr.db" (_format text) - (_timespec "2024-04-23T19:57:55") + (_timespec "2024-04-25T16:42:04") ) ) ) diff --git a/pin.csv b/pin.csv index 160e125..bbb031c 100644 --- a/pin.csv +++ b/pin.csv @@ -7,11 +7,11 @@ R18,spi_rx_pin,INPUT L17,uart_tx,OUTPUT L18,uart_rx,INPUT T11,core_board_debug_led,OUTPUT -M16,id[0],INPUT -L16,id[1],INPUT -J18,id[2],INPUT -J17,id[3],INPUT -E15,id[4],INPUT +M16,tmp_contrl_pin[0],OUTPUT +L16,tmp_contrl_pin[1],OUTPUT +J18,tmp_contrl_pin[2],OUTPUT +J17,tmp_contrl_pin[3],OUTPUT +E15,tmp_contrl_pin[4],OUTPUT M18,stm32_output_bus[0],OUTPUT K18,stm32_output_bus[1],OUTPUT K17,stm32_output_bus[2],OUTPUT diff --git a/release/v4/Top.sbit b/release/v4/Top.sbit new file mode 100644 index 0000000..d38ae18 Binary files /dev/null and b/release/v4/Top.sbit differ diff --git a/release/v4/Top.sfc b/release/v4/Top.sfc new file mode 100644 index 0000000..65b5ab4 Binary files /dev/null and b/release/v4/Top.sfc differ diff --git a/release/v5/Top.sbit b/release/v5/Top.sbit new file mode 100644 index 0000000..650f0c1 Binary files /dev/null and b/release/v5/Top.sbit differ diff --git a/release/v5/Top.sfc b/release/v5/Top.sfc new file mode 100644 index 0000000..c8132ff Binary files /dev/null and b/release/v5/Top.sfc differ diff --git a/source/src/config.v b/source/src/config.v index 56fbce4..0c859bf 100644 --- a/source/src/config.v +++ b/source/src/config.v @@ -1,4 +1,4 @@ -`define REGADDOFF__FPGA_VERSION 32'd4 +`define REGADDOFF__FPGA_VERSION 32'd5 /******************************************************************************* * 寄存器地址分配 * *******************************************************************************/ diff --git a/source/src/top.v b/source/src/top.v index eb34fe6..106560f 100644 --- a/source/src/top.v +++ b/source/src/top.v @@ -14,7 +14,7 @@ module Top ( input wire uart_rx, - input wire [4:0] id, + output wire [4:0] tmp_contrl_pin, output wire core_board_debug_led, @@ -102,8 +102,12 @@ module Top ( localparam SYS_CLOCK_FREQ = 100000000; assign sys_clk = sys_clk_100m; assign sys_rst_n = stm32_input_bus[0] & pll_lock; - // assign sys_rst_n = pll_lock; + assign tmp_contrl_pin[0] = !sys_rst_n; + assign tmp_contrl_pin[1] = !sys_rst_n; + assign tmp_contrl_pin[2] = !sys_rst_n; + assign tmp_contrl_pin[3] = !sys_rst_n; + assign tmp_contrl_pin[4] = !sys_rst_n; wire [31:0] rd_data_fpga_info; wire [31:0] rd_data_internal_clk;