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syncbox16ch_fpga
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v5

master
zhaohe 1 year ago
parent
636eefe6cd
commit
f8f8e031e8
10 changed files with 69 additions and 54 deletions
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  1. 1
      README.md
  2. 50
      camera_light_src_timing_controller_fpga.fdc
  3. 52
      camera_light_src_timing_controller_fpga.pds
  4. 10
      pin.csv
  5. BIN
      release/v4/Top.sbit
  6. BIN
      release/v4/Top.sfc
  7. BIN
      release/v5/Top.sbit
  8. BIN
      release/v5/Top.sfc
  9. 2
      source/src/config.v
  10. 8
      source/src/top.v

1
README.md
View File

@ -0,0 +1 @@
cfg_gen_sfc -device_name W25Q128Q -opcode 107 -sbit_start_address 0 -sbit generate_bitstream/Top.sbit

50
camera_light_src_timing_controller_fpga.fdc
View File

@ -36,26 +36,36 @@ define_attribute {p:core_board_debug_led} {PAP_IO_VCCIO} {3.3}
define_attribute {p:core_board_debug_led} {PAP_IO_STANDARD} {LVCMOS33} define_attribute {p:core_board_debug_led} {PAP_IO_STANDARD} {LVCMOS33}
define_attribute {p:core_board_debug_led} {PAP_IO_DRIVE} {4} define_attribute {p:core_board_debug_led} {PAP_IO_DRIVE} {4}
define_attribute {p:core_board_debug_led} {PAP_IO_SLEW} {SLOW} define_attribute {p:core_board_debug_led} {PAP_IO_SLEW} {SLOW}
define_attribute {p:id[0]} {PAP_IO_DIRECTION} {INPUT}
define_attribute {p:id[0]} {PAP_IO_LOC} {M16}
define_attribute {p:id[0]} {PAP_IO_VCCIO} {3.3}
define_attribute {p:id[0]} {PAP_IO_STANDARD} {LVTTL33}
define_attribute {p:id[1]} {PAP_IO_DIRECTION} {INPUT}
define_attribute {p:id[1]} {PAP_IO_LOC} {L16}
define_attribute {p:id[1]} {PAP_IO_VCCIO} {3.3}
define_attribute {p:id[1]} {PAP_IO_STANDARD} {LVTTL33}
define_attribute {p:id[2]} {PAP_IO_DIRECTION} {INPUT}
define_attribute {p:id[2]} {PAP_IO_LOC} {J18}
define_attribute {p:id[2]} {PAP_IO_VCCIO} {3.3}
define_attribute {p:id[2]} {PAP_IO_STANDARD} {LVTTL33}
define_attribute {p:id[3]} {PAP_IO_DIRECTION} {INPUT}
define_attribute {p:id[3]} {PAP_IO_LOC} {J17}
define_attribute {p:id[3]} {PAP_IO_VCCIO} {3.3}
define_attribute {p:id[3]} {PAP_IO_STANDARD} {LVTTL33}
define_attribute {p:id[4]} {PAP_IO_DIRECTION} {INPUT}
define_attribute {p:id[4]} {PAP_IO_LOC} {E15}
define_attribute {p:id[4]} {PAP_IO_VCCIO} {3.3}
define_attribute {p:id[4]} {PAP_IO_STANDARD} {LVTTL33}
define_attribute {p:tmp_contrl_pin[0]} {PAP_IO_DIRECTION} {OUTPUT}
define_attribute {p:tmp_contrl_pin[0]} {PAP_IO_LOC} {M16}
define_attribute {p:tmp_contrl_pin[0]} {PAP_IO_VCCIO} {3.3}
define_attribute {p:tmp_contrl_pin[0]} {PAP_IO_STANDARD} {LVCMOS33}
define_attribute {p:tmp_contrl_pin[0]} {PAP_IO_DRIVE} {4}
define_attribute {p:tmp_contrl_pin[0]} {PAP_IO_SLEW} {SLOW}
define_attribute {p:tmp_contrl_pin[1]} {PAP_IO_DIRECTION} {OUTPUT}
define_attribute {p:tmp_contrl_pin[1]} {PAP_IO_LOC} {L16}
define_attribute {p:tmp_contrl_pin[1]} {PAP_IO_VCCIO} {3.3}
define_attribute {p:tmp_contrl_pin[1]} {PAP_IO_STANDARD} {LVCMOS33}
define_attribute {p:tmp_contrl_pin[1]} {PAP_IO_DRIVE} {4}
define_attribute {p:tmp_contrl_pin[1]} {PAP_IO_SLEW} {SLOW}
define_attribute {p:tmp_contrl_pin[2]} {PAP_IO_DIRECTION} {OUTPUT}
define_attribute {p:tmp_contrl_pin[2]} {PAP_IO_LOC} {J18}
define_attribute {p:tmp_contrl_pin[2]} {PAP_IO_VCCIO} {3.3}
define_attribute {p:tmp_contrl_pin[2]} {PAP_IO_STANDARD} {LVCMOS33}
define_attribute {p:tmp_contrl_pin[2]} {PAP_IO_DRIVE} {4}
define_attribute {p:tmp_contrl_pin[2]} {PAP_IO_SLEW} {SLOW}
define_attribute {p:tmp_contrl_pin[3]} {PAP_IO_DIRECTION} {OUTPUT}
define_attribute {p:tmp_contrl_pin[3]} {PAP_IO_LOC} {J17}
define_attribute {p:tmp_contrl_pin[3]} {PAP_IO_VCCIO} {3.3}
define_attribute {p:tmp_contrl_pin[3]} {PAP_IO_STANDARD} {LVCMOS33}
define_attribute {p:tmp_contrl_pin[3]} {PAP_IO_DRIVE} {4}
define_attribute {p:tmp_contrl_pin[3]} {PAP_IO_SLEW} {SLOW}
define_attribute {p:tmp_contrl_pin[4]} {PAP_IO_DIRECTION} {OUTPUT}
define_attribute {p:tmp_contrl_pin[4]} {PAP_IO_LOC} {E15}
define_attribute {p:tmp_contrl_pin[4]} {PAP_IO_VCCIO} {3.3}
define_attribute {p:tmp_contrl_pin[4]} {PAP_IO_STANDARD} {LVCMOS33}
define_attribute {p:tmp_contrl_pin[4]} {PAP_IO_DRIVE} {4}
define_attribute {p:tmp_contrl_pin[4]} {PAP_IO_SLEW} {SLOW}
define_attribute {p:stm32_output_bus[0]} {PAP_IO_DIRECTION} {OUTPUT} define_attribute {p:stm32_output_bus[0]} {PAP_IO_DIRECTION} {OUTPUT}
define_attribute {p:stm32_output_bus[0]} {PAP_IO_LOC} {M18} define_attribute {p:stm32_output_bus[0]} {PAP_IO_LOC} {M18}
define_attribute {p:stm32_output_bus[0]} {PAP_IO_VCCIO} {3.3} define_attribute {p:stm32_output_bus[0]} {PAP_IO_VCCIO} {3.3}

52
camera_light_src_timing_controller_fpga.pds
View File

@ -1,5 +1,5 @@
(_flow fab_demo "2021.1-SP7" (_flow fab_demo "2021.1-SP7"
(_comment "Generated by Fabric Compiler (version on 2021.1-SP7<build 86875>) at Tue Apr 23 19:57:55 2024")
(_comment "Generated by Fabric Compiler (version on 2021.1-SP7<build 86875>) at Thu Apr 25 16:42:04 2024")
(_version "1.0.5") (_version "1.0.5")
(_status "initial") (_status "initial")
(_project (_project
@ -19,7 +19,7 @@
(_input (_input
(_file "source/src/top.v" + "Top:" (_file "source/src/top.v" + "Top:"
(_format verilog) (_format verilog)
(_timespec "2024-03-11T14:22:56")
(_timespec "2024-04-25T16:35:18")
) )
(_file "source/src/spi_reg_reader.v" (_file "source/src/spi_reg_reader.v"
(_format verilog) (_format verilog)
@ -228,7 +228,7 @@
(_input (_input
(_file "camera_light_src_timing_controller_fpga.fdc" (_file "camera_light_src_timing_controller_fpga.fdc"
(_format fdc) (_format fdc)
(_timespec "2024-03-10T19:50:39")
(_timespec "2024-04-25T16:32:20")
) )
) )
) )
@ -279,17 +279,17 @@
(_db_output (_db_output
(_file "compile/Top_comp.adf" (_file "compile/Top_comp.adf"
(_format adif) (_format adif)
(_timespec "2024-04-23T19:51:24")
(_timespec "2024-04-25T16:38:12")
) )
) )
(_output (_output
(_file "compile/Top.cmr" (_file "compile/Top.cmr"
(_format verilog) (_format verilog)
(_timespec "2024-04-23T19:51:22")
(_timespec "2024-04-25T16:38:10")
) )
(_file "compile/cmr.db" (_file "compile/cmr.db"
(_format text) (_format text)
(_timespec "2024-04-23T19:51:24")
(_timespec "2024-04-25T16:38:12")
) )
) )
) )
@ -305,21 +305,21 @@
(_db_output (_db_output
(_file "synthesize/Top_syn.adf" (_file "synthesize/Top_syn.adf"
(_format adif) (_format adif)
(_timespec "2024-04-23T19:52:50")
(_timespec "2024-04-25T16:38:30")
) )
) )
(_output (_output
(_file "synthesize/Top_syn.vm" (_file "synthesize/Top_syn.vm"
(_format structural_verilog) (_format structural_verilog)
(_timespec "2024-04-23T19:52:57")
(_timespec "2024-04-25T16:38:31")
) )
(_file "synthesize/Top.snr" (_file "synthesize/Top.snr"
(_format text) (_format text)
(_timespec "2024-04-23T19:53:04")
(_timespec "2024-04-25T16:38:32")
) )
(_file "synthesize/snr.db" (_file "synthesize/snr.db"
(_format text) (_format text)
(_timespec "2024-04-23T19:53:05")
(_timespec "2024-04-25T16:38:32")
) )
) )
) )
@ -340,21 +340,21 @@
(_db_output (_db_output
(_file "device_map/Top_map.adf" (_file "device_map/Top_map.adf"
(_format adif) (_format adif)
(_timespec "2024-04-23T19:53:15")
(_timespec "2024-04-25T16:38:36")
) )
) )
(_output (_output
(_file "device_map/Top_dmr.prt" (_file "device_map/Top_dmr.prt"
(_format text) (_format text)
(_timespec "2024-04-23T19:53:08")
(_timespec "2024-04-25T16:38:35")
) )
(_file "device_map/Top.dmr" (_file "device_map/Top.dmr"
(_format text) (_format text)
(_timespec "2024-04-23T19:53:15")
(_timespec "2024-04-25T16:38:36")
) )
(_file "device_map/dmr.db" (_file "device_map/dmr.db"
(_format text) (_format text)
(_timespec "2024-04-23T19:53:16")
(_timespec "2024-04-25T16:38:37")
) )
) )
) )
@ -363,7 +363,7 @@
(_input (_input
(_file "device_map/camera_light_src_timing_controller_fpga.pcf" (_file "device_map/camera_light_src_timing_controller_fpga.pcf"
(_format pcf) (_format pcf)
(_timespec "2024-04-23T19:53:15")
(_timespec "2024-04-25T16:38:36")
) )
) )
) )
@ -378,33 +378,33 @@
(_db_output (_db_output
(_file "place_route/Top_pnr.adf" (_file "place_route/Top_pnr.adf"
(_format adif) (_format adif)
(_timespec "2024-04-23T19:56:41")
(_timespec "2024-04-25T16:41:20")
) )
) )
(_output (_output
(_file "place_route/Top.prr" (_file "place_route/Top.prr"
(_format text) (_format text)
(_timespec "2024-04-23T19:56:41")
(_timespec "2024-04-25T16:41:20")
) )
(_file "place_route/Top_prr.prt" (_file "place_route/Top_prr.prt"
(_format text) (_format text)
(_timespec "2024-04-23T19:56:39")
(_timespec "2024-04-25T16:41:18")
) )
(_file "place_route/clock_utilization.txt" (_file "place_route/clock_utilization.txt"
(_format text) (_format text)
(_timespec "2024-04-23T19:56:40")
(_timespec "2024-04-25T16:41:18")
) )
(_file "place_route/Top_plc.adf" (_file "place_route/Top_plc.adf"
(_format adif) (_format adif)
(_timespec "2024-04-23T19:54:03")
(_timespec "2024-04-25T16:39:01")
) )
(_file "place_route/Top_pnr.netlist" (_file "place_route/Top_pnr.netlist"
(_format text) (_format text)
(_timespec "2024-04-23T19:56:41")
(_timespec "2024-04-25T16:41:20")
) )
(_file "place_route/prr.db" (_file "place_route/prr.db"
(_format text) (_format text)
(_timespec "2024-04-23T19:56:42")
(_timespec "2024-04-25T16:41:21")
) )
) )
) )
@ -439,19 +439,19 @@
(_output (_output
(_file "generate_bitstream/Top.sbit" (_file "generate_bitstream/Top.sbit"
(_format text) (_format text)
(_timespec "2024-04-23T19:57:53")
(_timespec "2024-04-25T16:42:03")
) )
(_file "generate_bitstream/Top.smsk" (_file "generate_bitstream/Top.smsk"
(_format text) (_format text)
(_timespec "2024-04-23T19:57:53")
(_timespec "2024-04-25T16:42:03")
) )
(_file "generate_bitstream/Top.bgr" (_file "generate_bitstream/Top.bgr"
(_format text) (_format text)
(_timespec "2024-04-23T19:57:53")
(_timespec "2024-04-25T16:42:03")
) )
(_file "generate_bitstream/bgr.db" (_file "generate_bitstream/bgr.db"
(_format text) (_format text)
(_timespec "2024-04-23T19:57:55")
(_timespec "2024-04-25T16:42:04")
) )
) )
) )

10
pin.csv
View File

@ -7,11 +7,11 @@ R18,spi_rx_pin,INPUT
L17,uart_tx,OUTPUT L17,uart_tx,OUTPUT
L18,uart_rx,INPUT L18,uart_rx,INPUT
T11,core_board_debug_led,OUTPUT T11,core_board_debug_led,OUTPUT
M16,id[0],INPUT
L16,id[1],INPUT
J18,id[2],INPUT
J17,id[3],INPUT
E15,id[4],INPUT
M16,tmp_contrl_pin[0],OUTPUT
L16,tmp_contrl_pin[1],OUTPUT
J18,tmp_contrl_pin[2],OUTPUT
J17,tmp_contrl_pin[3],OUTPUT
E15,tmp_contrl_pin[4],OUTPUT
M18,stm32_output_bus[0],OUTPUT M18,stm32_output_bus[0],OUTPUT
K18,stm32_output_bus[1],OUTPUT K18,stm32_output_bus[1],OUTPUT
K17,stm32_output_bus[2],OUTPUT K17,stm32_output_bus[2],OUTPUT

BIN
release/v4/Top.sbit
View File

BIN
release/v4/Top.sfc
View File

BIN
release/v5/Top.sbit
View File

BIN
release/v5/Top.sfc
View File

2
source/src/config.v
View File

@ -1,4 +1,4 @@
`define REGADDOFF__FPGA_VERSION 32'd4
`define REGADDOFF__FPGA_VERSION 32'd5
/******************************************************************************* /*******************************************************************************
* 寄存器地址分配 * * 寄存器地址分配 *
*******************************************************************************/ *******************************************************************************/

8
source/src/top.v
View File

@ -14,7 +14,7 @@ module Top (
input wire uart_rx, input wire uart_rx,
input wire [4:0] id,
output wire [4:0] tmp_contrl_pin,
output wire core_board_debug_led, output wire core_board_debug_led,
@ -102,8 +102,12 @@ module Top (
localparam SYS_CLOCK_FREQ = 100000000; localparam SYS_CLOCK_FREQ = 100000000;
assign sys_clk = sys_clk_100m; assign sys_clk = sys_clk_100m;
assign sys_rst_n = stm32_input_bus[0] & pll_lock; assign sys_rst_n = stm32_input_bus[0] & pll_lock;
// assign sys_rst_n = pll_lock;
assign tmp_contrl_pin[0] = !sys_rst_n;
assign tmp_contrl_pin[1] = !sys_rst_n;
assign tmp_contrl_pin[2] = !sys_rst_n;
assign tmp_contrl_pin[3] = !sys_rst_n;
assign tmp_contrl_pin[4] = !sys_rst_n;
wire [31:0] rd_data_fpga_info; wire [31:0] rd_data_fpga_info;
wire [31:0] rd_data_internal_clk; wire [31:0] rd_data_internal_clk;

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