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调整测试输出

master
zhaohe 1 year ago
parent
14aee36022
commit
f91c99b4c1
2 changed files with 38 additions and 35 deletions
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  1. 50
      camera_light_src_timing_controller_fpga.pds
  2. 23
      source/src/top.v

50
camera_light_src_timing_controller_fpga.pds
View File

@ -1,5 +1,5 @@
(_flow fab_demo "2021.1-SP7" (_flow fab_demo "2021.1-SP7"
(_comment "Generated by Fabric Compiler (version on 2021.1-SP7<build 86875>) at Tue May 7 10:48:58 2024")
(_comment "Generated by Fabric Compiler (version on 2021.1-SP7<build 86875>) at Tue May 7 11:00:42 2024")
(_version "1.0.5") (_version "1.0.5")
(_status "initial") (_status "initial")
(_project (_project
@ -19,7 +19,7 @@
(_input (_input
(_file "source/src/top.v" + "Top:" (_file "source/src/top.v" + "Top:"
(_format verilog) (_format verilog)
(_timespec "2024-05-07T10:45:38")
(_timespec "2024-05-07T10:58:09")
) )
(_file "source/src/spi_reg_reader.v" (_file "source/src/spi_reg_reader.v"
(_format verilog) (_format verilog)
@ -279,17 +279,17 @@
(_db_output (_db_output
(_file "compile/Top_comp.adf" (_file "compile/Top_comp.adf"
(_format adif) (_format adif)
(_timespec "2024-05-07T10:47:19")
(_timespec "2024-05-07T10:58:33")
) )
) )
(_output (_output
(_file "compile/Top.cmr" (_file "compile/Top.cmr"
(_format verilog) (_format verilog)
(_timespec "2024-05-07T10:47:16")
(_timespec "2024-05-07T10:58:30")
) )
(_file "compile/cmr.db" (_file "compile/cmr.db"
(_format text) (_format text)
(_timespec "2024-05-07T10:47:19")
(_timespec "2024-05-07T10:58:33")
) )
) )
) )
@ -305,21 +305,21 @@
(_db_output (_db_output
(_file "synthesize/Top_syn.adf" (_file "synthesize/Top_syn.adf"
(_format adif) (_format adif)
(_timespec "2024-05-07T10:47:41")
(_timespec "2024-05-07T10:58:57")
) )
) )
(_output (_output
(_file "synthesize/Top_syn.vm" (_file "synthesize/Top_syn.vm"
(_format structural_verilog) (_format structural_verilog)
(_timespec "2024-05-07T10:47:43")
(_timespec "2024-05-07T10:58:59")
) )
(_file "synthesize/Top.snr" (_file "synthesize/Top.snr"
(_format text) (_format text)
(_timespec "2024-05-07T10:47:45")
(_timespec "2024-05-07T10:59:01")
) )
(_file "synthesize/snr.db" (_file "synthesize/snr.db"
(_format text) (_format text)
(_timespec "2024-05-07T10:47:45")
(_timespec "2024-05-07T10:59:01")
) )
) )
) )
@ -340,21 +340,21 @@
(_db_output (_db_output
(_file "device_map/Top_map.adf" (_file "device_map/Top_map.adf"
(_format adif) (_format adif)
(_timespec "2024-05-07T10:47:51")
(_timespec "2024-05-07T10:59:07")
) )
) )
(_output (_output
(_file "device_map/Top_dmr.prt" (_file "device_map/Top_dmr.prt"
(_format text) (_format text)
(_timespec "2024-05-07T10:47:48")
(_timespec "2024-05-07T10:59:04")
) )
(_file "device_map/Top.dmr" (_file "device_map/Top.dmr"
(_format text) (_format text)
(_timespec "2024-05-07T10:47:51")
(_timespec "2024-05-07T10:59:07")
) )
(_file "device_map/dmr.db" (_file "device_map/dmr.db"
(_format text) (_format text)
(_timespec "2024-05-07T10:47:51")
(_timespec "2024-05-07T10:59:07")
) )
) )
) )
@ -363,7 +363,7 @@
(_input (_input
(_file "device_map/camera_light_src_timing_controller_fpga.pcf" (_file "device_map/camera_light_src_timing_controller_fpga.pcf"
(_format pcf) (_format pcf)
(_timespec "2024-05-07T10:47:51")
(_timespec "2024-05-07T10:59:07")
) )
) )
) )
@ -378,33 +378,33 @@
(_db_output (_db_output
(_file "place_route/Top_pnr.adf" (_file "place_route/Top_pnr.adf"
(_format adif) (_format adif)
(_timespec "2024-05-07T10:48:36")
(_timespec "2024-05-07T11:00:20")
) )
) )
(_output (_output
(_file "place_route/Top.prr" (_file "place_route/Top.prr"
(_format text) (_format text)
(_timespec "2024-05-07T10:48:37")
(_timespec "2024-05-07T11:00:20")
) )
(_file "place_route/Top_prr.prt" (_file "place_route/Top_prr.prt"
(_format text) (_format text)
(_timespec "2024-05-07T10:48:36")
(_timespec "2024-05-07T11:00:19")
) )
(_file "place_route/clock_utilization.txt" (_file "place_route/clock_utilization.txt"
(_format text) (_format text)
(_timespec "2024-05-07T10:48:36")
(_timespec "2024-05-07T11:00:19")
) )
(_file "place_route/Top_plc.adf" (_file "place_route/Top_plc.adf"
(_format adif) (_format adif)
(_timespec "2024-05-07T10:48:06")
(_timespec "2024-05-07T10:59:36")
) )
(_file "place_route/Top_pnr.netlist" (_file "place_route/Top_pnr.netlist"
(_format text) (_format text)
(_timespec "2024-05-07T10:48:37")
(_timespec "2024-05-07T11:00:20")
) )
(_file "place_route/prr.db" (_file "place_route/prr.db"
(_format text) (_format text)
(_timespec "2024-05-07T10:48:37")
(_timespec "2024-05-07T11:00:20")
) )
) )
) )
@ -439,19 +439,19 @@
(_output (_output
(_file "generate_bitstream/Top.sbit" (_file "generate_bitstream/Top.sbit"
(_format text) (_format text)
(_timespec "2024-05-07T10:48:57")
(_timespec "2024-05-07T11:00:41")
) )
(_file "generate_bitstream/Top.smsk" (_file "generate_bitstream/Top.smsk"
(_format text) (_format text)
(_timespec "2024-05-07T10:48:57")
(_timespec "2024-05-07T11:00:41")
) )
(_file "generate_bitstream/Top.bgr" (_file "generate_bitstream/Top.bgr"
(_format text) (_format text)
(_timespec "2024-05-07T10:48:57")
(_timespec "2024-05-07T11:00:41")
) )
(_file "generate_bitstream/bgr.db" (_file "generate_bitstream/bgr.db"
(_format text) (_format text)
(_timespec "2024-05-07T10:48:58")
(_timespec "2024-05-07T11:00:41")
) )
) )
) )

23
source/src/top.v
View File

@ -499,18 +499,21 @@ module Top (
assign debug_bus[0] = diff_in1; assign debug_bus[0] = diff_in1;
assign debug_bus[1] = optocoupler_in1; assign debug_bus[1] = optocoupler_in1;
assign debug_bus[2] = diff_in2;
assign debug_bus[3] = optocoupler_in2;
assign debug_bus[4] = diff_in3;
assign debug_bus[5] = optocoupler_in3;
assign debug_bus[6] = diff_in4;
assign debug_bus[7] = optocoupler_in4;
assign debug_bus[8] = sig_bus[`SIG_EXT_TRIGGER_1];
assign debug_bus[9] = sig_bus[`SIG_EXT_TRIGGER_2];
assign debug_bus[10] = sig_bus[`SIG_EXT_TRIGGER_3];
assign debug_bus[2] = sig_bus[`SIG_EXT_TRIGGER_1];
assign debug_bus[3] = diff_in2;
assign debug_bus[4] = optocoupler_in2;
assign debug_bus[5] = sig_bus[`SIG_EXT_TRIGGER_2];
assign debug_bus[6] = diff_in3;
assign debug_bus[7] = optocoupler_in3;
assign debug_bus[8] = sig_bus[`SIG_EXT_TRIGGER_3];
assign debug_bus[9] = diff_in4;
assign debug_bus[10] = optocoupler_in4;
assign debug_bus[11] = sig_bus[`SIG_EXT_TRIGGER_4]; assign debug_bus[11] = sig_bus[`SIG_EXT_TRIGGER_4];
assign debug_bus[12] = diff_out1;
assign debug_bus[12] = diff_out1;
assign debug_bus[13] = diff_out2; assign debug_bus[13] = diff_out2;
assign debug_bus[14] = diff_out3; assign debug_bus[14] = diff_out3;
assign debug_bus[15] = diff_out4; assign debug_bus[15] = diff_out4;

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