4 changed files with 53 additions and 88 deletions
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85README.md
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56camera_light_src_timing_controller_fpga.pds
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BINrelease/v2.0/Top.sbit
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BINrelease/v2.0/Top.sfc
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``` |
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https://iflytop1.feishu.cn/docx/Fk3CdIRNZoal1XxCGgjc9q1Dn1f |
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``` |
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``` |
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注意事项: |
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倍频和分频的前提建立在输入频率稳定的情况才有效的。如果输入频率在+-一定范围内变化,输出波形可能会出现异常 |
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``` |
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``` |
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核心板引脚分配: |
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define_attribute {p:rst_n} {PAP_IO_DIRECTION} {INPUT} |
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define_attribute {p:rst_n} {PAP_IO_LOC} {U12} |
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define_attribute {p:rst_n} {PAP_IO_VCCIO} {3.3} |
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define_attribute {p:rst_n} {PAP_IO_STANDARD} {LVTTL33} |
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define_attribute {p:sys_clk} {PAP_IO_DIRECTION} {INPUT} |
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define_attribute {p:sys_clk} {PAP_IO_LOC} {B5} |
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define_attribute {p:sys_clk} {PAP_IO_VCCIO} {3.3} |
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define_attribute {p:sys_clk} {PAP_IO_STANDARD} {LVTTL33} |
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``` |
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``` |
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TTL OUTPUT |
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1,2,3,4 丝印正确,正常输出 |
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``` |
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``` |
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SIGNAL_GENERATOR |
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启动方式: |
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1.寄存器控制启动 |
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2.外部触发启动 |
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3.TIMECODE触发启动 |
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帧格式: |
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TIMECODE: |
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25/30/... |
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GENLOCK: |
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.... |
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产生: |
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1.start_state_sig (高电平表示拍照进行中) |
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2.timecode_sig[64] |
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3.timecode_tirgger_sig[1] |
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4.genlock_sig[1] 帧信号,场信号 |
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5.秒信号 |
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TTL_INPUT |
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TIMECODE_INPUT |
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TIMECODE_OUTPUT |
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GENLOCK_INPUT |
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``` |
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``` |
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1. 修改启动方式 |
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2. 修改TIMECODE启动时间戳 |
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``` |
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``` |
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// timeocde[0->63] |
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// 0 1 2 3 4 5 6 7 |
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// 帧秒分时 U0U1U2U3 |
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``` |
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``` |
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插件: |
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Documenter - TerosHDL 0.1.4 documentation |
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Verilog-HDL/SystemVerilog/Bluespec SystemVerilog |
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``` |
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