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update release

master
zhaohe 1 year ago
parent
commit
fce07472f9
  1. 85
      README.md
  2. 56
      camera_light_src_timing_controller_fpga.pds
  3. BIN
      release/v2.0/Top.sbit
  4. BIN
      release/v2.0/Top.sfc

85
README.md

@ -1,85 +0,0 @@
```
https://iflytop1.feishu.cn/docx/Fk3CdIRNZoal1XxCGgjc9q1Dn1f
```
```
注意事项:
倍频和分频的前提建立在输入频率稳定的情况才有效的。如果输入频率在+-一定范围内变化,输出波形可能会出现异常
```
```
核心板引脚分配:
define_attribute {p:rst_n} {PAP_IO_DIRECTION} {INPUT}
define_attribute {p:rst_n} {PAP_IO_LOC} {U12}
define_attribute {p:rst_n} {PAP_IO_VCCIO} {3.3}
define_attribute {p:rst_n} {PAP_IO_STANDARD} {LVTTL33}
define_attribute {p:sys_clk} {PAP_IO_DIRECTION} {INPUT}
define_attribute {p:sys_clk} {PAP_IO_LOC} {B5}
define_attribute {p:sys_clk} {PAP_IO_VCCIO} {3.3}
define_attribute {p:sys_clk} {PAP_IO_STANDARD} {LVTTL33}
```
```
TTL OUTPUT
1,2,3,4 丝印正确,正常输出
```
```
SIGNAL_GENERATOR
启动方式:
1.寄存器控制启动
2.外部触发启动
3.TIMECODE触发启动
帧格式:
TIMECODE:
25/30/...
GENLOCK:
....
产生:
1.start_state_sig (高电平表示拍照进行中)
2.timecode_sig[64]
3.timecode_tirgger_sig[1]
4.genlock_sig[1] 帧信号,场信号
5.秒信号
TTL_INPUT
TIMECODE_INPUT
TIMECODE_OUTPUT
GENLOCK_INPUT
```
```
1. 修改启动方式
2. 修改TIMECODE启动时间戳
```
```
// timeocde[0->63]
// 0 1 2 3 4 5 6 7
// 帧秒分时 U0U1U2U3
```
```
插件:
Documenter - TerosHDL 0.1.4 documentation
Verilog-HDL/SystemVerilog/Bluespec SystemVerilog
```

56
camera_light_src_timing_controller_fpga.pds

@ -1,5 +1,5 @@
(_flow fab_demo "2021.1-SP7" (_flow fab_demo "2021.1-SP7"
(_comment "Generated by Fabric Compiler (version on 2021.1-SP7<build 86875>) at Mon Mar 11 15:59:04 2024")
(_comment "Generated by Fabric Compiler (version on 2021.1-SP7<build 86875>) at Mon Mar 11 16:07:30 2024")
(_version "1.0.5") (_version "1.0.5")
(_status "initial") (_status "initial")
(_project (_project
@ -373,8 +373,40 @@
) )
(_task tsk_pnr (_task tsk_pnr
(_command cmd_pnr (_command cmd_pnr
(_gci_state (_integer 0))
(_gci_state (_integer 2))
(_option mode (_string "fast")) (_option mode (_string "fast"))
(_db_output
(_file "place_route/Top_pnr.adf"
(_format adif)
(_timespec "2024-03-11T16:06:31")
)
)
(_output
(_file "place_route/Top.prr"
(_format text)
(_timespec "2024-03-11T16:06:31")
)
(_file "place_route/Top_prr.prt"
(_format text)
(_timespec "2024-03-11T16:06:29")
)
(_file "place_route/clock_utilization.txt"
(_format text)
(_timespec "2024-03-11T16:06:29")
)
(_file "place_route/Top_plc.adf"
(_format adif)
(_timespec "2024-03-11T15:59:49")
)
(_file "place_route/Top_pnr.netlist"
(_format text)
(_timespec "2024-03-11T16:06:31")
)
(_file "place_route/prr.db"
(_format text)
(_timespec "2024-03-11T16:06:32")
)
)
) )
(_widget wgt_power_calculator (_widget wgt_power_calculator
(_attribute _click_to_run (_switch ON)) (_attribute _click_to_run (_switch ON))
@ -403,7 +435,25 @@
) )
(_task tsk_gen_bitstream (_task tsk_gen_bitstream
(_command cmd_gen_bitstream (_command cmd_gen_bitstream
(_gci_state (_integer 0))
(_gci_state (_integer 2))
(_output
(_file "generate_bitstream/Top.sbit"
(_format text)
(_timespec "2024-03-11T16:07:28")
)
(_file "generate_bitstream/Top.smsk"
(_format text)
(_timespec "2024-03-11T16:07:29")
)
(_file "generate_bitstream/Top.bgr"
(_format text)
(_timespec "2024-03-11T16:07:29")
)
(_file "generate_bitstream/bgr.db"
(_format text)
(_timespec "2024-03-11T16:07:30")
)
)
) )
) )
) )

BIN
release/v2.0/Top.sbit

BIN
release/v2.0/Top.sfc

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