Pango 021001 PLL Logos PLL 1.5 ttl_pll Logos PGL22G MBG324 -6 IP Compiler

STATIC_DUTY2_basicPage 16 CLKOUT2_EN_advancedPage false FEEDBACK_DELAY_VALUE_basicPage 0.000 3 DEVICE_PGL35 false CLKOUT0_GATE_EN_advancedPage false CLK_CAS1_EN_advancedPage false STATIC_RATIO4_basicPage 16 CLKOUT0_EN_basicPage true STATIC_DUTYF_basicPage 24 CLKIN_BYPASS_EN_basicPage false CLK_CAS4_EN_basicPage false CLK_CAS4_EN_advancedPage false CLKOUT1_REQ_FREQ_basicPage 50.0000 4 FBMODE_advancedPage false CLKOUT2_REQ_DUTY_basicPage 50.0000 4 STATIC_DUTY3_advancedPage 16 CLKOUT1_REQ_PHASE_basicPage 0.0000 4 CLKOUT0_EXT_GATE_EN_basicPage false STATIC_DUTY1_basicPage 16 FBMODE_basicPage false CLKOUT1_EN_basicPage false CLKOUT0_REQ_PHASE_basicPage 0.0000 4 CLK_CAS2_EN_advancedPage false DYNAMIC_LOOP_EN_advancedPage false STATIC_DUTY2_advancedPage 16 CLKOUT0_EXT_GATE_EN_advancedPage false FBDIV_SEL_advancedPage 0 CLKOUT1_GATE_EN_basicPage false DYNAMIC_RATIOI_EN_advancedPage false DYNAMIC_RATIOM_EN_advancedPage false MODE false CLKOUT4_GATE_EN_advancedPage false STATIC_PHASE0_advancedPage 16 DYNAMIC_PHASE3_EN_advancedPage false LOOP_MAPPING_EN_advancedPage false CLKIN_SEL_ENABLE_advancedPage false DYNAMIC_DUTY1_EN_advancedPage false STATIC_PHASE1_advancedPage 16 DYNAMIC_PHASE4_EN_advancedPage false PFDEN_EN_advancedPage false DEVICE_PGL22 true STATIC_RATIOM_basicPage 1 FB_MODE_advancedPage 0 STATIC_RATIO2_basicPage 16 CLKIN_SEL_ENABLE_basicPage false CLKOUT5_SEL_advancedPage 0 CLKSWITCH_FLAG_ENABLE_advancedPage false DEVICE_PGL12 false STATIC_PHASE4_basicPage 16 SHOW_SETTING_EN_basicPage false STATIC_PHASE3_basicPage 16 FBDIV_SEL_basicPage 0 STATIC_RATIO3_basicPage 16 STATIC_RATIOM_advancedPage 1 STATIC_DUTY4_basicPage 16 CLKOUT4_EN_basicPage false CLKOUT0_REQ_FREQ_basicPage 50.0000 4 CLK_CAS3_EN_advancedPage false STATIC_RATIOF_basicPage 24 FEEDBACK_DELAY_ENABLE_advancedPage false DYNAMIC_RATIO3_EN_advancedPage false FEEDBACK_DELAY_ENABLE_basicPage false STATIC_DUTY0_advancedPage 16 STATIC_DUTY1_advancedPage 16 CLKOUT0_GATE_EN_basicPage false RST_ENABLE_basicPage false DYNAMIC_RATIO1_EN_advancedPage false CLKOUT5_GATE_EN_advancedPage false CLKOUT3_REQ_DUTY_basicPage 50.0000 4 STATIC_PHASE2_basicPage 16 CLKOUT2_GATE_EN_advancedPage false CLKOUT1_GATE_EN_advancedPage false CLKOUT5_EN_advancedPage false CLKOUT4_EN_advancedPage false VCODIV2_ENABLE_advancedPage false DYNAMIC_CLKIN_EN_advancedPage false STATIC_RATIO1_advancedPage 16 RST_ENABLE_advancedPage false CLKIN_FREQ_advancedPage 50.0000 4 STATIC_DUTY3_basicPage 16 STATIC_RATIO0_basicPage 12 STATIC_PHASE2_advancedPage 16 PLL_PWD_ENABLE_basicPage false STATIC_PHASE1_basicPage 16 DYNAMIC_DUTY3_EN_advancedPage false RSTODIV_ENABLE_advancedPage false DYNAMIC_RATIOF_EN_advancedPage false CLKOUT4_GATE_EN_basicPage false CLKOUT4_REQ_PHASE_basicPage 0.0000 4 CLKOUT3_EN_advancedPage false STATIC_DUTY0_basicPage 12 DYNAMIC_DUTY4_EN_advancedPage false PLL_PWD_ENABLE_advancedPage false CLKOUT3_REQ_FREQ_basicPage 50.0000 4 STATIC_RATIO0_advancedPage 16 FB_MODE_basicPage 0 DYNAMIC_RATIO0_EN_advancedPage false STATIC_PHASE4_advancedPage 16 DYNAMIC_PHASE0_EN_advancedPage false CLKOUT3_GATE_EN_basicPage false DYNAMIC_PHASE1_EN_advancedPage false STATIC_RATIOI_advancedPage 2 CLKOUT2_EN_basicPage false BANDWIDTH_advancedPage OPTIMIZED CLKOUT4_REQ_DUTY_basicPage 50.0000 4 CLKOUT3_EN_basicPage false CLKOUT2_REQ_PHASE_basicPage 0.0000 4 STATIC_RATIO2_advancedPage 16 STATIC_DUTY4_advancedPage 16 STATIC_RATIOF_advancedPage 16 CLK_CAS3_EN_basicPage false STATIC_PHASE3_advancedPage 16 CLKOUT0_EXT_EN_basicPage false CLKOUT0_EN_advancedPage true STATIC_PHASE0_basicPage 16 STATIC_RATIOI_basicPage 2 CLKIN_BYPASS_EN_advancedPage false CLKOUT1_EN_advancedPage false STATIC_RATIO3_advancedPage 16 CLKOUT3_REQ_PHASE_basicPage 0.0000 4 DYNAMIC_DUTY2_EN_advancedPage false CLKOUT2_REQ_FREQ_basicPage 50.0000 4 CLKOUT0_REQ_DUTY_basicPage 50.0000 4 CLKOUT0_EXT_EN_advancedPage false CLKIN_SEL_EN_ENABLE_basicPage false CLKIN_SEL_EN_ENABLE_advancedPage false DYNAMIC_PHASE_EN_advancedPage false CLK_CAS2_EN_basicPage false CLKOUT3_GATE_EN_advancedPage false FEEDBACK_DELAY_VALUE_advancedPage 0.000 3 CLKSWITCH_FLAG_ENABLE_basicPage false CLKOUT1_REQ_DUTY_basicPage 50.0000 4 BANDWIDTH_basicPage OPTIMIZED CLK_CAS1_EN_basicPage false DYNAMIC_PHASE2_EN_advancedPage false STATIC_RATIO1_basicPage 16 STATIC_RATIO4_advancedPage 16 CLKOUT4_REQ_FREQ_basicPage 50.0000 4 CLKIN_FREQ_basicPage 50.0000 4 CLKOUT2_GATE_EN_basicPage false DYNAMIC_RATIO2_EN_advancedPage false DYNAMIC_DUTY0_EN_advancedPage false DYNAMIC_CLKIN_EN_basicPage false MODE_CFG 0 DYNAMIC_RATIO4_EN_advancedPage false clkin1 clkin1 input left pll_lock pll_lock output right clkout0 clkout0 output right