module zutils_trigger_sig_gen (
    input clk,   //clock input
    input rst_n, //asynchronous reset input, low active


    input        start_sig,
    input        stop_sig,
    input [31:0] cfg_freq_cnt,
    input [31:0] cfg_pluse_cnt,

    output reg output_signal
);

  reg [31:0] cfg_freq_cnt_cache;
  reg [31:0] cfg_pluse_cnt_cache;

  reg        work_state;

  reg [31:0] freq_cnt;
  reg [31:0] pluse_cnt;
  reg        first_start;

  always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
      cfg_freq_cnt_cache  <= 0;
      cfg_pluse_cnt_cache <= 0;
      work_state          <= 0;
      work_state          <= 0;
      freq_cnt            <= 0;
      pluse_cnt           <= 0;
      output_signal       <= 0;
      first_start         <= 1;

    end else begin
      case (work_state)
        0: begin
          if (start_sig || first_start) begin
            work_state          <= 1;
            cfg_freq_cnt_cache  <= cfg_freq_cnt;
            cfg_pluse_cnt_cache <= cfg_pluse_cnt_cache;
            freq_cnt            <= 0;
            pluse_cnt           <= 0;
            output_signal       <= 0;
            first_start         <= 0;
          end else begin
            output_signal <= 0;
          end
        end
        1: begin

          if (!stop_sig) begin
            if (freq_cnt >= cfg_freq_cnt_cache) begin
              freq_cnt      <= 0;
              output_signal <= 1;

              if (cfg_pluse_cnt_cache != 0) begin
                if (pluse_cnt == cfg_pluse_cnt_cache - 1) begin
                  work_state <= 0;
                end else begin
                  pluse_cnt <= pluse_cnt + 1;
                end
              end
            end else begin
              freq_cnt      <= freq_cnt + 1;
              output_signal <= 0;
            end
          end else begin
            work_state <= 0;
          end



        end
        default: work_state <= 0;
      endcase
    end
  end


endmodule