`include "config.v"
/*
 * Hacky baud rate generator to divide a 50MHz clock into a 115200 baud
 * rx/tx pair where the rx clcken oversamples by 16x.
 */
module rd_data_router (
    input [31:0] addr,

    input [31:0] stm32_rd_data,
    input [31:0] fpga_test_rd_data,
    input [31:0] control_sensor_rd_data,
    input [31:0] ttlin1_rd_data,
    input [31:0] ttlin2_rd_data,
    input [31:0] ttlin3_rd_data,
    input [31:0] ttlin4_rd_data,
    input [31:0] timecode_in_rd_data,
    input [31:0] genlock_in_rd_data,
    input [31:0] ttlout1_rd_data,
    input [31:0] ttlout2_rd_data,
    input [31:0] ttlout3_rd_data,
    input [31:0] ttlout4_rd_data,
    input [31:0] timecode_out_rd_data,
    input [31:0] genlock_out_rd_data,
    input [31:0] stm32_if_rd_data,
    input [31:0] debuger_rd_data,

    output reg [31:0] rd_data_out
);



  always @(*) begin
    case (addr >> 8)
      `REG_ADD_OFF_STM32 >> 8: rd_data_out = stm32_rd_data;
      `REG_ADD_OFF_FPGA_TEST >> 8: rd_data_out = fpga_test_rd_data;
      `REG_ADD_OFF_CONTROL_SENSOR >> 8: rd_data_out = control_sensor_rd_data;
      `REG_ADD_OFF_TTLIN1 >> 8: rd_data_out = ttlin1_rd_data;
      `REG_ADD_OFF_TTLIN2 >> 8: rd_data_out = ttlin2_rd_data;
      `REG_ADD_OFF_TTLIN3 >> 8: rd_data_out = ttlin3_rd_data;
      `REG_ADD_OFF_TTLIN4 >> 8: rd_data_out = ttlin4_rd_data;
      `REG_ADD_OFF_TIMECODE_IN >> 8: rd_data_out = timecode_in_rd_data;
      `REG_ADD_OFF_GENLOCK_IN >> 8: rd_data_out = genlock_in_rd_data;
      `REG_ADD_OFF_TTLOUT1 >> 8: rd_data_out = ttlout1_rd_data;
      `REG_ADD_OFF_TTLOUT2 >> 8: rd_data_out = ttlout2_rd_data;
      `REG_ADD_OFF_TTLOUT3 >> 8: rd_data_out = ttlout3_rd_data;
      `REG_ADD_OFF_TTLOUT4 >> 8: rd_data_out = ttlout4_rd_data;
      `REG_ADD_OFF_TIMECODE_OUT >> 8: rd_data_out = timecode_out_rd_data;
      `REG_ADD_OFF_GENLOCK_OUT >> 8: rd_data_out = genlock_out_rd_data;
      `REG_ADD_OFF_STM32_IF >> 8: rd_data_out = stm32_if_rd_data;
      `REG_ADD_OFF_DEBUGER >> 8: rd_data_out = debuger_rd_data;
      default: rd_data_out = 0;
    endcase
  end

endmodule