module zutils_reset_sig_gen (
    input      clk,       //clock input
    input      rst_n,     //asynchronous reset input, low active
    output reg rst_n_out
);
  reg [31:0] counter = 0;

  always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
      counter   <= 0;
      rst_n_out <= 0;
    end else begin
      if (counter < 10) begin
        rst_n_out <= 0;
        counter   <= counter + 1;
      end else if (counter == 10) begin
        counter   <= counter;
        rst_n_out <= 1;
      end
    end
  end
endmodule